summaryrefslogtreecommitdiff
path: root/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts
blob: fd7274eb7aaa5a8cd857cacc86cfccea9b994e8f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 Linaro
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "imx8mm-pinfunc.h"

&{/} {
	clocks {
		#address-cells = <1>;
		#size-cells = <0>;
		clk40m: clk@1 {
			compatible = "fixed-clock";
			reg = <1>;
			#clock-cells = <0>;
			clock-frequency = <40000000>;
			clock-output-names = "clk40m";
		};
	};
};

&ecspi3 {
	#address-cells = <1>;
	#size-cells = <0>;

	can1: can@0 {
		compatible = "microchip,mcp2518fd";
		reg = <0>;
		microchip,rx-int = <&gpio5 28 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can1>;
		interrupt-parent = <&gpio5>;
		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
		spi-max-frequency = <20000000>;
		clocks = <&clk40m>;
		status = "okay";
	};
};

&iomuxc {
	pinctrl_can1: can1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x00
			MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28	0x00
		>;
	};
};