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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019, 2021 NXP
*/
#include "imx8mp-sec-def.h"
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
mcu_rdc {
compatible = "imx8m,mcu_rdc";
/* rdc config when MCU starts
* master
* SDMA3p --> domain 1
* SDMA3b --> domian 1
* SDMA3_SPBA2 --> domian 1
* peripheral:
* SAI3 --> Only Domian 1 can access
* UART4 --> Only Domian 1 can access
* GPT1 --> Only Domian 1 can access
* SDMA3 --> Only Domian 1 can access
* I2C3 --> Only Domian 1 can access
* memory:
* TCM --> Only Domian 1 can access (0x7E0000~0x81FFFF)
* DDR --> Only Domian 1 can access (0x80000000~0x81000000)
* end.
*/
start-config = <
RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0
RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0
RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0
RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0
RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS
RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS
0x0 0x0 0x0 0x0 0x0
>;
/* rdc config when MCU stops
* memory:
* TCM --> domain 0/1 can access (0x7E0000~0x81FFFF)
* DDR --> domain 0/1 can access (0x80000000~0x81000000)
* end.
*/
stop-config = <
RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS
RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS
0x0 0x0 0x0 0x0 0x0
>;
};
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
};
®_usdhc2_vmmc {
u-boot,dm-spl;
u-boot,off-on-delay-us = <20000>;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&wdog1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&eqos {
compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
ðphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&flexspi {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&lcdif1 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&mipi_dsi {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&usb3_0 {
/delete-property/ power-domains;
};
&usb3_1 {
/delete-property/ power-domains;
};
&usb_dwc3_0 {
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>;
};
&usb_dwc3_1 {
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>;
};
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