diff options
| author | Bai Ping <b51503@freescale.com> | 2015-06-12 01:02:43 +0800 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-06-12 19:30:38 +0800 |
| commit | 34ff6ab4e6af5e87eb3edc0420b204bf09e859e6 (patch) | |
| tree | 2f3b98c391bf240d77bc4c630b36c7c4a381427d | |
| parent | d40d224c1db101382b14753520aa3408715380e3 (diff) | |
MLK-11092 ARM: imx6: set pl310 l2 cache prefetch offset to zero
Set the L2 cache prefetch offset to zero due to the
system instability issue.
Signed-off-by: Bai Ping <b51503@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/system.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 56693366f55b..a428edf37268 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -155,7 +155,7 @@ void __init imx_init_l2cache(void) /* Configure the L2 PREFETCH and POWER registers */ /* Set prefetch offset with any value except 23 as per errata 765569 */ val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); - val |= 0x7000000f; + val |= 0x70000000; /* * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP |