diff options
| author | Philippe Schenker <philippe.schenker@toradex.com> | 2021-11-23 17:15:59 +0100 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2021-11-25 08:44:44 +0000 |
| commit | 96257d74c674794165997e3a1e997ae5178f23c7 (patch) | |
| tree | 55bcd954ac784313899557bf76402900fb79ddcb | |
| parent | fee494b82862c4098d4b1232f0db55ee917055ad (diff) | |
ARM64: dts: verdin-imx8mp: dev-board: limit usdhc2 clock
Limit the USDHC2 clock to 100MHz as with certain SDIO cards the clock
frequency cannot go higher without being distorted.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index 31885fe7f7d5..dfe66386261e 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -73,6 +73,11 @@ }; }; +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; + &wm8904_1a { status = "disabled"; }; |