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2012-02-22ENGR00174734-3 usb: change function name for discharge data linerel_imx_3.0.15_12.02.013.0-imx6-12.02.01-201202221138Peter Chen
In order to reflect the function well, it needs to discharge both dp and dm, so change the function name. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-22ENGR00174734-2 usb: fix bugs that dp and dm are floating at device modePeter Chen
At i.mx6x, the data line (dp and dm) are floating at device mode, that is to say data line will be any values (0-3.6v). So if the usb wakeup is enabled, there will be a wakeup interrupt that causes usb to active mode. In order to fix this problem well, we need to do below things: - Need to discharge both dp and dm - It needs to discharge data line when we switch to device mode and usb cable is disconnected from the host, but not to disable discharge after line state is SE0, the reason is that if we do not pulldown the data line, the line state will be floating again, and possible cause the wakeup interrupt. - It needs to disable discharge data line when the usb cable connects at device mode and usb device is connected at host mode, otherwise it will affect signal quality. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-22ENGR00174734-1 usb: need to discharge both dp and dmPeter Chen
Change to discharge both dp and dm Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-22ENGR00174916 MX6x, console output hang 20 seconds when system bootupSandor Yu
It is cause by fb driver to init HDMI PHY when HDMI driver not register. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-02-22ENGR00174911 MX6x Setting HDMI default mode according bootload cmdlineSandor Yu
Origin HDMI default video mode is setting to VGA. But the HDMI will change to the vide mode setting in bootloader command line when the first time HDMI cable plugin. It will cause GUI sometime can't not get correct FB video mode when system bootup without HDMI cable plugout. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-02-21ENGR00174925 HDMI Kernel panic whatever plug in or plug outAlan Tull
Panic is due to runtime being a NULL pointer. Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-17ENGR00174809 hdmi audio oops in hdmi_dma_mmap_copyAlan Tull
Runtime dma_area may be invalid after trigger stop command. This will cause an oops in hdmi_dma_mmap_copy. To fix this, disable mmap copying with trigger stop command and also check the runtime->dma_area before doing hdmi_dma_mmap_copy. Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-17ENGR00173964 make hdmi audio init dependent on hdmi video initAlan Tull
Don't show hdmi as an audio playback device if hdmi isn't configured on the command line. Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-17ENGR00174652 i.mx6: explicitly set the LPM mode to run mode during early bootupJason Liu
the reset value of LPM[1:0] in CCM_CLPCR register is b'01, which means system will enter into wait mode on next assertion of dsm_request signal. In order to avoid the system unexpectly enter the wait mode during bootup we need set the LPM mode to run mode explicity during early boot up phase, Anytime, we want system to enter the wait mode, the sw procedure is: mxc_cpu_lp_set(LP_MODE) -> set CCM_CLPCR register -> system enter wait mode This patch also fix linux kernel reboot stress test on i.mx6dl, without this patch linux kernel reboot test will fail random with error like this: [ 12.091220] Bad mode in interrupt handler detected [ 12.096056] Bad mode in interrupt handler detected [ 12.100851] Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-17ENGR00174630 [MX6]Disable GPT serial clockAnson Huang
Currently we use 24MHz clock as GPT's clock source, serial clock can be disabled, it sourced from high freq clock, gating it can save ~8mA @VDDSOC. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-16ENGR00174540: i.mx6: anatop_regulator: LDO voltage print not correctlyJason Liu
The LDO voltage constraint not printed correctly: print_constraints: vddpu: 725 <--> 1300 mV at 700 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 700 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2000 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 700 mV fast normal print_constraints: vdd3p0: 2800 <--> 3150 mV at 2625 mV fast normal There due to one typo: << in the code, thus will make the LDO constraint print not correctly, the patch will make the print correctly as the followings: print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 5c2d296401e2ded0cd36f9e651871c6454049de1)
2012-02-16ENGR00174532 [MX6Q]Change 2D clock to 480MLarry Li
Change GPU2D core clock to 480M and use PLL3 as parent Signed-off-by: Larry Li <b20787@freescale.com>
2012-02-15ENGR00174569: MX6 - Disable WAIT mode by defaultRanjani Vaidyanathan
None of the workarounds implemented in SW provide a stable solution for the WAIT mode issue. For 4.1 release, WAIT mode is disabled by default. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-15ENGR00172274-02 - [MX6]: rework IEEE-1588 in MX6Q Sabre-lite/sd board.Fugang Duan
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: TO1.1 IEEE 1588 is convergent in Sabrelite board. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-02-14ENGR00174381 imx6q-sabreauto: spdif remove tx clock settingsAdrian Alonso
* Sabreauto platform only supports spdif in (Rx) Remove unused Tx clock settings Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-14ENGR00174437 ESAI: Add cs42888 build support in Makefile.Lionel Xu
Add cs42888 build support. Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
2012-02-14ENGR00174399 ASRC: fix mmap fail bugChen Liangjun
If output sample rate is less than input sample rate, it is possible that the address of output dma buffer 0 can not be divided by page size. Thus the mmap of output dma in the user space would fail and test would fail. let all output dma buffers allocate dma buffer together and we can assure that the address of output dma buffer 0 can be divided by page size. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-02-14ENGR00174323 vpu: Fix system hang issue of multi-instances processingSammy He
VPU registers have been mapped with ioremap() at probe which L_PTE_XN is 1, and the same physical address must be mapped multiple times with same type when doing mmap() to user space, so also need to set it to 1. Otherwise, there may be unexpected result in video codec. Here, Use new defined pgprot_noncachedxn for vm_page_prot in mmap(). Signed-off-by: Sammy He <r62914@freescale.com>
2012-02-14ENGR00174243 MIPI_DSI: mipi dsi panel enable should be after IPU initWayne Zou
MIPI_DSI: mipi dsi panel enable should be after IPU init, due to ENGR00173962 change in the mxc_ipuv3_fb.c Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-02-13ENGR00174315 MX6Q max7310 set the default value of PCIE PWR ctrl2 to lowRichard Zhu
System would be halt, when the default value CTRL_2 is set to high, change the default value to low. root cause: System 3V3 would be dragged down to 1.5V for about 4ms. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-13ENGR00174316 MX6Q ARM2: Fix ov5640_mipi IOMUX incorrect configureEven Xu
One type error on ov5640_mipi IOMUX configure, fix it. Signed-off-by: Even Xu <b21019@freescale.com>
2012-02-13ENGR00174311: [MX6Q]USDHC: SD3.0 card failed to workRyan QIAN
- add auto_tune back on pretuning to improve compatibility. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-02-13ENGR00174310 [MX6Q]USDHC: DDR50 mode for SD3.0 is not supported yetRyan QIAN
- change UHS-I mode selection to try SDR50 first, then DDR50. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-02-13ENGR00174307 [mx6 mmc]fix build warningTony Lin
mmc/core/bus.c:189: warning: initialization from incompatible pointer type Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-13ENGR00174302 [MX6]Clean build warningAnson Huang
arch/arm/mach-mx6/clock.c:1749: warning: unused variable 'reg'; Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-13ENGR00174295-02:[MX6]USDHC: ddr mode is masked on slots with no 1.8v support.Ryan QIAN
- check ocr_avail_sd & MMC_VDD_165_195 before set S18R bit to check whether the host is support 1.8v support. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-02-13ENGR00174295-01 Revert "ENGR173939 Skip sending S18R on slots with no 1.8V"Ryan QIAN
- this patch will mask ddr mode support on the slots support ddr, but no 1.8v support This reverts commit 05b7fdd4d6103500f1e531b3e5bd91d97f40ee34. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-02-13ENGR00174242 usb: device: Improve discharge dp operationPeter Chen
The discharge dp function needs to be added at below situation: - USB cable is disconnected from the PC - When the usb mode switchs to device mode Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-10ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1Tony Lin
remove the workaround For TO1.0: bit16 of GPR11 must be set to enable perfmon For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon. set 1/0 to enable/disable perfmon add workaround for mx6dl Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-10ENGR00174224 [MX6Q]: Add new AR6003 driver to 3.0.15 into default configRyan QIAN
- Add cfg80211, Atheros Wifi driver into default kernel config. Signed-off-by: Ryan QIAN <b32804@freescale.com>
2012-02-10ENGR00174033-2 MX6 PCIE: add pcie RC driverRichard Zhu
Add PCIE RC driver on MX6 platforms. Based on iwl4965agn pcie wifi device, verified the following features. * Link up is stable * map the CFG, IO and MEM spaces, and CFG/MEM spaces can accessed Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-10ENGR00174033-1 MX6 PCIE: add pcie RC driverRichard Zhu
Add PCIE RC driver on MX6 platforms. Based on iwl4965agn pcie wifi device, verified the following features. * Link up is stable * map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-10ENGR00174128-3 Revert "Remove the discharge for VBUS and DP -3"Peter Chen
This reverts commit cc9616316bf044382ec422da5a6d4ed007235a3d. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-10ENGR00174128-2 Revert "Remove the discharge for VBUS and DP-2"Peter Chen
This reverts commit 4f025d73de4a55077691096eacf60f90c3b9e7af. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-10ENGR00174128-1 Revert "Remove the discharge for VBUS and DP-1"Peter Chen
As dp/dm is floating with no usb cable and switch host mode to device mode situation, it do needs this discharge dp patch But, discharge vbus doesn't be needed at suspend_irq, so keep it removing. This reverts commit 0924b71278650fa3891a8f6ea70f91242ca6e5fd. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-09ENGR00174094 i.MX6DL: Change CPU voltages to 1VNancy Chen
Change CPU voltages (0.95V and 0.85V) to 1V CPU voltage should be above 1.0V for all CPU frequency since L1 Cache power is connected to VDDARM internally. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-02-09ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400MJason Liu
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need set DDR/periph_clk parent to pll2_mfd_400M during clock init, which will setup the clock usecount of pll2_mfd_400M correctly, otherwise, when all the child device with clock source from pll2_mfd_400M turn off, the pll2_mfd_400M will turns off automaticly, which will cause system hang due to DDR clock is off when code is runing on it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-09ENGR00174124: Revert "[USB Host]change the default wakeup value of RH"Peter Chen
This patch creates two bugs at current i.mx usb framework. - The high speed device can't be recognized at the first time. - The usb device can't be recognized after system resume with usb vbus. The reason why it creates bugs that it changes (auto)suspend/resume process for usb core. This reverts commit e5c4318450e1fe7c61950214e779658c6cea0da7. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-09ENGR00174103 [usb hsic] add usb hsic support for mx6dlTony LIU
- change the pad setting Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-09ENGR00174037-3 Add HSIC suspend/resume featureTony LIU
head file Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-09ENGR00174037-2 Add HSIC suspend/resume featureTony LIU
device part - implement reset_device interface for HSIC host Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-09ENGR00174037-1 Add HSIC suspend/resume featureTony LIU
MSL part - For HSIC, not connect nor disconnect, then WKCN, WKDC must not be set during suspend - For HSIC, must set bit 21 in host control registry after device connected to host controller - USB PHY 480M clock output must turn on to avoid about 10ms delay before sending out resume signal - HW_ANA_MISC clkgate delay must be set to 2 or 3 to avoid 24M OSCI not stable issue Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-08ENGR00172342-2 EDID parse audio data blocksAlan Tull
Add functionality to parse Audio Data Blocks from EDID data to find out what modes of LPCM are suppored by the HDMI sink device. The parsed settings are saved in the hdmi mfd. The HDMI audio driver will check the settings when the audio stream is opened and will then apply appropriate constraints. If we are unable to read from the EDID, then we default to supporting Basic Audio as defined by the HDMI specification (stereo, 16 bit, 32KHz, 44.1KHz, 48KHz PCM). Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-08ENGR00172342-1 EDID parse audio data blocksAlan Tull
Add functionality to parse Audio Data Blocks from EDID data to find out what modes of LPCM are suppored by the HDMI sink device. The parsed settings are saved in the hdmi mfd. The HDMI audio driver will check the settings when the audio stream is opened and will then apply appropriate constraints. If we are unable to read from the EDID, then we default to supporting Basic Audio as defined by the HDMI specification (stereo, 16 bit, 32KHz, 44.1KHz, 48KHz PCM). Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-08ENGR00171353 MIPI_DSI: mipi display blank and unblank fail fixedWayne Zou
mipi display blank and unblank fail on HW board: MX6Q_ARM2 1G SN 0112 The host processor sends PCLK, HS and VS information to display modules two frames before sleep-out command is sent. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-02-08ENGR00174054-2: imx6_defconfig: enable CONFIG_COMPACTIONJason Liu
Enable CONFIG_COMPACTION on imx6_defconfig to reduce the external memory fragementation Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-08ENGR00174054-1: i.mx6_defconfig: sync imx6_defconfig with v3.0.15Jason Liu
After upgrade kernel to 3.0.15, the defconfig also need be updated to sync with the kernel version change Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-08ENGR00173962 Added HDMI enable functionSandor Yu
Whenever IPU clock change or gating, the HDMI PHY should reset or config again, otherwise the HDMI PHY will not work. It is the root cause for Ubuntu can't show GUI to HDMI device when bootup and GPU application tutorial4_es20 no output to HDMI device. Added enable function in mxcfb_set_par() to fix aboved two issue. Added HDMI initialization check, only one HDMI instanse supported. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-02-08ENGR00174039 camera: modify camera driversYuxi Sun
Modify ov3640 ov5640 ov5642 driver according to sensor data structure change for dual camera switch Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-02-08ENGR00173864 MX6Q ipu capture: add multi camera switchYuxi Sun
Add IOCTRL command V4L2_CID_MXC_SWITCH_CAM for multi camera switch Signed-off-by: Yuxi Sun <b36102@freescale.com>
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