summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/tegra_cl_dvfs.c
AgeCommit message (Expand)Author
2017-11-29Merge tag 'tegra-l4t-r21.6' into toradex_tk1_l4t_r21.6Marcel Ziswiler
2016-11-30dvfs: tegra: Validate CLDVFS register addressBibek Basu
2016-06-29tegra: fix dvfs gcc 5.2 build errorMarcel Ziswiler
2014-06-26ARM: tegra: dvfs: Add SiMon grading to DFLL tuningAlex Frid
2014-06-09ARM: tegra: dvfs: Increase DFLL force guard-bandAlex Frid
2014-05-16ARM: tegra: dvfs: Defer calibration on force valueAlex Frid
2014-04-10ARM: tegra: dvfs: Use hrtimer for DFLL tuningAlex Frid
2014-04-09ARM: tegra: dvfs: Calibrate DFLL tuning thresholdAlex Frid
2014-04-09ARM: tegra: dvfs: Tune DFLL low at coldAlex Frid
2014-04-08ARM: tegra: dvfs: Update DFLL calibrationAlex Frid
2014-04-03ARM: tegra: dvfs: Compare set and required DFLL VminAlex Frid
2014-03-31ARM: tegra: dvfs: Swap CL-DVFS barrier and read fenceAlex Frid
2014-03-28ARM: tegra: dvfs: Fix compiler cast warningAlex Frid
2014-03-28ARM: tegra: dvfs: Add delay after DFLL enableAlex Frid
2014-03-20ARM: tegra: dvfs: Add DFLL output clamping interfaceAlex Frid
2014-03-19ARM: tegra: dvfs: Re-factor DFLL output force controlAlex Frid
2014-03-10ARM: tegra: dvfs: Check DFLL unlock voltage outputAlex Frid
2014-03-04Revert "ARM: T132: dvfs: Update dfll request ratio for 1st post silicon table"Krishna Sitaraman
2014-03-03ARM: tegra: dvfs: Update DFLL Fmax@Vmin calibrationAlex Frid
2014-02-24ARM: tegra: dvfs: Add 1st CL-DVFS out disable fenceAlex Frid
2014-02-21ARM: tegra: dvfs: Add CL-DVFS driver compatibilityAlex Frid
2014-02-20ARM: tegra: dvfs: Use safe DFLL caps below minimaxAlex Frid
2014-02-18ARM: tegra: dvfs: Add access to DFLL thermal floorsAlex Frid
2014-02-09ARM: T132: dvfs: Update dfll request ratio for 1st post silicon tableKrishna Sitaraman
2014-02-07ARM: tegra: dvfs: Allow no-tracking DFLL limit readAlex Frid
2014-02-07ARM: tegra: dvfs: Apply guard-band to tuning thresholdAlex Frid
2014-02-03ARM: tegra: Move PWM PMIC binding into DFLL sub-nodeAlex Frid
2014-01-30ARM: tegra: dvfs: Add PWM DFLL device tree supportAlex Frid
2014-01-30ARM: tegra: dvfs: Track CL-DVFS limits changeAlex Frid
2014-01-30ARM: tegra: clock: Update DFLL private data accessAlex Frid
2014-01-29ARM: tegra12: Move DFLL bypass device registrationAlex Frid
2014-01-23ARM: tegra: dvfs: Parse DFLL device tree dataAlex Frid
2014-01-17ARM: tegra: dvfs: Re-factor DFLL output limits controlAlex Frid
2014-01-17ARM: tegra: dvfs: Set DFLL clock data in common codeAlex Frid
2014-01-17ARM: tegra: dvfs: Build DFLL voltage selection mapAlex Frid
2014-01-07ARM: tegra: dvfs: Fix DFLL I2C mode calibrationAlex Frid
2013-12-13ARM: tegra: dvfs: Exempt top floor from SiMon offsetAlex Frid
2013-12-13ARM: tegra: dvfs: Handle SiMon CPU notificationAlex Frid
2013-12-11ARM: tegra: dvfs: Fix DFLL voltage mappingAlex Frid
2013-12-09ARM: tegra: dvfs: Update DFLL profile debugfs nodeAlex Frid
2013-12-04ARM: tegra: dvfs: Support non-sync DFLL monitorAlex Frid
2013-12-04ARM: tegra: dvfs: Work-around DFLL monitor fluctuationsAlex Frid
2013-11-15ARM: tegra: power: Fix DFLL bypass ops return typeAlex Frid
2013-11-15ARM: tegra: dvfs: Update DFLL debugfs profile nodesAlex Frid
2013-11-07ARM: tegra: dvfs: Split CL-DVFS registers accessorsAlex Frid
2013-11-04ARM: tegra: dvfs: Allow GPIO # 0 for DFLL PWM controlAlex Frid
2013-11-04ARM: tegra: dvfs: Fix DFLL undershoot guard-bandAlex Frid
2013-10-30ARM: tegra: dvfs: Show DFLL thermal profiles in debugfsAlex Frid
2013-10-16ARM: tegra: dvfs: Don't enbale DFLL bypass on LP clusterAlex Frid
2013-10-14ARM: tegra: dvfs: Explicitly enumerate CL-DVFS PWM busesAlex Frid
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-01 07:48:50 +0000