| Age | Commit message (Expand) | Author |
|---|
| 2015-05-24 | x86, cpu, amd: Add workaround for family 16h, erratum 793 | Borislav Petkov |
| 2014-05-19 | powernow-k6: reorder frequencies | Mikulas Patocka |
| 2014-05-19 | powernow-k6: correctly initialize default parameters | Mikulas Patocka |
| 2014-05-19 | powernow-k6: disable cache when changing frequency | Mikulas Patocka |
| 2014-05-19 | powernow-k6: set transition latency value so ondemand governor can be used | Krzysztof Helt |
| 2013-06-10 | MCE: Fix vm86 handling for 32bit mce handler | Andi Kleen |
| 2012-10-07 | x86, random: Verify RDRAND functionality and allow it to be disabled | H. Peter Anvin |
| 2011-06-23 | x86, amd: Use _safe() msr access for GartTlbWlk disable code | Roedel, Joerg |
| 2011-06-23 | x86, amd: Do not enable ARAT feature on AMD processors below family 0x12 | Boris Ostrovsky |
| 2011-05-23 | x86, mce, AMD: Fix leaving freed data in a list | Julia Lawall |
| 2011-05-23 | x86, apic: Fix spurious error interrupts triggering on all non-boot APs | Youquan Song |
| 2011-05-23 | x86, AMD: Fix ARAT feature setting again | Borislav Petkov |
| 2011-05-23 | Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors" | Borislav Petkov |
| 2011-05-09 | x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors | Boris Ostrovsky |
| 2011-04-22 | x86, cpu: Fix regression in AMD errata checking code | Hans Rosenfeld |
| 2011-04-22 | x86, amd: Disable GartTlbWlkErr when BIOS forgets it | Joerg Roedel |
| 2011-04-22 | x86, AMD: Set ARAT feature on AMD processors | Boris Ostrovsky |
| 2011-04-22 | x86, cpu: Clean up AMD erratum 400 workaround | Hans Rosenfeld |
| 2011-04-22 | x86, cpu: AMD errata checking framework | Hans Rosenfeld |
| 2011-04-14 | x86, mtrr, pat: Fix one cpu getting out of sync during resume | Suresh Siddha |
| 2011-02-17 | x86, mtrr: Avoid MTRR reprogramming on BP during boot on UP platforms | Suresh Siddha |
| 2011-01-07 | x86, amd: Fix panic on AMD CPU family 0x15 | Andreas Herrmann |
| 2010-12-09 | acpi-cpufreq: fix a memleak when unloading driver | Zhang Rui |
| 2010-11-22 | x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs | Andreas Herrmann |
| 2010-10-28 | x86: detect scattered cpuid features earlier | Jacob Pan |
| 2010-10-28 | x86, AMD, MCE thresholding: Fix the MCi_MISCj iteration order | Borislav Petkov |
| 2010-10-28 | x86, cpu: After uncapping CPUID, re-run CPU feature detection | H. Peter Anvin |
| 2010-08-13 | x86, vmware: Preset lpj values when on VMware. | Alok Kataria |
| 2010-07-05 | perf_events: Fix resource leak in x86 __hw_perf_event_init() | Stephane Eranian |
| 2010-05-26 | x86, cacheinfo: Turn off L3 cache index disable feature in virtualized enviro... | Frank Arnold |
| 2010-05-12 | x86, AMD: Fix stale cpuid4_info shared_map data in shared_cpu_map cpumasks | Prarit Bhargava |
| 2010-05-12 | x86: Disable large pages on CPUs with Atom erratum AAE44 | H. Peter Anvin |
| 2010-05-12 | powernow-k8: Fix frequency reporting | Mark Langsdorf |
| 2010-04-26 | perf_events, x86: Implement Intel Westmere/Nehalem-EX support | Peter Zijlstra |
| 2010-04-26 | x86, cacheinfo: Enable L3 CID only on AMD | Borislav Petkov |
| 2010-04-26 | x86, cacheinfo: Remove NUMA dependency, fix for AMD Fam10h rev D1 | Borislav Petkov |
| 2010-04-26 | x86, cacheinfo: Calculate L3 indices | Borislav Petkov |
| 2010-04-26 | x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches | Borislav Petkov |
| 2010-04-26 | x86, cacheinfo: Fix disabling of L3 cache indices | Borislav Petkov |
| 2010-04-26 | x86, amd: Get multi-node CPU info from NodeId MSR instead of PCI config space | Andreas Herrmann |
| 2010-04-01 | x86: Fix sched_clock_cpu for systems with unsynchronized TSC | Dimitri Sivanich |
| 2010-02-23 | CPUFREQ: Fix use after free of struct powernow_k8_data | Thomas Renninger |
| 2010-02-09 | x86: Remove "x86 CPU features in debugfs" (CONFIG_X86_CPU_DEBUG) | H. Peter Anvin |
| 2010-01-28 | x86: Reenable TSC sync check at boot, even with NONSTOP_TSC | Pallipadi, Venkatesh |
| 2010-01-22 | x86, mce: Thermal monitoring depends on APIC being enabled | Cyrill Gorcunov |
| 2009-12-18 | x86: Under BIOS control, restore AP's APIC_LVTTHMR to the BSP value | Yong Wang |
| 2009-12-18 | x86: Fix typo in Intel CPU cache size descriptor | Dave Jones |
| 2009-12-18 | x86: Add new Intel CPU cache size descriptors | Dave Jones |
| 2009-12-18 | x86/mce: Set up timer unconditionally | Jan Beulich |
| 2009-12-18 | x86, mce: don't restart timer if disabled | Hidetoshi Seto |
