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path: root/drivers/clk/bcm/clk-bcm2835.c
AgeCommit message (Expand)Author
2018-04-24clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon
2018-03-28clk: bcm2835: Protect sections updating shared registersBoris Brezillon
2018-03-28clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon
2017-03-22clk: bcm2835: Fix ->fixed_divider of pllh_auxBoris Brezillon
2017-01-09clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clkBoris Brezillon
2016-10-17clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.Eric Anholt
2016-09-14clk: bcm2835: Migrate to clk_hw based registration and OF APIsStephen Boyd
2016-09-07clk: bcm2835: Skip PLLC clocks when deciding on a new clock parentEric Anholt
2016-09-07clk: bcm2835: Mark the CM SDRAM clock's parent as criticalEric Anholt
2016-09-07clk: bcm2835: Mark GPIO clocks enabled at boot as criticalEric Anholt
2016-09-07clk: bcm2835: Mark the VPU clock as criticalEric Anholt
2016-04-19clk: bcm2835: Fix PLL poweronEric Anholt
2016-04-19clk: bcm2835: Fix compiler warnings on 64-bit buildsEric Anholt
2016-03-17clk: bcm2835: add missing osc and per clocksMartin Sperl
2016-03-17clk: bcm2835: add missing PLL clock dividersMartin Sperl
2016-03-17clk: bcm2835: enable management of PCM clockMartin Sperl
2016-03-17clk: bcm2835: reorganize bcm2835_clock_array assignmentMartin Sperl
2016-03-17clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driverMartin Sperl
2016-03-17clk: bcm2835: expose raw clock-registers via debugfsMartin Sperl
2016-03-17clk: bcm2835: clean up coding style issuesMartin Sperl
2016-03-17clk: bcm2835: correctly enable fractional clock supportMartin Sperl
2016-03-17clk: bcm2835: divider value has to be 1 or moreMartin Sperl
2016-03-17clk: bcm2835: add locking to pll*_on/off methodsMartin Sperl
2016-03-17clk: bcm2835: pll_off should only update CM_PLL_ANARSTMartin Sperl
2016-03-02clk: bcm: Remove CLK_IS_ROOTStephen Boyd
2016-02-25clk: bcm2835: added missing clock register definitionsMartin Sperl
2016-02-16clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()Eric Anholt
2016-02-16clk: bcm2835: Fix setting of PLL divider clock ratesEric Anholt
2015-12-24clk: bcm2835: Add PWM clock supportRemi Pommarel
2015-12-24clk: bcm2835: Support for clock parent selectionRemi Pommarel
2015-12-24clk: bcm2835: add a round up ability to the clock divisorRemi Pommarel
2015-10-12clk: bcm2835: Add support for programming the audio domain clocksEric Anholt
2015-10-01clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.Eric Anholt