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path: root/drivers/video/tegra/dc/dsi.c
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2016-09-29video: tegra: dsi: fix gcc-6 compilationMarcel Ziswiler
drivers/video/tegra/dc/dsi.c: In function 'tegra_dsi_read_fifo': drivers/video/tegra/dc/dsi.c:2515:3: error: this 'if' clause does not guard... [-Werror=misleading-indentation] if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) ^~ drivers/video/tegra/dc/dsi.c:2518:4: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the 'if' break; ^~~~~ Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2012-09-03video: tegra: dc: support for vblank syncRakesh Iyer
Add wait for vsync support for one-shot panels. The code supports extension of this feature to other panels. Bug 1033411. Change-Id: Ie4d6cb45e5de81083458169ccdfa33230235ed72 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/128927 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2012-07-30video: tegra: dsi: Fix host HS transmissionAnimesh Kishore
Fixing host transmission with HS enabled. Bug 999141 Change-Id: I9dcc5282971830865dacf16dbbbebf4096aeb00e Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/118315 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-25video: tegra: dc: synchronize dsi clock-gatingRakesh Iyer
The one shot thread will clock gate the modules periodically. This will ensure relevant paths in dc driver have an active dc clock and dsi host. Bug 1013172 Change-Id: Ibb505e35044f31405c06cb9fa0d6fdf78aafd4a6 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/117137 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-19video: tegra: dsi: Implement dcs video + hostAnimesh Kishore
Send host commands to panel during vertical blanking of a frame. Implementation is generic enough to handle both long and short packets. Bug 1009863 Change-Id: I9a80641df2d8b67eb3649d220c028543b246a5f3 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/114990 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-07-02video: tegra: dc: split dc.c into smaller filesJon Mayo
Moved mode setting code into mode.c Move window code info window.c Moved clock related code into clock.c Moved LUT and gamma related code into lut.c Moved csc(color space conversion) into csc.c Removed unnecessary static function prototypes from header. Moved many short inline functions to dc_priv.h Cleaned up copyright headings. Cleaned up formatting and indent in all files. Fixed build warnings. Bug 870907 Change-Id: I6ccc37150191765394f0b5629423eafd4e5e5792 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/111371 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-01video: tegra: dsi: 720p panel power fixRakesh Iyer
Send specified DC frames to 720p panel during power up/down sequencing. Bug 997484. Change-Id: I3927e98322ec93f68cabf635c71485b64750d7f9 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/109917 (cherry picked from commit e1d10bc056031fbc2f68101978d76317c44fc7af) Reviewed-on: http://git-master/r/111944 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-06-27video: tegra: dc: Deactivate DSI runtime when DC is idle.Kevin Huang
We support 3 different aggressiveness levels of disabling DSI runtime. The larger the aggressive level is, the higher DSI power we can save. Bug 936337 Change-Id: Idadcb49b364e29ddd0a05dde1c6d3dfda6cd493e Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/106361 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-26video: tegra: use public APIs exposed by host1x driverMayuresh Kulkarni
Bug 961009 Change-Id: Ifdcc7bc8a40d270e70a63329f46caff541bf01e2 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/109461 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-06-14video: tegra: dc: Move #includes from dc_priv.hTerje Bergstrom
Move #include directives for nvhost headers from dc_priv.h to the source files that need the #includes. This allows #including dc_priv.h without access to all nvhost headers. Also adds nvhost to the #include path of dc to allow making dev.h a stub in a later commit. Bug 982965 Change-Id: Icfe7084d295f57926195b178174f81047eb01187 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/108225 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-11video: tegra: dc: Clock-gate display modules dynamically.Kevin Huang
Bug 936337 Bug 899053 Change-Id: I2b3d8cfc8a00881338c1e17d03f2844d15ba7d3e Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/106313 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-04video: tegra: dsi: remove build warningsJon Mayo
Added void to function prototypes and initialized some variables. Change-Id: I69250f5e17560f900fffddec9697e496af6ad4d2 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/106073 Reviewed-by: Automatic_Commit_Validation_User
2012-05-23video: tegra: dsi: enable dsi panel BPreetham Chandru
Enable dsi panel B by setting the first bit in APB_MISC_GP_MIPI_PAD_CTRL_0 register. Bug 935764 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I9e958e0c9d9e934edf77688fd6a987b5e863392b Reviewed-on: http://git-master/r/96672 Reviewed-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Kiran Adduri <kadduri@nvidia.com> Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-15video: tegra: dsi: WAR to stop on going host writeAnimesh Kishore
WAR comprises of soft reset dsi controller followed by explicitly clearing host trigger. Bug 982919 Change-Id: Ia8c497dd496435e429cd5b5ee8aaf1b7d78dc797 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/102204 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-03video: tegra: dsi: Ref-count pllp_out3 clock in DSI.Kevin Huang
Bug 933653 Change-Id: If7ce4dc5129782a7e3487028d2dba01c9380ba90 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/98256 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-04-25video: tegra: dsi: Add DSI register dump in debugfs.Kevin Huang
Bug 951349 Change-Id: I79fb2e49fa38b83af78323b5f5cf6dbca8fd83c2 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/98512 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-24video: tegra: dc: add tracing informationJon Mayo
add trace_printk to log useful debug information. Bug 870685 Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/89204 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Malani <pmalani@nvidia.com>
2012-03-20video: tegra: dsi: Clear host trigger bit explicitly on fifo emptyAnimesh Kishore
dsi HW does not clear host trigger bit automatically on dsi interface disable if host fifo is empty. This leads to hang. Clearing the bit explicitly. Bug 930453 Change-Id: Id24359dc274f187f8ac634ad838ef4a6a29a6a5e Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/90043 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-03-15video: tegra: dsi: Add checks to dsi for HOST1X powerTerje Bergstrom
Add checks to ensure host1x is powered when DSI is used. Change-Id: I2e61abdd5c0741571fb18262fd2efa16ffee71d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/86361 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-15video: tegra: dc: Add rated refresh rate for one-shot mode.Kevin Huang
We add this variable for two purposes. First, it would remind developer to make sure actual refresh rate is larger than rated refresh rate. Second, gralloc would read rated refresh rate for one-shot mode since actual refresh rates of most devices are expected running at rated refresh rate. Bug 946370 Bug 934977 Change-Id: Ib4121337df1a388b40440b22687c39f373f08890 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/89871 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-15video: tegra: dsi: Add phy timing check for hblankAnimesh Kishore
Horizontal blank must be greater than phy timing for HS transmission. Bug 938043 Change-Id: I5afe68ec04341f7b83c2897c586d4618bd518222 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/89789 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-03-15video: tegra: dsi: Fix phy timing HW incrementAnimesh Kishore
Adding support to accomodate hw increment to phy timing reg values. Bug 938043 Change-Id: I8de14648c0994b03c37a2ee455a656ff11c3cc34 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/89741 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-03-06video: tegra: dsi: fix DSI_PAD_CONTROL reg wr value on resumeBoris Suvorov
In panel resume path DSI_PAD_CONTROL value gets calibrated, however later on values are overwritten with bit settings for ulpm mode. refactor value for reg write to only change ulpm related bits. Change-Id: I9f9713bdf376c06b0e1b9f43b3e6c9f719bbd855 Signed-off-by: Boris Suvorov <bsuvorov@nvidia.com> Reviewed-on: http://git-master/r/85873 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-05video: tegra: dsi: Fix syncpt hang during early suspend cycleAnimesh Kishore
Fixing dsi syncpt hang issue after multiple cycles of early suspend-late resume. Bug 943096 Change-Id: Iefc0530a6e514b7733819dd1df35cde8f5c3dd47 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/86946 Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
2012-02-23video: tegra: dsi: Fix dsi phy timingAnimesh Kishore
Corrected the formulas to calculate phy timing. Added mipi d-phy constraints. Bug 938043 Change-Id: Ie1f2dd45e7e39f83735fe28e21a62dc0415c7c00 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/85217 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-02-16video: tegra: dsi: Config dsi and csi shared padAnimesh Kishore
Configure voltage regulator. Bug 914749 Change-Id: I6cf1924a928839249d4e62029dd14fca84b05792 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/83361 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-16video: tegra: dsi: Soft reset if dsi host busyAnimesh Kishore
If dsi host is unexpectedly busy, soft resetting will restore controller state. Bug 930453 Change-Id: I1bbce55d0b27a2be80a66218978e73c616e9d894 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/83986 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-15video: tegra: dc: Schedule delayed work to clear emc bandwidth.Kevin Huang
Bug 932840 Change-Id: I12d8d2d2cd42d0dafea38463ad77b44f7e64d7c1 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/83645 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-13video: tegra: dc: Ignore suspend if DSI is disabledTerje Bergstrom
DSI enables during suspend time host1x, and then checks if DSI is really enabled. Now DSI first checks if it's enabled. If yes, it'll turn on host1x and disable it. Bug 887332 Change-Id: I206f908a62d0a56f0737c31634fa46613ca07d7e Reviewed-on: http://git-master/r/82755 Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2012-01-30video: tegra: dsi: Refine the DSI clock calculation.Kevin Huang
Reviewed-on: http://git-master/r/76406 Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77306 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24video: tegra: host: Access nvhost_master via drvdataTerje Bergstrom
Use standard drvdata interface for storing and accessing nvhost_master. Reviewed-on: http://git-master/r/72846 Change-Id: I191987c8f6d313a6ede9b59f723269cb6a197e8a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76815 Reviewed-by: Automatic_Commit_Validation_User
2012-01-16Revert "video: tegra: dc: fix DSI pclk calculation"Jon Mayo
This reverts commit 20f43dfc590d22ad1e80b7b948f108b17038b084. Conflicts: drivers/video/tegra/dc/dc.c This fix is no longer needed to boot. Change-Id: Ie8d877207b6a1d70c63834f234d7a7cc68a372bf Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/74884 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-on: http://git-master/r/75151 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-06video: tegra: dsi: Fix mipi continuous clk disableAnimesh Kishore
Fix for stopping mipi high speed continuous clk. Bug 903878 Change-Id: Id318fabd9c6aef116a60608c6f444846172f4803 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/72968 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-30video: tegra: dc: Fix dc stream random failure to stopAnimesh Kishore
Fix dc stream randomly failing to stop. Add stablization delay during dsi interface reset. Bug 913019 Change-Id: I1cf3013659de75d15cb1ff41b27c63abd953d614 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/71952 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-21video dsi: tegra: Fix support for hs clk in lp modeAnimesh Kishore
Enables high speed clock on mipi lanes in low power mode. Change-Id: I3b05d7f9bc5e8f63483220100f3361904e627c52 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/69951 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-15video: tegra: dc: Move DSI clock configuration to DC.Kevin Huang
We'd better place clock set-up in dc as HDMI. It makes code cleaner. Also eliminate a false warning. Bug 902786 Bug 850852 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/65024 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit e570e8dd45a66f11f0fc432f5919c5a036e34ba0) Change-Id: I90d73602048e2b3c706550128ba04665c307da22 Reviewed-on: http://git-master/r/68863 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2011-12-08tegra: treewide: Remove unused gpio-names.h includesDan Willemsen
Most places shouldn't be using these macros, they should get the gpio information from the board files. Either way, all of these instances were unused. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: Ifb76704dccb24e5e6eab4c06c79bc8e97802c6d3 Reviewed-on: http://git-master/r/68481 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-12-08video: dsi: tegra: Implement panel sanity checkAnimesh Kishore
-Send NOP cmd and BTA -Switch to host operation from any state and switch back on completion. -Optimize for code reusability Bug 880775 Bug 903882 Change-Id: I2f5132d6d72743606696040d6bb6878f5b29418f Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/66826 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-30video: tegra: dsi: Fix read in lp write configAnimesh Kishore
Use separate freq for read and write operation. Freq mentioned in board file. Change-Id: I9d641679d975e18713e147f73960ba584755a663 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/66134 Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Rebase-Id: Ra82e1506f68bd7c598b74b63beee822c9619e0ec
2011-11-30video: tegra: dsi: Add support for DCS short write (1 parameter)Ming Wong
Add MIPI DCS short write (1 parameter) support. The cmds sent with this new function will be sent every frame by hardware Bug 884157 Reviewed-on: http://git-master/r/58180 Reviewed-by: Jon Mayo <jmayo@nvidia.com> (cherry picked from commit df4679db62b164e33e82fe56a18787cfca431d82) Signed-off-by: Jon Mayo <jmayo@nvidia.com> [jmayo@nvidia.com: cleaned up formatting] Change-Id: Ia2b54c070c91bbb4ba59741c0c5c23dae8f71ce8 Reviewed-on: http://git-master/r/63413 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: R965eb64babd304bd66f2c057721a9dd1eedb17ca
2011-11-30video: tegra: dsi: use mask to control interruptsXin Xie
This patch is based on "video: tegra: dc: use mask to control interrupts", so we do not use DC_CMD_INT_ENABLE to disable IRQ. Bug 888207 Bug 870801 Reviewed-on: http://git-master/r/58176 (cherry picked from commit 6feaad5a74a934f604f5d25220afff478c43736d) Change-Id: I2d7f8575c7d88fa89eb18c88e09cef62228353e8 Signed-off-by: Jon Mayo <jmayo@nvidia.com> [jmayo@nvidia.com: fixed conflicts] Reviewed-on: http://git-master/r/63371 Rebase-Id: R31808eb1648f8634cc183f0d92c763999909d10d
2011-11-30video: tegra: dc: Use FRAME_END_INT to mark completion of frame end.Kevin Huang
V_BLANK_INT was used to mark frame end for other tasks. However, it occurs at frame start. Switch to FRAME_END_INT to mark the end of frame. Bug 875448 Reviewed-on: http://git-master/r/52694 (cherry picked from commit 078a2688c67c46cf840f191405cd4324cb9c4574) Signed-off-by: Jon Mayo <jmayo@nvidia.com> [jmayo@nvidia.com: wrapped commit message, fixed bug in S_TO_MS()] Change-Id: I507148772c2f3037befd30289e5b3a56fe417ee9 Reviewed-on: http://git-master/r/63369 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R5dbcf2d7ff3fd627194ae1a6163a300e6e48ff7c
2011-11-30video: tegra: dsi: Refactor code in tegra_dsi_hw_init()Kevin Huang
Reviewed-on: http://git-master/r/54824 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> (cherry picked from commit 4681815651f5949840815a03698d55ec8186796c) Change-Id: I5553b52806c63f8fb1fdc38f151a144ec103bcc5 Reviewed-on: http://git-master/r/61617 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rf733836f46f9afb42b5d680683d98e04c4a0e776
2011-11-30video: tegra: dsi: Fix value of PKT_WR_FIFO_SEL.Kevin Huang
Bug 834959 Reviewed-on: http://git-master/r/54861 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit 8f2ce3c04c16331332d4ba12f097787fd82af2db) Change-Id: I3e8c9039316459a563a432507e880c29f04260ba Reviewed-on: http://git-master/r/61612 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re5a1aab4caec5539d213697ed2cc90b2255a79be
2011-11-30video: tegra: dsi: Adjust two CSI registers in DSI module.Kevin Huang
Bug 829327 Reviewed-on: http://git-master/r/50871 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit 8d9aa14595348a2daa408710927471169447e73c) Change-Id: Ib3e335dab5329ef29842354dc9934f8213ae3d58 Reviewed-on: http://git-master/r/61603 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6ec4d12410e956f37db259fb337fd17d86622838
2011-11-30video: tegra: dsi: Adjust CSI register values to follow MIPI spec.Kevin Huang
Bug 829327 Reviewed-on: http://git-master/r/50352 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit 36eb87ff03c2bc6ee5b3821117b3afb225417034) Change-Id: I1533f55d0817c76c3cd75890b13927b81a2f0c4b Reviewed-on: http://git-master/r/61602 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R70593482503bd6de287d3cbf90e4b075c1cfb194
2011-11-30video: tegra: dsi: Code clean-upAnimesh Kishore
Fix indentation Change-Id: I40edd117a454d0307e38bec93729cbe3f3fb86c5 Reviewed-on: http://git-master/r/61868 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Raeb8098dcf39d9a54208cee6ed14e754ea969a4f
2011-11-30video: dsi: tegra: Use separate LP freq for readAnimesh Kishore
Recommended LP freq for read and write is sometimes different. Adding provision to use diff freq for read and write. Bug 863030 Reviewed-on: http://git-master/r/49197 (cherry picked from commit fd5448995b73bb3e896765a2695d01699f2e7c99) Change-Id: I78bda39223cb56bad5e917420b9748439f37c5cf Reviewed-on: http://git-master/r/54182 Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Tested-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: R02f17dbaee01fc98d49f728da0a1bed4e2a7c0e8
2011-11-30video: tegra: dsi: deep sleepAnimesh Kishore
Aggregate code for dsi deep sleep Bug 862427 Original-Change-Id: I5296e6659112642f9fe0fb84bec1d5938014c33a Reviewed-on: http://git-master/r/49506 Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Tested-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Ref7c30c407efe88481af5f2d23e5892bb0d05ef3
2011-11-30video: tegra: dsi: Reset DSI state during system booting.Kevin Huang
Bug 866389 Original-Change-Id: Ia382270e29fb8b0c111ffe41bcee20f8a072f3a2 Reviewed-on: http://git-master/r/48343 Reviewed-by: Kevin Huang <kevinh@nvidia.com> Tested-by: Kevin Huang <kevinh@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R5d78a5727bafe0f6f66eece2791a18f66bdd9df8
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-26 05:51:11 +0000