summaryrefslogtreecommitdiff
path: root/drivers/net/sfc/falcon_io.h
blob: c16da3149fa9ddc6d4fde23482a3f91c08147be3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2008 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef EFX_FALCON_IO_H
#define EFX_FALCON_IO_H

#include <linux/io.h>
#include <linux/spinlock.h>

/**************************************************************************
 *
 * Falcon hardware access
 *
 **************************************************************************
 *
 * Notes on locking strategy:
 *
 * Most Falcon registers require 16-byte (or 8-byte, for SRAM
 * registers) atomic writes which necessitates locking.
 * Under normal operation few writes to the Falcon BAR are made and these
 * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
 * cased to allow 4-byte (hence lockless) accesses.
 *
 * It *is* safe to write to these 4-byte registers in the middle of an
 * access to an 8-byte or 16-byte register.  We therefore use a
 * spinlock to protect accesses to the larger registers, but no locks
 * for the 4-byte registers.
 *
 * A write barrier is needed to ensure that DW3 is written after DW0/1/2
 * due to the way the 16byte registers are "collected" in the Falcon BIU
 *
 * We also lock when carrying out reads, to ensure consistency of the
 * data (made possible since the BIU reads all 128 bits into a cache).
 * Reads are very rare, so this isn't a significant performance
 * impact.  (Most data transferred from NIC to host is DMAed directly
 * into host memory).
 *
 * I/O BAR access uses locks for both reads and writes (but is only provided
 * for testing purposes).
 */

/* Special buffer descriptors (Falcon SRAM) */
#define BUF_TBL_KER_A1 0x18000
#define BUF_TBL_KER_B0 0x800000


#if BITS_PER_LONG == 64
#define FALCON_USE_QWORD_IO 1
#endif

#ifdef FALCON_USE_QWORD_IO
static inline void _falcon_writeq(struct efx_nic *efx, __le64 value,
				  unsigned int reg)
{
	__raw_writeq((__force u64)value, efx->membase + reg);
}
static inline __le64 _falcon_readq(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le64)__raw_readq(efx->membase + reg);
}
#endif

static inline void _falcon_writel(struct efx_nic *efx, __le32 value,
				  unsigned int reg)
{
	__raw_writel((__force u32)value, efx->membase + reg);
}
static inline __le32 _falcon_readl(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le32)__raw_readl(efx->membase + reg);
}

/* Writes to a normal 16-byte Falcon register, locking as appropriate. */
static inline void falcon_write(struct efx_nic *efx, efx_oword_t *value,
				unsigned int reg)
{
	unsigned long flags;

	EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
		    EFX_OWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef FALCON_USE_QWORD_IO
	_falcon_writeq(efx, value->u64[0], reg + 0);
	wmb();
	_falcon_writeq(efx, value->u64[1], reg + 8);
#else
	_falcon_writel(efx, value->u32[0], reg + 0);
	_falcon_writel(efx, value->u32[1], reg + 4);
	_falcon_writel(efx, value->u32[2], reg + 8);
	wmb();
	_falcon_writel(efx, value->u32[3], reg + 12);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Writes to an 8-byte Falcon SRAM register, locking as appropriate. */
static inline void falcon_write_sram(struct efx_nic *efx, efx_qword_t *value,
				     unsigned int index)
{
	unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
	unsigned long flags;

	EFX_REGDUMP(efx, "writing SRAM register %x with " EFX_QWORD_FMT "\n",
		    reg, EFX_QWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef FALCON_USE_QWORD_IO
	_falcon_writeq(efx, value->u64[0], reg + 0);
#else
	_falcon_writel(efx, value->u32[0], reg + 0);
	wmb();
	_falcon_writel(efx, value->u32[1], reg + 4);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write dword to Falcon register that allows partial writes
 *
 * Some Falcon registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
 * TX_DESC_UPD_REG) can be written to as a single dword.  This allows
 * for lockless writes.
 */
static inline void falcon_writel(struct efx_nic *efx, efx_dword_t *value,
				 unsigned int reg)
{
	EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
		    reg, EFX_DWORD_VAL(*value));

	/* No lock required */
	_falcon_writel(efx, value->u32[0], reg);
}

/* Read from a Falcon register
 *
 * This reads an entire 16-byte Falcon register in one go, locking as
 * appropriate.  It is essential to read the first dword first, as this
 * prompts Falcon to load the current value into the shadow register.
 */
static inline void falcon_read(struct efx_nic *efx, efx_oword_t *value,
			       unsigned int reg)
{
	unsigned long flags;

	spin_lock_irqsave(&efx->biu_lock, flags);
	value->u32[0] = _falcon_readl(efx, reg + 0);
	rmb();
	value->u32[1] = _falcon_readl(efx, reg + 4);
	value->u32[2] = _falcon_readl(efx, reg + 8);
	value->u32[3] = _falcon_readl(efx, reg + 12);
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
		    EFX_OWORD_VAL(*value));
}

/* This reads an 8-byte Falcon SRAM entry in one go. */
static inline void falcon_read_sram(struct efx_nic *efx, efx_qword_t *value,
				    unsigned int index)
{
	unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
	unsigned long flags;

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef FALCON_USE_QWORD_IO
	value->u64[0] = _falcon_readq(efx, reg + 0);
#else
	value->u32[0] = _falcon_readl(efx, reg + 0);
	rmb();
	value->u32[1] = _falcon_readl(efx, reg + 4);
#endif
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	EFX_REGDUMP(efx, "read from SRAM register %x, got "EFX_QWORD_FMT"\n",
		    reg, EFX_QWORD_VAL(*value));
}

/* Read dword from Falcon register that allows partial writes (sic) */
static inline void falcon_readl(struct efx_nic *efx, efx_dword_t *value,
				unsigned int reg)
{
	value->u32[0] = _falcon_readl(efx, reg);
	EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
		    reg, EFX_DWORD_VAL(*value));
}

/* Write to a register forming part of a table */
static inline void falcon_write_table(struct efx_nic *efx, efx_oword_t *value,
				      unsigned int reg, unsigned int index)
{
	falcon_write(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Read to a register forming part of a table */
static inline void falcon_read_table(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int index)
{
	falcon_read(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Write to a dword register forming part of a table */
static inline void falcon_writel_table(struct efx_nic *efx, efx_dword_t *value,
				       unsigned int reg, unsigned int index)
{
	falcon_writel(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Page-mapped register block size */
#define FALCON_PAGE_BLOCK_SIZE 0x2000

/* Calculate offset to page-mapped register block */
#define FALCON_PAGED_REG(page, reg) \
	((page) * FALCON_PAGE_BLOCK_SIZE + (reg))

/* As for falcon_write(), but for a page-mapped register. */
static inline void falcon_write_page(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int page)
{
	falcon_write(efx, value, FALCON_PAGED_REG(page, reg));
}

/* As for falcon_writel(), but for a page-mapped register. */
static inline void falcon_writel_page(struct efx_nic *efx, efx_dword_t *value,
				      unsigned int reg, unsigned int page)
{
	falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
}

/* Write dword to Falcon page-mapped register with an extra lock.
 *
 * As for falcon_writel_page(), but for a register that suffers from
 * SFC bug 3181. Take out a lock so the BIU collector cannot be
 * confused. */
static inline void falcon_writel_page_locked(struct efx_nic *efx,
					     efx_dword_t *value,
					     unsigned int reg,
					     unsigned int page)
{
	unsigned long flags;

	spin_lock_irqsave(&efx->biu_lock, flags);
	falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

#endif /* EFX_FALCON_IO_H */