ENGR00122852-5 MX37: pass mem and irq via resources

Pass memory and irq information via resources in MX37 platform

Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>

1 files changed, 67 insertions, 12 deletions

diff --git a/arch/arm/mach-mx37/serial.c b/arch/arm/mach-mx37/serial.c
index 6a3c4a7e5c6c..d1f9824a7585 100644
--- a/arch/arm/mach-mx37/serial.c
+++ b/arch/arm/mach-mx37/serial.c
@@ -37,16 +37,12 @@
 static uart_mxc_port mxc_ports[] = {
 	[0] = {
 	       .port = {
-			.membase = (void *)IO_ADDRESS(UART1_BASE_ADDR),
-			.mapbase = UART1_BASE_ADDR,
 			.iotype = SERIAL_IO_MEM,
-			.irq = UART1_INT1,
 			.fifosize = 32,
 			.flags = ASYNC_BOOT_AUTOCONF,
 			.line = 0,
 			},
 	       .ints_muxed = UART1_MUX_INTS,
-	       .irqs = {UART1_INT2, UART1_INT3},
 	       .mode = UART1_MODE,
 	       .ir_mode = UART1_IR,
 	       .enabled = UART1_ENABLED,
@@ -62,16 +58,12 @@ static uart_mxc_port mxc_ports[] = {
 	       },
 	[1] = {
 	       .port = {
-			.membase = (void *)IO_ADDRESS(UART2_BASE_ADDR),
-			.mapbase = UART2_BASE_ADDR,
 			.iotype = SERIAL_IO_MEM,
-			.irq = UART2_INT1,
 			.fifosize = 32,
 			.flags = ASYNC_BOOT_AUTOCONF,
 			.line = 1,
 			},
 	       .ints_muxed = UART2_MUX_INTS,
-	       .irqs = {UART2_INT2, UART2_INT3},
 	       .mode = UART2_MODE,
 	       .ir_mode = UART2_IR,
 	       .enabled = UART2_ENABLED,
@@ -87,16 +79,12 @@ static uart_mxc_port mxc_ports[] = {
 	       },
 	[2] = {
 	       .port = {
-			.membase = (void *)IO_ADDRESS(UART3_BASE_ADDR),
-			.mapbase = UART3_BASE_ADDR,
 			.iotype = SERIAL_IO_MEM,
-			.irq = UART3_INT1,
 			.fifosize = 32,
 			.flags = ASYNC_BOOT_AUTOCONF,
 			.line = 2,
 			},
 	       .ints_muxed = UART3_MUX_INTS,
-	       .irqs = {UART3_INT2, UART3_INT3},
 	       .mode = UART3_MODE,
 	       .ir_mode = UART3_IR,
 	       .enabled = UART3_ENABLED,
@@ -112,25 +100,92 @@ static uart_mxc_port mxc_ports[] = {
 	       },
 };
 
+static struct resource mxc_uart_resources1[] = {
+	{
+		.start = UART1_BASE_ADDR,
+		.end = UART1_BASE_ADDR + 0x0B5,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = UART1_INT1,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = UART1_INT2,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = UART1_INT3,
+		.flags = IORESOURCE_IRQ,
+	},
+
+};
+
 static struct platform_device mxc_uart_device1 = {
 	.name = "mxcintuart",
 	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_uart_resources1),
+	.resource = mxc_uart_resources1,
 	.dev = {
 		.platform_data = &mxc_ports[0],
 		},
 };
 
+static struct resource mxc_uart_resources2[] = {
+	{
+		.start = UART2_BASE_ADDR,
+		.end = UART2_BASE_ADDR + 0x0B5,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = UART2_INT1,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = UART2_INT2,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = UART2_INT3,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
 static struct platform_device mxc_uart_device2 = {
 	.name = "mxcintuart",
 	.id = 1,
+       .num_resources = ARRAY_SIZE(mxc_uart_resources2),
+	.resource = mxc_uart_resources2,
 	.dev = {
 		.platform_data = &mxc_ports[1],
 		},
 };
 
+static struct resource mxc_uart_resources3[] = {
+	{
+		.start = UART3_BASE_ADDR,
+		.end = UART3_BASE_ADDR + 0x0B5,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = UART3_INT1,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = UART3_INT2,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		.start = UART3_INT3,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
 static struct platform_device mxc_uart_device3 = {
 	.name = "mxcintuart",
 	.id = 2,
+       .num_resources = ARRAY_SIZE(mxc_uart_resources3),
+	.resource = mxc_uart_resources3,
 	.dev = {
 		.platform_data = &mxc_ports[2],
 		},