ENGR00124989-1 MX508:Configure ELCDIF pads attribute

1) Enable keepers for LCDIF pads.
2) Remove input path selection for LCDIF pads.

Signed-off-by: Liu Ying <b17645@freescale.com>

2 files changed, 58 insertions, 46 deletions

diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c
index 1e656d65ad9e..1dd3228a585d 100644
--- a/arch/arm/mach-mx5/mx50_arm2.c
+++ b/arch/arm/mach-mx5/mx50_arm2.c
@@ -345,27 +345,59 @@ static void wvga_reset(void)
 	/* ELCDIF D0 */
 	mxc_free_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D0, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D1 */
 	mxc_free_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D1, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D2 */
 	mxc_free_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D2, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D3 */
 	mxc_free_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D3, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D4 */
 	mxc_free_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D4, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D5 */
 	mxc_free_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D5, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D6 */
 	mxc_free_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D6, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	/* ELCDIF D7 */
 	mxc_free_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
 	mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX50_PIN_DISP_D7, PAD_CTL_PKE_ENABLE |
+			  PAD_CTL_PUE_KEEPER |
+			  PAD_CTL_ODE_OPENDRAIN_NONE |
+			  PAD_CTL_DRV_HIGH);
 	return;
 }
 
diff --git a/arch/arm/mach-mx5/mx50_arm2_gpio.c b/arch/arm/mach-mx5/mx50_arm2_gpio.c
index 1835f51afe28..d2586d7486f8 100644
--- a/arch/arm/mach-mx5/mx50_arm2_gpio.c
+++ b/arch/arm/mach-mx5/mx50_arm2_gpio.c
@@ -287,88 +287,68 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
 	 },
 	{ /* ELCDIF D8 */
 	 MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D9 */
 	 MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D10 */
 	 MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D11 */
 	 MX50_PIN_DISP_D11, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D12 */
 	 MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D13 */
 	 MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D14 */
 	 MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF D15 */
 	 MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF VSYNC */
 	 MX50_PIN_DISP_RS, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_VSYNC_I_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF contrast */
 	 MX50_PIN_DISP_BUSY, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF HSYNC */
 	 MX50_PIN_DISP_CS, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
-	 MUX_IN_ELCDIF_LCDIF_BUSY_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF DRDY */
 	 MX50_PIN_DISP_RD, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* ELCDIF PIXCLK */
 	 MX50_PIN_DISP_WR, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_HIGH),
+	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
 	 },
 	{ /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
 	 MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1,