imx6:phyflex: Add support for duallite and single

Add support for duallite and single core version of i.MX6 CPU

Signed-off-by: Christian Hemp <c.hemp@phytec.de>

4 files changed, 213 insertions, 10 deletions

diff --git a/arch/arm/mach-mx6/board-mx6dl_phyflex.h b/arch/arm/mach-mx6/board-mx6dl_phyflex.h
new file mode 100644
index 000000000000..f2ad9316e18f
--- /dev/null
+++ b/arch/arm/mach-mx6/board-mx6dl_phyflex.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2013 Phytec Messtechnik GmbH
+ *      
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+        
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _BOARD_MX6DL_PHYFLEX_H
+#define _BOARD_MX6DL_PHYFLEX_H
+#include <mach/iomux-mx6dl.h>
+
+static iomux_v3_cfg_t mx6dl_phyflex_pads[] = {
+
+	/* GPIOs for revision control */
+	MX6DL_PAD_SD4_DAT4__GPIO_2_12,
+	MX6DL_PAD_SD4_DAT5__GPIO_2_13,
+	MX6DL_PAD_SD4_DAT6__GPIO_2_14,
+	MX6DL_PAD_SD4_DAT7__GPIO_2_15,
+
+	/* User LEDs */
+	MX6DL_PAD_ENET_TXD0__GPIO_1_30,
+	MX6DL_PAD_EIM_EB3__GPIO_2_31,
+
+	MX6DL_PAD_EIM_D25__UART3_RXD,
+	MX6DL_PAD_EIM_D24__UART3_TXD,
+	MX6DL_PAD_EIM_D30__UART3_CTS,
+	MX6DL_PAD_EIM_D31__UART3_RTS,
+
+	/* UART4 */
+	MX6DL_PAD_KEY_COL0__UART4_TXD,
+	MX6DL_PAD_KEY_ROW0__UART4_RXD,
+
+	/* Ethernet */
+	MX6DL_PAD_ENET_MDIO__ENET_MDIO,
+	MX6DL_PAD_ENET_MDC__ENET_MDC,
+	MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
+	MX6DL_PAD_ENET_TX_EN__ENET_TX_EN,
+	MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
+	MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
+	MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
+	MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
+	MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
+	MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
+	MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
+	MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
+	MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
+	MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
+	MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
+	MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+	MX6DL_PAD_EIM_D23__GPIO_3_23,
+	
+	/* USDHC2 */
+	MX6DL_PAD_SD2_CLK__USDHC2_CLK,
+	MX6DL_PAD_SD2_CMD__USDHC2_CMD,
+	MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
+	/* SD2_CD and SD2_WP */
+	MX6DL_PAD_GPIO_2__GPIO_1_2,
+        MX6DL_PAD_GPIO_4__GPIO_1_4,
+
+	/* USDHC3 */
+	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
+	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
+	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
+	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
+	MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
+	MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
+	MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
+	MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
+	/* SD3_CD and SD3_WP */
+	MX6DL_PAD_ENET_RXD0__GPIO_1_27,
+	MX6DL_PAD_ENET_TXD1__GPIO_1_29,
+
+	/* SPI 3 */
+	MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK,
+	MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI,
+	MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO,
+	MX6DL_PAD_DISP0_DAT3__GPIO_4_24,
+	MX6DL_PAD_DISP0_DAT4__GPIO_4_25,
+	MX6DL_PAD_DISP0_DAT5__GPIO_4_26,
+	MX6DL_PAD_EIM_D29__GPIO_3_29,
+
+	/* GPIOs */
+	MX6DL_PAD_DISP0_DAT14__GPIO_5_8,
+	MX6DL_PAD_DISP0_DAT13__GPIO_5_7,
+	MX6DL_PAD_DI0_PIN2__GPIO_4_18,
+	MX6DL_PAD_DI0_PIN3__GPIO_4_19,
+	MX6DL_PAD_GPIO_6__GPIO_1_6,
+	MX6DL_PAD_GPIO_9__GPIO_1_9,
+	MX6DL_PAD_GPIO_17__GPIO_7_12,
+	MX6DL_PAD_GPIO_18__GPIO_7_13,
+	MX6DL_PAD_GPIO_19__GPIO_4_5,
+	MX6DL_PAD_EIM_CS0__GPIO_2_23,
+
+	/* I2C1 */
+	MX6DL_PAD_EIM_D28__I2C1_SDA,
+	MX6DL_PAD_EIM_D21__I2C1_SCL,
+
+	/* I2C2 */
+	MX6DL_PAD_EIM_EB2__I2C2_SCL,
+	MX6DL_PAD_EIM_D16__I2C2_SDA,
+
+	/* I2C3 */
+	MX6DL_PAD_EIM_D17__I2C3_SCL,
+	MX6DL_PAD_EIM_D18__I2C3_SDA,
+
+	/* Display */
+	MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+	MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN4,
+	MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+	MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+	MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+	MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+	MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+	MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+	MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+	MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+	MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+	MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+	MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+
+	/* LVDS0 BACKLIGHT ENABLE */
+	MX6DL_PAD_GPIO_8__GPIO_1_8,
+
+	/* PWM1 */
+	MX6DL_PAD_DISP0_DAT8__PWM1_PWMO,
+        MX6DL_PAD_DISP0_DAT9__PWM2_PWMO,
+
+	/* HDMI */
+	MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL,
+	MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA,
+	MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE,
+};
+
+#endif  /* _BOARD_MX6DL_PHYFLEX_H */
diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.c b/arch/arm/mach-mx6/board-mx6q_phyflex.c
index d5462bccc514..1d85892a6947 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.c
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.c
@@ -92,6 +92,7 @@
 #include "crm_regs.h"
 #include "cpu_op-mx6.h"
 #include "board-mx6q_phyflex.h"
+#include "board-mx6dl_phyflex.h"
 
 #include "board-mx6q_phytec-common.h"
 #include "board-mx6q_phytec-sd.h"
@@ -1173,17 +1174,32 @@ static void __init mx6_phyflex_init(void)
 	long csi0_cam_address_hex;
 	long csi1_cam_address_hex;
 	
+	if (cpu_is_mx6q()) {
+		 mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_common_pads,
+						ARRAY_SIZE(mx6q_phytec_common_pads));
+	} else if (cpu_is_mx6dl()) {
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_phyflex_pads,
+						ARRAY_SIZE(mx6dl_phyflex_pads));
+	}
+
 	/* imx6q SoC revision and CPU uniq ID setup */
 	mx6_setup_cpuinfo();
 
-	mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_common_pads, ARRAY_SIZE(mx6q_phytec_common_pads));
-	
+
 	if (module_rev == PHYFLEX_MODULE_REV_1) {
-		mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_rev1_pads,
+		if (cpu_is_mx6q()) {
+			mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_rev1_pads,
 						ARRAY_SIZE(mx6q_phytec_rev1_pads));
+		} else if (cpu_is_mx6dl()) {
+//			mxc_iomux_v3_setup_multiple_pads();
+		}
 	} else {
-		mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_rev2_pads,
+		if (cpu_is_mx6q()) {
+			mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_rev2_pads,
 						ARRAY_SIZE(mx6q_phytec_rev2_pads));
+		} else if (cpu_is_mx6dl()) {
+//			mxc_iomux_v3_setup_multiple_pads();
+		}
 		mx6_phyflex_pcie_data.pcie_rst = IMX_GPIO_NR(4, 17);
 	}
 
@@ -1205,14 +1221,23 @@ static void __init mx6_phyflex_init(void)
 
 	/* Video devices initialization */
 	imx6q_add_ipuv3(0, &ipu_data[0]);
-	imx6q_add_ipuv3(1, &ipu_data[1]);
-	for (i = 0; i < ARRAY_SIZE(phyflex_fb_data); i++)
-		imx6q_add_ipuv3fb(i, &phyflex_fb_data[i]);
+	if(cpu_is_mx6q()) {
+		imx6q_add_ipuv3(1, &ipu_data[1]);
+		for (i = 0; i < ARRAY_SIZE(phyflex_fb_data); i++)
+			imx6q_add_ipuv3fb(i, &phyflex_fb_data[i]);
+	} else {
+		ldb_data.ipu_id = 0;
+                ldb_data.disp_id = 0;
+		for (i = 0; i < ARRAY_SIZE(phyflex_fb_data) / 2; i++)
+			imx6q_add_ipuv3fb(i, &phyflex_fb_data[i]);
+	}
+
 
 	imx6q_add_ldb(&ldb_data);
 
 	imx6q_add_v4l2_output(0);
-	
+
+if(cpu_is_mx6q()) {	
 	/***************************************************************************
 	Camera section:
 	The bootargs csi0 and csi1 will be interpreted. 
@@ -1453,7 +1478,7 @@ static void __init mx6_phyflex_init(void)
 
 	imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata);
 	imx6q_add_vpu();
-
+}
 	/* Initialize SoC RTC */
 	imx6q_add_imx_snvs_rtc();
 
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-sd.c b/arch/arm/mach-mx6/board-mx6q_phytec-sd.c
index 68280747b060..c963048fd3cd 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-sd.c
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-sd.c
@@ -35,6 +35,10 @@ static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING_SHORT(2, 50);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING_SHORT(2, 100);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING_SHORT(2, 200);
 
+static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING_SHORT(3, 50);
+static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING_SHORT(3, 100);
+static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING_SHORT(3, 200);
+
 enum sd_pad_mode {
 	SD_PAD_MODE_LOW_SPEED,
 	SD_PAD_MODE_MED_SPEED,
@@ -101,6 +105,11 @@ static int plt_sd3_pad_change(unsigned int index, int clock)
 	u32 sd3_pads_100mhz_cnt;
 	u32 sd3_pads_50mhz_cnt;
 
+	if (index != 2) {
+		printk(KERN_ERR"no such SD host controller index %d\n", index);
+		return -EINVAL;
+	}
+
 	if (cpu_is_mx6q()) {
 		sd3_pads_200mhz = mx6q_sd3_200mhz;
 		sd3_pads_100mhz = mx6q_sd3_100mhz;
@@ -109,6 +118,14 @@ static int plt_sd3_pad_change(unsigned int index, int clock)
 		sd3_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd3_200mhz);
 		sd3_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd3_100mhz);
 		sd3_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd3_50mhz);
+	} else if (cpu_is_mx6dl()) {
+		sd3_pads_200mhz = mx6dl_sd3_200mhz;
+		sd3_pads_100mhz = mx6dl_sd3_100mhz;
+		sd3_pads_50mhz = mx6dl_sd3_50mhz;
+
+		sd3_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd3_200mhz);
+		sd3_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd3_100mhz);
+		sd3_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd3_50mhz);
 	}
 
 	if (clock > 100000000) {
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-sd.h b/arch/arm/mach-mx6/board-mx6q_phytec-sd.h
index 798f360f7c62..365cdeb35f17 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-sd.h
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-sd.h
@@ -2,6 +2,7 @@
 #define __BOARD_MX6Q_PHYTEC_SD_H__
 
 #include <mach/iomux-mx6q.h>
+#include <mach/iomux-mx6dl.h>
 
 #define MX6Q_USDHC_PAD_SETTING(id, speed)       \
 mx6q_sd##id##_##speed##mhz[] = {                \
@@ -27,6 +28,16 @@ mx6q_sd##id##_##speed##mhz[] = {                \
 	MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ,  \
 }
 
+#define MX6DL_USDHC_PAD_SETTING_SHORT(id, speed) \
+mx6dl_sd##id##_##speed##mhz[] = {                \
+        MX6DL_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ,    \
+        MX6DL_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ,    \
+        MX6DL_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ,  \
+        MX6DL_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ,  \
+        MX6DL_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ,  \
+        MX6DL_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ,  \
+}
+
 extern void __init board_esdhc_init(char id, int cd_gpio, int wp_gpio);
 
-#endif /* __BOARD_MX6Q_PHYTEC_SD_H__ */
\ No newline at end of file
+#endif /* __BOARD_MX6Q_PHYTEC_SD_H__ */