Merge commit 'rel_imx_3.0.35_12.09.02_RC1' into imx_3.0.35_android_r13.5-beta

Conflicts: arch/arm/mach-mx6/board-mx6q_sabresd.c arch/arm/mach-mx6/board-mx6sl_arm2.c arch/arm/mach-mx6/bus_freq.c arch/arm/mach-mx6/cpu_op-mx6.c arch/arm/plat-mxc/cpufreq.c Signed-off-by: Jack Lee <jacklee@freescale.com>
author: Jack Lee <jacklee@freescale.com> 2012-09-05 10:21:49 +0800
committer: Jack Lee <jacklee@freescale.com> 2012-09-05 10:21:49 +0800
commit: a0619e1d6c1c51a367b8d0bf74bb9058df919545 (patch)
tree: d40e30c91892ea35c82d22a8364b9b9548e42b7a
parent: 65745dd4b7f80711d03dce5529fc501162428c53 (diff)
parent: 85a6685fb327f1eebaeea5dfc04a6750573472ef (diff)
82 files changed, 7375 insertions, 1018 deletions
diff --git a/arch/arm/configs/imx6_updater_defconfig b/arch/arm/configs/imx6_updater_defconfig
index 5fad815940e8..02b3707f62d0 100644
--- a/arch/arm/configs/imx6_updater_defconfig
+++ b/arch/arm/configs/imx6_updater_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux/arm 3.0.15 Kernel Configuration
+# Linux/arm 3.0.35 Kernel Configuration
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
@@ -265,6 +265,7 @@ CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
@@ -278,10 +279,14 @@ CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
 CONFIG_IMX_HAVE_PLATFORM_AHCI=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_DCP=y
+CONFIG_IMX_HAVE_PLATFORM_RANDOM_RNGC=y
 CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
 CONFIG_IMX_HAVE_PLATFORM_LDB=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDC=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
 CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
 CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
@@ -326,6 +331,7 @@ CONFIG_MXC_PWM=y
 # CONFIG_MXC_DEBUG_BOARD is not set
 # CONFIG_MXC_REBOOT_MFGMODE is not set
 # CONFIG_MXC_REBOOT_ANDROID_CMD is not set
+CONFIG_ARCH_HAS_RNGC=y
 CONFIG_ARCH_MXC_IOMUX_V3=y
 CONFIG_ARCH_MXC_AUDMUX_V2=y
 CONFIG_IRAM_ALLOC=y
@@ -1064,6 +1070,7 @@ CONFIG_FSL_OTP=y
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_FSL_RNGC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
@@ -1185,7 +1192,20 @@ CONFIG_GPIOLIB=y
 # MODULbus GPIO expanders:
 #
 # CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_GPIO is not set
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_WATCHDOG=y
@@ -1396,25 +1416,15 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_THS7303 is not set
 # CONFIG_VIDEO_M52790 is not set
 # CONFIG_VIDEO_VIVI is not set
-CONFIG_VIDEO_MXC_CAMERA=m
-
-#
-# MXC Camera/V4L2 PRP Features support
-#
-CONFIG_VIDEO_MXC_IPU_CAMERA=y
-# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
+# CONFIG_VIDEO_MXC_CAMERA is not set
 # CONFIG_MXC_CAMERA_MICRON111 is not set
 # CONFIG_MXC_CAMERA_OV2640 is not set
-CONFIG_MXC_CAMERA_OV3640=m
-CONFIG_MXC_CAMERA_OV5640=m
+# CONFIG_MXC_CAMERA_OV3640 is not set
+# CONFIG_MXC_CAMERA_OV5640 is not set
 # CONFIG_MXC_CAMERA_OV8820_MIPI is not set
-CONFIG_MXC_CAMERA_OV5642=m
+# CONFIG_MXC_CAMERA_OV5642 is not set
 # CONFIG_MXC_TVIN_ADV7180 is not set
-# CONFIG_MXC_CAMERA_OV5640_MIPI is not set
-CONFIG_MXC_CAMERA_SENSOR_CLK=m
-CONFIG_MXC_IPU_PRP_VF_SDC=m
-CONFIG_MXC_IPU_PRP_ENC=m
-CONFIG_MXC_IPU_CSI_ENC=m
+# CONFIG_MXC_IPU_DEVICE_QUEUE_SDC is not set
 CONFIG_VIDEO_MXC_OUTPUT=y
 CONFIG_VIDEO_MXC_IPU_OUTPUT=y
 # CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
@@ -1483,6 +1493,7 @@ CONFIG_FB_MXC_LDB=y
 # CONFIG_FB_MXC_TVOUT_CH7024 is not set
 # CONFIG_FB_MXC_ASYNC_PANEL is not set
 # CONFIG_FB_MXC_EINK_PANEL is not set
+# CONFIG_FB_MXC_SIPIX_PANEL is not set
 # CONFIG_FB_MXC_ELCDIF_FB is not set
 CONFIG_FB_MXC_HDMI=y
 
@@ -1731,6 +1742,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
 CONFIG_USB_GADGET_ARC=y
+# CONFIG_IMX_USB_CHARGER is not set
 CONFIG_USB_ARC=y
 # CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_FUSB300 is not set
@@ -2009,6 +2021,11 @@ CONFIG_MXC_ASRC=y
 # CONFIG_MXC_MIPI_CSI2 is not set
 
 #
+# MXC HDMI CEC (Consumer Electronics Control) support
+#
+# CONFIG_MXC_HDMI_CEC is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
@@ -2349,6 +2366,7 @@ CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_USER_API_SKCIPHER is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_FSL_CAAM is not set
+# CONFIG_CRYPTO_DEV_DCP is not set
 # CONFIG_BINARY_PRINTF is not set
 
 #
diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig
index 04c445e3258b..f03e456d7386 100644
--- a/arch/arm/configs/imx6s_defconfig
+++ b/arch/arm/configs/imx6s_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux/arm 3.0.15 Kernel Configuration
+# Linux/arm 3.0.35 Kernel Configuration
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
@@ -311,6 +311,7 @@ CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
 CONFIG_MACH_MX6Q_ARM2=y
 CONFIG_MACH_MX6SL_ARM2=y
+CONFIG_MACH_MX6SL_EVK=y
 # CONFIG_MACH_MX6Q_SABRELITE is not set
 CONFIG_MACH_MX6Q_SABRESD=y
 # CONFIG_MACH_MX6Q_SABREAUTO is not set
@@ -319,6 +320,7 @@ CONFIG_MACH_MX6Q_SABRESD=y
 # MX6 Options:
 #
 # CONFIG_IMX_PCIE is not set
+CONFIG_USB_EHCI_ARC_H1=y
 CONFIG_MX6_INTER_LDO_BYPASS=y
 CONFIG_ISP1504_MXC=y
 # CONFIG_MXC_IRQ_PRIOR is not set
@@ -1380,8 +1382,8 @@ CONFIG_SENSORS_MAX17135=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 CONFIG_SENSORS_MAG3110=y
-# CONFIG_MXC_MMA8450 is not set
-CONFIG_MXC_MMA8451=y
+CONFIG_MXC_MMA8450=y
+# CONFIG_MXC_MMA8451 is not set
 CONFIG_THERMAL=y
 # CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
@@ -1593,25 +1595,7 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_THS7303 is not set
 # CONFIG_VIDEO_M52790 is not set
 # CONFIG_VIDEO_VIVI is not set
-CONFIG_VIDEO_MXC_CAMERA=m
-
-#
-# MXC Camera/V4L2 PRP Features support
-#
-CONFIG_VIDEO_MXC_IPU_CAMERA=y
-# CONFIG_VIDEO_MXC_CSI_CAMERA is not set
-# CONFIG_MXC_CAMERA_MICRON111 is not set
-# CONFIG_MXC_CAMERA_OV2640 is not set
-CONFIG_MXC_CAMERA_OV3640=m
-CONFIG_MXC_CAMERA_OV5640=m
-CONFIG_MXC_CAMERA_OV8820_MIPI=m
-CONFIG_MXC_CAMERA_OV5642=m
-CONFIG_MXC_TVIN_ADV7180=m
-CONFIG_MXC_CAMERA_OV5640_MIPI=m
-CONFIG_MXC_CAMERA_SENSOR_CLK=m
-CONFIG_MXC_IPU_PRP_VF_SDC=m
-CONFIG_MXC_IPU_PRP_ENC=m
-CONFIG_MXC_IPU_CSI_ENC=m
+# CONFIG_VIDEO_MXC_CAMERA is not set
 CONFIG_VIDEO_MXC_OUTPUT=y
 CONFIG_VIDEO_MXC_IPU_OUTPUT=y
 # CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
@@ -1924,7 +1908,6 @@ CONFIG_USB_OTG=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ARC=y
 CONFIG_USB_EHCI_ARC_OTG=y
-CONFIG_USB_EHCI_ARC_H1=y
 # CONFIG_USB_EHCI_ARC_HSIC is not set
 # CONFIG_USB_STATIC_IRAM is not set
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
diff --git a/arch/arm/configs/imx6s_updater_defconfig b/arch/arm/configs/imx6s_updater_defconfig
new file mode 100644
index 000000000000..0bd3bcaac829
--- /dev/null
+++ b/arch/arm/configs/imx6s_updater_defconfig
@@ -0,0 +1,2376 @@
+#
+# Automatically generated make config: don't edit
+# Linux/arm 3.0.35 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_PREEMPT_RCU=y
+# CONFIG_TINY_RCU is not set
+# CONFIG_TINY_PREEMPT_RCU is not set
+CONFIG_PREEMPT_RCU=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_BOOST is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_IMX_HAVE_PLATFORM_DMA=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_MLB=y
+CONFIG_IMX_HAVE_PLATFORM_FEC=y
+CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
+CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y
+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_DCP=y
+CONFIG_IMX_HAVE_PLATFORM_RANDOM_RNGC=y
+CONFIG_IMX_HAVE_PLATFORM_PERFMON=y
+CONFIG_IMX_HAVE_PLATFORM_LDB=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
+CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y
+CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y
+
+#
+# Freescale MXC Implementations
+#
+# CONFIG_ARCH_MX1 is not set
+# CONFIG_ARCH_MX2 is not set
+# CONFIG_ARCH_MX25 is not set
+# CONFIG_ARCH_MX3 is not set
+# CONFIG_ARCH_MX503 is not set
+# CONFIG_ARCH_MX51 is not set
+CONFIG_ARCH_MX6=y
+CONFIG_ARCH_MX6Q=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_MACH_MX6Q_ARM2=y
+CONFIG_MACH_MX6SL_ARM2=y
+CONFIG_MACH_MX6SL_EVK=y
+CONFIG_MACH_MX6Q_SABRELITE=y
+CONFIG_MACH_MX6Q_SABRESD=y
+CONFIG_MACH_MX6Q_SABREAUTO=y
+
+#
+# MX6 Options:
+#
+# CONFIG_IMX_PCIE is not set
+CONFIG_MX6_INTER_LDO_BYPASS=y
+CONFIG_ISP1504_MXC=y
+# CONFIG_MXC_IRQ_PRIOR is not set
+CONFIG_MXC_PWM=y
+# CONFIG_MXC_DEBUG_BOARD is not set
+# CONFIG_MXC_REBOOT_MFGMODE is not set
+# CONFIG_MXC_REBOOT_ANDROID_CMD is not set
+CONFIG_ARCH_HAS_RNGC=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
+CONFIG_ARCH_MXC_AUDMUX_V2=y
+CONFIG_IRAM_ALLOC=y
+CONFIG_CLK_DEBUG=y
+CONFIG_DMA_ZONE_SIZE=184
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+CONFIG_ARM_ERRATA_743622=y
+# CONFIG_ARM_ERRATA_753970 is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_GIC=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_SMP is not set
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0x80000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+# CONFIG_USE_OF is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_AUTO_ZRELADDR=y
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_IMX=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_APM_EMULATION=y
+CONFIG_PM_RUNTIME_CLK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=y
+# CONFIG_CAN_SLCAN is not set
+# CONFIG_CAN_DEV is not set
+CONFIG_HAVE_CAN_FLEXCAN=y
+CONFIG_CAN_DEBUG_DEVICES=y
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+CONFIG_BT_HCIVHCI=y
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_GPMI_NAND is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_SATA_MV is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ARASAN_CF is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_PLATFORM is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_FEC=y
+# CONFIG_FEC_NAPI is not set
+# CONFIG_FEC_1588 is not set
+# CONFIG_FTMAC100 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+CONFIG_TOUCHSCREEN_EGALAX=y
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_P1003 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_ISL29023 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_FSL_OTP=y
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_FSL_RNGC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_MXS_VIIM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_IMX_VER_2_3=y
+CONFIG_SPI_IMX=y
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_BASIC_MMIO is not set
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_IMX2_WDT=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_PMIC_DIALOG is not set
+# CONFIG_MFD_MC_PMIC is not set
+# CONFIG_MFD_MC34708 is not set
+CONFIG_MFD_PFUZE=y
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65910 is not set
+CONFIG_MFD_MAX17135=y
+CONFIG_MFD_MXC_HDMI=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_MC34708 is not set
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+CONFIG_REGULATOR_ANATOP=y
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_MAX17135=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_MXC_CAMERA is not set
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set
+# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
+# CONFIG_VIDEO_MXC_OPL is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_V4L_USB_DRIVERS is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_EDID=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set
+CONFIG_FB_MXC_LDB=y
+# CONFIG_FB_MXC_MIPI_DSI is not set
+# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set
+# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set
+# CONFIG_FB_MXC_SII902X is not set
+# CONFIG_FB_MXC_CH7026 is not set
+# CONFIG_FB_MXC_TVOUT_CH7024 is not set
+# CONFIG_FB_MXC_ASYNC_PANEL is not set
+# CONFIG_FB_MXC_EINK_PANEL is not set
+# CONFIG_FB_MXC_SIPIX_PANEL is not set
+# CONFIG_FB_MXC_ELCDIF_FB is not set
+CONFIG_FB_MXC_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_MXC_SOC_MX2=y
+# CONFIG_SND_SOC_IMX_SGTL5000 is not set
+# CONFIG_SND_SOC_IMX_WM8962 is not set
+CONFIG_SND_SOC_IMX_CS42888=y
+# CONFIG_SND_SOC_IMX_SI4763 is not set
+# CONFIG_SND_SOC_IMX_SPDIF is not set
+# CONFIG_SND_SOC_IMX_HDMI is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_CS42888=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+# CONFIG_HID_PRODIKEYS is not set
+CONFIG_HID_CYPRESS=m
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+CONFIG_HID_GYRATION=m
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWII_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_ARVO is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_ROCCAT_KONEPLUS is not set
+# CONFIG_HID_ROCCAT_KOVAPLUS is not set
+# CONFIG_HID_ROCCAT_PYRA is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_ARC=y
+# CONFIG_IMX_USB_CHARGER is not set
+CONFIG_USB_ARC=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_FUSB300 is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA_U2O is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=y
+CONFIG_FSL_UTP=y
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_DRV_SNVS=y
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_DW_DMAC is not set
+# CONFIG_MXC_PXP_V2 is not set
+# CONFIG_TIMB_DMA is not set
+CONFIG_IMX_SDMA=y
+# CONFIG_MXS_DMA is not set
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+CONFIG_STAGING=y
+# CONFIG_USBIP_CORE is not set
+# CONFIG_ECHO is not set
+# CONFIG_BRCMUTIL is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_R8712U is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_VT6656 is not set
+# CONFIG_IIO is not set
+# CONFIG_XVMALLOC is not set
+# CONFIG_ZRAM is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_EASYCAP is not set
+CONFIG_MACH_NO_WESTBRIDGE=y
+# CONFIG_USB_ENESTORAGE is not set
+# CONFIG_BCM_WIMAX is not set
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+
+#
+# MXC support drivers
+#
+CONFIG_MXC_IPU=y
+CONFIG_MXC_IPU_V3=y
+CONFIG_MXC_IPU_V3H=y
+
+#
+# MXC SSI support
+#
+# CONFIG_MXC_SSI is not set
+
+#
+# MXC Digital Audio Multiplexer support
+#
+# CONFIG_MXC_DAM is not set
+
+#
+# MXC PMIC support
+#
+# CONFIG_MXC_PMIC_MC13783 is not set
+# CONFIG_MXC_PMIC_MC13892 is not set
+# CONFIG_MXC_PMIC_MC34704 is not set
+# CONFIG_MXC_PMIC_MC9SDZ60 is not set
+# CONFIG_MXC_PMIC_MC9S08DZ60 is not set
+
+#
+# MXC Security Drivers
+#
+# CONFIG_MXC_SECURITY_SCC is not set
+# CONFIG_MXC_SECURITY_RNG is not set
+
+#
+# MXC MPEG4 Encoder Kernel module support
+#
+# CONFIG_MXC_HMP4E is not set
+
+#
+# MXC HARDWARE EVENT
+#
+# CONFIG_MXC_HWEVENT is not set
+
+#
+# MXC VPU(Video Processing Unit) support
+#
+CONFIG_MXC_VPU=y
+# CONFIG_MXC_VPU_DEBUG is not set
+# CONFIG_MX6_VPU_352M is not set
+
+#
+# MXC Asynchronous Sample Rate Converter support
+#
+CONFIG_MXC_ASRC=y
+
+#
+# MXC Bluetooth support
+#
+
+#
+# Broadcom GPS ioctrl support
+#
+
+#
+# MXC Media Local Bus Driver
+#
+# CONFIG_MXC_MLB150 is not set
+
+#
+# i.MX ADC support
+#
+# CONFIG_IMX_ADC is not set
+
+#
+# MXC Vivante GPU support
+#
+# CONFIG_MXC_GPU_VIV is not set
+
+#
+# ANATOP_THERMAL
+#
+# CONFIG_ANATOP_THERMAL is not set
+
+#
+# MXC MIPI Support
+#
+# CONFIG_MXC_MIPI_CSI2 is not set
+
+#
+# MXC HDMI CEC (Consumer Electronics Control) support
+#
+# CONFIG_MXC_HDMI_CEC is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+# CONFIG_LKDTM is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CRYPTODEV=y
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
+# CONFIG_CRYPTO_DEV_DCP is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index a9098ca89a33..5eaa7a2f4240 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -211,8 +211,6 @@ extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
  */
 extern void *dma_alloc_writethrough(struct device *, size_t, dma_addr_t *, gfp_t);
 
-
-#ifdef CONFIG_FSL_UTP
 /**
  * dma_alloc_noncacheable - allocate consistent memory for DMA
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -225,7 +223,6 @@ extern void *dma_alloc_writethrough(struct device *, size_t, dma_addr_t *, gfp_t
  * device-viewed address.
  */
 extern void *dma_alloc_noncacheable(struct device *, size_t, dma_addr_t *, gfp_t);
-#endif
 
 /**
  * dma_free_coherent - free memory allocated by dma_alloc_coherent
diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index 08875a60a31c..45ae9eac67d2 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -107,6 +107,43 @@ config MACH_MX6SL_ARM2
 	  Include support for i.MX 6Sololite Armadillo2 platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_MX6SL_EVK
+	bool "Support i.MX 6SoloLite EVK platform"
+	select ARCH_MX6Q
+	select SOC_IMX6SL
+	select IMX_HAVE_PLATFORM_IMX_UART
+	select IMX_HAVE_PLATFORM_DMA
+	select IMX_HAVE_PLATFORM_FEC
+	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+	select IMX_HAVE_PLATFORM_SPI_IMX
+	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_VIV_GPU
+	select IMX_HAVE_PLATFORM_IMX_DVFS
+	select IMX_HAVE_PLATFORM_IMX_SSI
+	select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL
+	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+	select IMX_HAVE_PLATFORM_MXC_EHCI
+	select IMX_HAVE_PLATFORM_FSL_OTG
+	select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP
+	select IMX_HAVE_PLATFORM_AHCI
+	select IMX_HAVE_PLATFORM_IMX_OCOTP
+	select IMX_HAVE_PLATFORM_IMX_VIIM
+	select IMX_HAVE_PLATFORM_IMX2_WDT
+	select IMX_HAVE_PLATFORM_IMX_SNVS_RTC
+	select IMX_HAVE_PLATFORM_IMX_PM
+	select IMX_HAVE_PLATFORM_IMX_SPDIF
+	select IMX_HAVE_PLATFORM_PERFMON
+	select IMX_HAVE_PLATFORM_IMX_EPDC
+	select IMX_HAVE_PLATFORM_IMX_SPDC
+	select IMX_HAVE_PLATFORM_IMX_PXP
+	select IMX_HAVE_PLATFORM_IMX_KEYPAD
+	select IMX_HAVE_PLATFORM_IMX_DCP
+	select IMX_HAVE_PLATFORM_RANDOM_RNGC
+	select ARCH_HAS_RNGC
+	help
+	  Include support for i.MX 6Sololite EVK platform. This includes specific
+	  configurations for the board and its peripherals.
+
 config MACH_MX6Q_SABRELITE
 	bool "Support i.MX 6Quad SABRE Lite platform"
 	select ARCH_MX6Q
diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
index 24dae23dd089..49b5f86a6920 100644
--- a/arch/arm/mach-mx6/Makefile
+++ b/arch/arm/mach-mx6/Makefile
@@ -5,15 +5,16 @@
 # Object file lists.
 obj-y   := cpu.o mm.o system.o devices.o dummy_gpio.o irq.o bus_freq.o usb_dr.o usb_h2.o usb_h3.o\
 pm.o cpu_op-mx6.o mx6_wfi.o mx6_fec.o mx6_anatop_regulator.o cpu_regulator-mx6.o \
-mx6_mmdc.o mx6_ddr_freq.o
+mx6_mmdc.o mx6_ddr_freq.o mx6sl_ddr.o mx6sl_wfi.o
 
 obj-$(CONFIG_ARCH_MX6) += clock.o mx6_suspend.o clock_mx6sl.o
 obj-$(CONFIG_MACH_MX6Q_ARM2) += board-mx6q_arm2.o
 obj-$(CONFIG_MACH_MX6SL_ARM2) += board-mx6sl_arm2.o mx6sl_arm2_pmic_pfuze100.o
+obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
 obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
 obj-$(CONFIG_SMP) += plat_hotplug.o platsmp.o headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_IMX_PCIE) += pcie.o
-obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
-\ No newline at end of file
+obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o
diff --git a/arch/arm/mach-mx6/board-mx6dl_arm2.h b/arch/arm/mach-mx6/board-mx6dl_arm2.h
index 6ed3e65e68ee..429febb9813d 100644
--- a/arch/arm/mach-mx6/board-mx6dl_arm2.h
+++ b/arch/arm/mach-mx6/board-mx6dl_arm2.h
@@ -188,7 +188,9 @@ static iomux_v3_cfg_t mx6dl_arm2_pads[] = {
 	MX6DL_PAD_GPIO_6__MLB_MLBSIG,
 	MX6DL_PAD_GPIO_2__MLB_MLBDAT,
 
-	/* EPDC pins */
+};
+
+static iomux_v3_cfg_t mx6dl_arm2_epdc_pads[] = {
 	MX6DL_PAD_EIM_A17__GPIO_2_21,
 	MX6DL_PAD_EIM_D17__GPIO_3_17,
 	MX6DL_PAD_EIM_A18__GPIO_2_20,
diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index 62db4d47ba41..c604319ef986 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -2005,12 +2005,14 @@ static void __init mx6_arm2_init(void)
 	iomux_v3_cfg_t *spdif_pads = NULL;
 	iomux_v3_cfg_t *flexcan_pads = NULL;
 	iomux_v3_cfg_t *i2c3_pads = NULL;
+	iomux_v3_cfg_t *epdc_pads = NULL;
 
 	int common_pads_cnt;
 	int esai_rec_pads_cnt;
 	int spdif_pads_cnt;
 	int flexcan_pads_cnt;
 	int i2c3_pads_cnt;
+	int epdc_pads_cnt;
 
 
 	/*
@@ -2036,12 +2038,14 @@ static void __init mx6_arm2_init(void)
 		spdif_pads = mx6dl_arm2_spdif_pads;
 		flexcan_pads = mx6dl_arm2_can_pads;
 		i2c3_pads = mx6dl_arm2_i2c3_pads;
+		epdc_pads = mx6dl_arm2_epdc_pads;
 
 		common_pads_cnt = ARRAY_SIZE(mx6dl_arm2_pads);
 		esai_rec_pads_cnt = ARRAY_SIZE(mx6dl_arm2_esai_record_pads);
 		spdif_pads_cnt =  ARRAY_SIZE(mx6dl_arm2_spdif_pads);
 		flexcan_pads_cnt = ARRAY_SIZE(mx6dl_arm2_can_pads);
 		i2c3_pads_cnt = ARRAY_SIZE(mx6dl_arm2_i2c3_pads);
+		epdc_pads_cnt = ARRAY_SIZE(mx6dl_arm2_epdc_pads);
 	}
 
 	BUG_ON(!common_pads);
@@ -2222,6 +2226,8 @@ static void __init mx6_arm2_init(void)
 	imx6q_add_mlb150(&mx6_arm2_mlb150_data);
 
 	if (cpu_is_mx6dl() && epdc_enabled) {
+		BUG_ON(!epdc_pads);
+		mxc_iomux_v3_setup_multiple_pads(epdc_pads, epdc_pads_cnt);
 		imx6dl_add_imx_pxp();
 		imx6dl_add_imx_pxp_client();
 		mxc_register_device(&max17135_sensor_device, NULL);
diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
index d972cda66750..530466dd7b2f 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
@@ -576,6 +576,15 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 	},
 };
 
+static void mx6q_csi0_cam_powerdown(int powerdown)
+{
+	if (powerdown)
+		gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 1);
+	else
+		gpio_set_value(MX6Q_SABRELITE_CSI0_PWN, 0);
+
+	msleep(2);
+}
 
 static void mx6q_csi0_io_init(void)
 {
@@ -616,6 +625,7 @@ static struct fsl_mxc_camera_platform_data camera_data = {
 	.mclk_source = 0,
 	.csi = 0,
 	.io_init = mx6q_csi0_io_init,
+	.pwdn = mx6q_csi0_cam_powerdown,
 };
 
 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
@@ -1260,6 +1270,10 @@ static void __init mx6_sabrelite_board_init(void)
 	clk_set_rate(clko2, rate);
 	clk_enable(clko2);
 	imx6q_add_busfreq();
+
+	imx6q_add_perfmon(0);
+	imx6q_add_perfmon(1);
+	imx6q_add_perfmon(2);
 }
 
 extern void __iomem *twd_base;
diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
index 3a02094869e7..9bb1ee3f93ed 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
@@ -1592,13 +1592,14 @@ static struct platform_pwm_backlight_data mx6_sabresd_pwm_backlight_data = {
 };
 
 static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
-	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.reg_id = "VDDCORE",
-	#else
+	.soc_id	= "VDDSOC",
+#else
 	.reg_id = "cpu_vddgp",
 	.soc_id = "cpu_vddsoc",
 	.pu_id = "cpu_vddvpu",
-	#endif
+#endif
 	.clk1_id = "cpu_clk",
 	.clk2_id = "gpc_dvfs_clk",
 	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
@@ -1824,12 +1825,9 @@ static void __init mx6_sabresd_board_init(void)
 	imx6q_add_dma();
 
 	imx6q_add_dvfs_core(&sabresd_dvfscore_data);
-	#ifndef CONFIG_MX6_INTER_LDO_BYPASS
+#ifndef CONFIG_MX6_INTER_LDO_BYPASS
 	mx6_cpu_regulator_init();
-	#endif
-
-	imx6q_add_ion(0, &imx_ion_data,
-		sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
+#endif
 	imx6q_add_device_buttons();
 
 	/* enable sensor 3v3 and 1v8 */
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index 249912b82d04..419b2447e215 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -33,7 +33,6 @@
 #include <linux/spi/flash.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
-#include <linux/ata.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
@@ -71,67 +70,11 @@
 #include "devices-imx6q.h"
 #include "crm_regs.h"
 #include "cpu_op-mx6.h"
-#include "board-mx6sl_arm2.h"
-
-#define MX6_ARM2_USBOTG1_PWR    IMX_GPIO_NR(4, 0)       /* KEY_COL4 */
-#define MX6_ARM2_USBOTG2_PWR    IMX_GPIO_NR(4, 2)       /* KEY_COL5 */
-#define MX6_ARM2_LCD_PWR_EN	IMX_GPIO_NR(4, 3)	/* KEY_ROW5 */
-#define MX6_ARM2_SD1_WP		IMX_GPIO_NR(4, 6)	/* KEY_COL7 */
-#define MX6_ARM2_SD1_CD		IMX_GPIO_NR(4, 7)	/* KEY_ROW7 */
-#define MX6_ARM2_ECSPI1_CS0	IMX_GPIO_NR(4, 11)	/* ECSPI1_SS0 */
-#define MX6_ARM2_HEADPHONE_DET	IMX_GPIO_NR(4, 19)	/* FEC_RX_ER */
-#define MX6_ARM2_SD2_WP		IMX_GPIO_NR(4, 29)	/* SD2_DAT6 */
-#define MX6_ARM2_SD2_CD		IMX_GPIO_NR(5, 0)	/* SD2_DAT7 */
-#define MX6_ARM2_SD3_CD		IMX_GPIO_NR(3, 22)	/* REF_CLK_32K */
-#define MX6_ARM2_FEC_PWR_EN	IMX_GPIO_NR(4, 21)	/* FEC_TX_CLK */
-
-/* EPDC GPIO pins */
-#define MX6SL_ARM2_EPDC_SDDO_0		IMX_GPIO_NR(1, 7)
-#define MX6SL_ARM2_EPDC_SDDO_1		IMX_GPIO_NR(1, 8)
-#define MX6SL_ARM2_EPDC_SDDO_2		IMX_GPIO_NR(1, 9)
-#define MX6SL_ARM2_EPDC_SDDO_3		IMX_GPIO_NR(1, 10)
-#define MX6SL_ARM2_EPDC_SDDO_4		IMX_GPIO_NR(1, 11)
-#define MX6SL_ARM2_EPDC_SDDO_5		IMX_GPIO_NR(1, 12)
-#define MX6SL_ARM2_EPDC_SDDO_6		IMX_GPIO_NR(1, 13)
-#define MX6SL_ARM2_EPDC_SDDO_7		IMX_GPIO_NR(1, 14)
-#define MX6SL_ARM2_EPDC_SDDO_8		IMX_GPIO_NR(1, 15)
-#define MX6SL_ARM2_EPDC_SDDO_9		IMX_GPIO_NR(1, 16)
-#define MX6SL_ARM2_EPDC_SDDO_10		IMX_GPIO_NR(1, 17)
-#define MX6SL_ARM2_EPDC_SDDO_11		IMX_GPIO_NR(1, 18)
-#define MX6SL_ARM2_EPDC_SDDO_12		IMX_GPIO_NR(1, 19)
-#define MX6SL_ARM2_EPDC_SDDO_13		IMX_GPIO_NR(1, 20)
-#define MX6SL_ARM2_EPDC_SDDO_14		IMX_GPIO_NR(1, 21)
-#define MX6SL_ARM2_EPDC_SDDO_15		IMX_GPIO_NR(1, 22)
-#define MX6SL_ARM2_EPDC_GDCLK		IMX_GPIO_NR(1, 31)
-#define MX6SL_ARM2_EPDC_GDSP		IMX_GPIO_NR(2, 2)
-#define MX6SL_ARM2_EPDC_GDOE		IMX_GPIO_NR(2, 0)
-#define MX6SL_ARM2_EPDC_GDRL		IMX_GPIO_NR(2, 1)
-#define MX6SL_ARM2_EPDC_SDCLK		IMX_GPIO_NR(1, 23)
-#define MX6SL_ARM2_EPDC_SDOE		IMX_GPIO_NR(1, 25)
-#define MX6SL_ARM2_EPDC_SDLE		IMX_GPIO_NR(1, 24)
-#define MX6SL_ARM2_EPDC_SDSHR		IMX_GPIO_NR(1, 26)
-#define MX6SL_ARM2_EPDC_PWRCOM		IMX_GPIO_NR(2, 11)
-#define MX6SL_ARM2_EPDC_PWRSTAT		IMX_GPIO_NR(2, 13)
-#define MX6SL_ARM2_EPDC_PWRCTRL0	IMX_GPIO_NR(2, 7)
-#define MX6SL_ARM2_EPDC_PWRCTRL1	IMX_GPIO_NR(2, 8)
-#define MX6SL_ARM2_EPDC_PWRCTRL2	IMX_GPIO_NR(2, 9)
-#define MX6SL_ARM2_EPDC_PWRCTRL3	IMX_GPIO_NR(2, 10)
-#define MX6SL_ARM2_EPDC_BDR0		IMX_GPIO_NR(2, 5)
-#define MX6SL_ARM2_EPDC_BDR1		IMX_GPIO_NR(2, 6)
-#define MX6SL_ARM2_EPDC_SDCE0		IMX_GPIO_NR(1, 27)
-#define MX6SL_ARM2_EPDC_SDCE1		IMX_GPIO_NR(1, 28)
-#define MX6SL_ARM2_EPDC_SDCE2		IMX_GPIO_NR(1, 29)
-#define MX6SL_ARM2_EPDC_SDCE3		IMX_GPIO_NR(1, 30)
-#define MX6SL_ARM2_EPDC_PMIC_WAKE	IMX_GPIO_NR(2, 14) /* EPDC_PWRWAKEUP */
-#define MX6SL_ARM2_EPDC_PMIC_INT	IMX_GPIO_NR(2, 12) /* EPDC_PWRINT */
-#define MX6SL_ARM2_EPDC_VCOM		IMX_GPIO_NR(2, 3)
-#define MX6SL_ARM2_ELAN_CE		IMX_GPIO_NR(2, 9)
-#define MX6SL_ARM2_ELAN_INT		IMX_GPIO_NR(2, 10)
-#define MX6SL_ARM2_ELAN_RST		IMX_GPIO_NR(4, 4)
+#include "board-mx6sl_common.h"
 
 static int spdc_sel;
 static int max17135_regulator_init(struct max17135 *max17135);
-struct clk *extern_audio_root;
+static struct clk *extern_audio_root;
 
 extern char *gp_reg_id;
 extern char *soc_reg_id;
@@ -215,8 +158,8 @@ static int plt_sd_pad_change(unsigned int index, int clock)
 }
 
 static const struct esdhc_platform_data mx6_arm2_sd1_data __initconst = {
-	.cd_gpio		= MX6_ARM2_SD1_CD,
-	.wp_gpio		= MX6_ARM2_SD1_WP,
+	.cd_gpio		= MX6_BRD_SD1_CD,
+	.wp_gpio		= MX6_BRD_SD1_WP,
 	.support_8bit		= 1,
 	.support_18v		= 1,
 	.keep_power_at_suspend	= 1,
@@ -225,8 +168,8 @@ static const struct esdhc_platform_data mx6_arm2_sd1_data __initconst = {
 };
 
 static const struct esdhc_platform_data mx6_arm2_sd2_data __initconst = {
-	.cd_gpio		= MX6_ARM2_SD2_CD,
-	.wp_gpio		= MX6_ARM2_SD2_WP,
+	.cd_gpio		= MX6_BRD_SD2_CD,
+	.wp_gpio		= MX6_BRD_SD2_WP,
 	.keep_power_at_suspend	= 1,
 	.delay_line		= 0,
 	.support_18v		= 1,
@@ -234,7 +177,7 @@ static const struct esdhc_platform_data mx6_arm2_sd2_data __initconst = {
 };
 
 static const struct esdhc_platform_data mx6_arm2_sd3_data __initconst = {
-	.cd_gpio		= MX6_ARM2_SD3_CD,
+	.cd_gpio		= MX6_BRD_SD3_CD,
 	.wp_gpio		= -1,
 	.keep_power_at_suspend	= 1,
 	.delay_line		= 0,
@@ -377,11 +320,11 @@ static struct max17135_platform_data max17135_pdata __initdata = {
 	.vpos_pwrdn = 2,
 	.gvee_pwrdn = 1,
 	.vneg_pwrdn = 1,
-	.gpio_pmic_pwrgood = MX6SL_ARM2_EPDC_PWRSTAT,
-	.gpio_pmic_vcom_ctrl = MX6SL_ARM2_EPDC_VCOM,
-	.gpio_pmic_wakeup = MX6SL_ARM2_EPDC_PMIC_WAKE,
-	.gpio_pmic_v3p3 = MX6SL_ARM2_EPDC_PWRCTRL0,
-	.gpio_pmic_intr = MX6SL_ARM2_EPDC_PMIC_INT,
+	.gpio_pmic_pwrgood = MX6SL_BRD_EPDC_PWRSTAT,
+	.gpio_pmic_vcom_ctrl = MX6SL_BRD_EPDC_VCOM,
+	.gpio_pmic_wakeup = MX6SL_BRD_EPDC_PMIC_WAKE,
+	.gpio_pmic_v3p3 = MX6SL_BRD_EPDC_PWRCTRL0,
+	.gpio_pmic_intr = MX6SL_BRD_EPDC_PMIC_INT,
 	.regulator_init = max17135_init_data,
 	.init = max17135_regulator_init,
 };
@@ -448,7 +391,7 @@ static int __init max17135_regulator_init(struct max17135 *max17135)
 }
 
 static int mx6_arm2_spi_cs[] = {
-	MX6_ARM2_ECSPI1_CS0,
+	MX6_BRD_ECSPI1_CS0,
 };
 
 static const struct spi_imx_master mx6_arm2_spi_data __initconst = {
@@ -551,7 +494,7 @@ static struct mxc_audio_platform_data wm8962_data = {
 	.ssi_num = 1,
 	.src_port = 2,
 	.ext_port = 3,
-	.hp_gpio = MX6_ARM2_HEADPHONE_DET,
+	.hp_gpio = MX6_BRD_HEADPHONE_DET,
 	.hp_active_low = 1,
 	.mic_gpio = -1,
 	.mic_active_low = 1,
@@ -618,7 +561,9 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 		.platform_data = &max17135_pdata,
 	}, {
 		I2C_BOARD_INFO("elan-touch", 0x10),
-		.irq = gpio_to_irq(MX6SL_ARM2_ELAN_INT),
+		.irq = gpio_to_irq(MX6SL_BRD_ELAN_INT),
+	}, {
+		I2C_BOARD_INFO("mma8450", 0x1c),
 	},
 };
 
@@ -635,13 +580,14 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 };
 
 static struct mxc_dvfs_platform_data mx6sl_arm2_dvfscore_data = {
-	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.reg_id			= "VDDCORE",
-	#else
+	.soc_id			= "VDDSOC",
+#else
 	.reg_id			= "cpu_vddgp",
 	.soc_id			= "cpu_vddsoc",
 	.pu_id			= "cpu_vddvpu",
-	#endif
+#endif
 	.clk1_id		= "cpu_clk",
 	.clk2_id		= "gpc_dvfs_clk",
 	.gpc_cntr_offset	= MXC_GPC_CNTR_OFFSET,
@@ -679,11 +625,11 @@ static int mx6sl_arm2_fec_phy_init(struct phy_device *phydev)
 	int val;
 
 	/* power on FEC phy and reset phy */
-	gpio_request(MX6_ARM2_FEC_PWR_EN, "fec-pwr");
-	gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 0);
+	gpio_request(MX6_BRD_FEC_PWR_EN, "fec-pwr");
+	gpio_direction_output(MX6_BRD_FEC_PWR_EN, 0);
 	/* wait RC ms for hw reset */
 	msleep(1);
-	gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 1);
+	gpio_direction_output(MX6_BRD_FEC_PWR_EN, 1);
 
 	/* check phy power */
 	val = phy_read(phydev, 0x0);
@@ -704,109 +650,109 @@ static int epdc_get_pins(void)
 	int ret = 0;
 
 	/* Claim GPIOs for EPDC pins - used during power up/down */
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_0, "epdc_d0");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_1, "epdc_d1");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_2, "epdc_d2");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_3, "epdc_d3");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_4, "epdc_d4");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_5, "epdc_d5");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_6, "epdc_d6");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_7, "epdc_d7");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDCLK, "epdc_gdclk");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDSP, "epdc_gdsp");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDOE, "epdc_gdoe");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDRL, "epdc_gdrl");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCLK, "epdc_sdclk");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDOE, "epdc_sdoe");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDLE, "epdc_sdle");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDSHR, "epdc_sdshr");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_BDR0, "epdc_bdr0");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE0, "epdc_sdce0");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE1, "epdc_sdce1");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE2, "epdc_sdce2");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_0, "epdc_d0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_1, "epdc_d1");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_2, "epdc_d2");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_3, "epdc_d3");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_4, "epdc_d4");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_5, "epdc_d5");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_6, "epdc_d6");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_7, "epdc_d7");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDCLK, "epdc_gdclk");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDSP, "epdc_gdsp");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDOE, "epdc_gdoe");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDRL, "epdc_gdrl");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCLK, "epdc_sdclk");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDOE, "epdc_sdoe");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDLE, "epdc_sdle");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDSHR, "epdc_sdshr");
+	ret |= gpio_request(MX6SL_BRD_EPDC_BDR0, "epdc_bdr0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE0, "epdc_sdce0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE1, "epdc_sdce1");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE2, "epdc_sdce2");
 
 	return ret;
 }
 
 static void epdc_put_pins(void)
 {
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_0);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_1);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_2);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_3);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_4);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_5);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_6);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_7);
-	gpio_free(MX6SL_ARM2_EPDC_GDCLK);
-	gpio_free(MX6SL_ARM2_EPDC_GDSP);
-	gpio_free(MX6SL_ARM2_EPDC_GDOE);
-	gpio_free(MX6SL_ARM2_EPDC_GDRL);
-	gpio_free(MX6SL_ARM2_EPDC_SDCLK);
-	gpio_free(MX6SL_ARM2_EPDC_SDOE);
-	gpio_free(MX6SL_ARM2_EPDC_SDLE);
-	gpio_free(MX6SL_ARM2_EPDC_SDSHR);
-	gpio_free(MX6SL_ARM2_EPDC_BDR0);
-	gpio_free(MX6SL_ARM2_EPDC_SDCE0);
-	gpio_free(MX6SL_ARM2_EPDC_SDCE1);
-	gpio_free(MX6SL_ARM2_EPDC_SDCE2);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_7);
+	gpio_free(MX6SL_BRD_EPDC_GDCLK);
+	gpio_free(MX6SL_BRD_EPDC_GDSP);
+	gpio_free(MX6SL_BRD_EPDC_GDOE);
+	gpio_free(MX6SL_BRD_EPDC_GDRL);
+	gpio_free(MX6SL_BRD_EPDC_SDCLK);
+	gpio_free(MX6SL_BRD_EPDC_SDOE);
+	gpio_free(MX6SL_BRD_EPDC_SDLE);
+	gpio_free(MX6SL_BRD_EPDC_SDSHR);
+	gpio_free(MX6SL_BRD_EPDC_BDR0);
+	gpio_free(MX6SL_BRD_EPDC_SDCE0);
+	gpio_free(MX6SL_BRD_EPDC_SDCE1);
+	gpio_free(MX6SL_BRD_EPDC_SDCE2);
 }
 
 static void epdc_enable_pins(void)
 {
 	/* Configure MUX settings to enable EPDC use */
-	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_epdc_enable_pads, \
-				ARRAY_SIZE(mx6sl_arm2_epdc_enable_pads));
-
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_0);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_1);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_2);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_3);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_4);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_5);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_6);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_7);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDCLK);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDSP);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDOE);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDRL);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCLK);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDOE);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDLE);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDSHR);
-	gpio_direction_input(MX6SL_ARM2_EPDC_BDR0);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCE0);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCE1);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCE2);
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_epdc_enable_pads, \
+				ARRAY_SIZE(mx6sl_brd_epdc_enable_pads));
+
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_7);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDSP);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDOE);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDRL);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDOE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDLE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDSHR);
+	gpio_direction_input(MX6SL_BRD_EPDC_BDR0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE2);
 }
 
 static void epdc_disable_pins(void)
 {
 	/* Configure MUX settings for EPDC pins to
 	 * GPIO and drive to 0. */
-	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_epdc_disable_pads, \
-				ARRAY_SIZE(mx6sl_arm2_epdc_disable_pads));
-
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_0, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_1, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_2, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_3, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_4, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_5, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_6, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_7, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDCLK, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDSP, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDOE, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDRL, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCLK, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDOE, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDLE, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDSHR, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_BDR0, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCE0, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCE1, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCE2, 0);
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_epdc_disable_pads, \
+				ARRAY_SIZE(mx6sl_brd_epdc_disable_pads));
+
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_2, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_3, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_4, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_5, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_6, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_7, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDSP, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDOE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDRL, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDOE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDLE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDSHR, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_BDR0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE2, 0);
 }
 
 static struct fb_videomode e60_v110_mode = {
@@ -946,108 +892,108 @@ static int spdc_get_pins(void)
 	int ret = 0;
 
 	/* Claim GPIOs for SPDC pins - used during power up/down */
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_0, "SPDC_D0");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_1, "SPDC_D1");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_2, "SPDC_D2");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_3, "SPDC_D3");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_4, "SPDC_D4");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_5, "SPDC_D5");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_6, "SPDC_D6");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_7, "SPDC_D7");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_0, "SPDC_D0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_1, "SPDC_D1");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_2, "SPDC_D2");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_3, "SPDC_D3");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_4, "SPDC_D4");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_5, "SPDC_D5");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_6, "SPDC_D6");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_7, "SPDC_D7");
 
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDOE, "SIPIX_YOE");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_9, "SIPIX_PWR_RDY");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDOE, "SIPIX_YOE");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_9, "SIPIX_PWR_RDY");
 
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDSP, "SIPIX_YDIO");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDSP, "SIPIX_YDIO");
 
-	ret |= gpio_request(MX6SL_ARM2_EPDC_GDCLK, "SIPIX_YCLK");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDSHR, "SIPIX_XDIO");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDCLK, "SIPIX_YCLK");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDSHR, "SIPIX_XDIO");
 
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDLE, "SIPIX_LD");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE1, "SIPIX_SOE");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDLE, "SIPIX_LD");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE1, "SIPIX_SOE");
 
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCLK, "SIPIX_XCLK");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_10, "SIPIX_SHD_N");
-	ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE0, "SIPIX2_CE");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCLK, "SIPIX_XCLK");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_10, "SIPIX_SHD_N");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE0, "SIPIX2_CE");
 
 	return ret;
 }
 
 static void spdc_put_pins(void)
 {
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_0);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_1);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_2);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_3);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_4);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_5);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_6);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_7);
-
-	gpio_free(MX6SL_ARM2_EPDC_GDOE);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_9);
-	gpio_free(MX6SL_ARM2_EPDC_GDSP);
-	gpio_free(MX6SL_ARM2_EPDC_GDCLK);
-	gpio_free(MX6SL_ARM2_EPDC_SDSHR);
-	gpio_free(MX6SL_ARM2_EPDC_SDLE);
-	gpio_free(MX6SL_ARM2_EPDC_SDCE1);
-	gpio_free(MX6SL_ARM2_EPDC_SDCLK);
-	gpio_free(MX6SL_ARM2_EPDC_SDDO_10);
-	gpio_free(MX6SL_ARM2_EPDC_SDCE0);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_7);
+
+	gpio_free(MX6SL_BRD_EPDC_GDOE);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_9);
+	gpio_free(MX6SL_BRD_EPDC_GDSP);
+	gpio_free(MX6SL_BRD_EPDC_GDCLK);
+	gpio_free(MX6SL_BRD_EPDC_SDSHR);
+	gpio_free(MX6SL_BRD_EPDC_SDLE);
+	gpio_free(MX6SL_BRD_EPDC_SDCE1);
+	gpio_free(MX6SL_BRD_EPDC_SDCLK);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_10);
+	gpio_free(MX6SL_BRD_EPDC_SDCE0);
 }
 
 static void spdc_enable_pins(void)
 {
 	/* Configure MUX settings to enable SPDC use */
-	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_spdc_enable_pads, \
-				ARRAY_SIZE(mx6sl_arm2_spdc_enable_pads));
-
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_0);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_1);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_2);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_3);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_4);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_5);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_6);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_7);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDOE);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_9);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDSP);
-	gpio_direction_input(MX6SL_ARM2_EPDC_GDCLK);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDSHR);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDLE);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCE1);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCLK);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_10);
-	gpio_direction_input(MX6SL_ARM2_EPDC_SDCE0);
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_spdc_enable_pads, \
+				ARRAY_SIZE(mx6sl_brd_spdc_enable_pads));
+
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_7);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDOE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_9);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDSP);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDSHR);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDLE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_10);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE0);
 }
 
 static void spdc_disable_pins(void)
 {
 	/* Configure MUX settings for SPDC pins to
 	 * GPIO and drive to 0. */
-	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_spdc_disable_pads, \
-				ARRAY_SIZE(mx6sl_arm2_spdc_disable_pads));
-
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_0, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_1, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_2, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_3, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_4, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_5, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_6, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_7, 0);
-
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDOE, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_9, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDSP, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_GDCLK, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDSHR, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDLE, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCE1, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCLK, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_10, 0);
-	gpio_direction_output(MX6SL_ARM2_EPDC_SDCE0, 0);
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_spdc_disable_pads, \
+				ARRAY_SIZE(mx6sl_brd_spdc_disable_pads));
+
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_2, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_3, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_4, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_5, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_6, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_7, 0);
+
+	gpio_direction_output(MX6SL_BRD_EPDC_GDOE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_9, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDSP, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDSHR, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDLE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_10, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE0, 0);
 }
 
 static struct imx_spdc_panel_init_set spdc_init_set = {
@@ -1105,9 +1051,9 @@ static void setup_spdc(void)
 static void imx6_arm2_usbotg_vbus(bool on)
 {
 	if (on)
-		gpio_set_value(MX6_ARM2_USBOTG1_PWR, 1);
+		gpio_set_value(MX6_BRD_USBOTG1_PWR, 1);
 	else
-		gpio_set_value(MX6_ARM2_USBOTG1_PWR, 0);
+		gpio_set_value(MX6_BRD_USBOTG1_PWR, 0);
 }
 
 static void __init mx6_arm2_init_usb(void)
@@ -1120,23 +1066,28 @@ static void __init mx6_arm2_init_usb(void)
 	 * or it will affect signal quality at dp.
 	 */
 
-	ret = gpio_request(MX6_ARM2_USBOTG1_PWR, "usbotg-pwr");
+	ret = gpio_request(MX6_BRD_USBOTG1_PWR, "usbotg-pwr");
 	if (ret) {
-		pr_err("failed to get GPIO MX6_ARM2_USBOTG1_PWR:%d\n", ret);
+		pr_err("failed to get GPIO MX6_BRD_USBOTG1_PWR:%d\n", ret);
 		return;
 	}
-	gpio_direction_output(MX6_ARM2_USBOTG1_PWR, 0);
+	gpio_direction_output(MX6_BRD_USBOTG1_PWR, 0);
 
-	ret = gpio_request(MX6_ARM2_USBOTG2_PWR, "usbh1-pwr");
+	ret = gpio_request(MX6_BRD_USBOTG2_PWR, "usbh1-pwr");
 	if (ret) {
-		pr_err("failed to get GPIO MX6_ARM2_USBOTG2_PWR:%d\n", ret);
+		pr_err("failed to get GPIO MX6_BRD_USBOTG2_PWR:%d\n", ret);
 		return;
 	}
-	gpio_direction_output(MX6_ARM2_USBOTG2_PWR, 1);
+	gpio_direction_output(MX6_BRD_USBOTG2_PWR, 1);
 
 	mx6_set_otghost_vbus_func(imx6_arm2_usbotg_vbus);
 	mx6_usb_dr_init();
 #ifdef CONFIG_USB_EHCI_ARC_HSIC
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_HSIC_DAT,
+		PAD_CTL_DDR_SEL_DDR3, PAD_CTL_DDR_SEL_MASK);
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_HSIC_STROBE,
+		PAD_CTL_DDR_SEL_DDR3, PAD_CTL_DDR_SEL_MASK);
+
 	mx6_usb_h2_init();
 #endif
 }
@@ -1197,23 +1148,23 @@ static const struct matrix_keymap_data mx6sl_arm2_map_data __initconst = {
 };
 static void __init elan_ts_init(void)
 {
-	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_elan_pads,
-					ARRAY_SIZE(mx6sl_arm2_elan_pads));
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_elan_pads,
+					ARRAY_SIZE(mx6sl_brd_elan_pads));
 
 	/* ELAN Touchscreen */
-	gpio_request(MX6SL_ARM2_ELAN_INT, "elan-interrupt");
-	gpio_direction_input(MX6SL_ARM2_ELAN_INT);
+	gpio_request(MX6SL_BRD_ELAN_INT, "elan-interrupt");
+	gpio_direction_input(MX6SL_BRD_ELAN_INT);
 
-	gpio_request(MX6SL_ARM2_ELAN_CE, "elan-cs");
-	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 1);
-	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 0);
+	gpio_request(MX6SL_BRD_ELAN_CE, "elan-cs");
+	gpio_direction_output(MX6SL_BRD_ELAN_CE, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_CE, 0);
 
-	gpio_request(MX6SL_ARM2_ELAN_RST, "elan-rst");
-	gpio_direction_output(MX6SL_ARM2_ELAN_RST, 1);
-	gpio_direction_output(MX6SL_ARM2_ELAN_RST, 0);
+	gpio_request(MX6SL_BRD_ELAN_RST, "elan-rst");
+	gpio_direction_output(MX6SL_BRD_ELAN_RST, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_RST, 0);
 	mdelay(1);
-	gpio_direction_output(MX6SL_ARM2_ELAN_RST, 1);
-	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_RST, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_CE, 1);
 }
 
 #define SNVS_LPCR 0x38
@@ -1232,18 +1183,20 @@ static void mx6_snvs_poweroff(void)
  */
 static void __init mx6_arm2_init(void)
 {
-	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_pads, ARRAY_SIZE(mx6sl_arm2_pads));
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_pads,
+					ARRAY_SIZE(mx6sl_brd_pads));
 
 	elan_ts_init();
 
-	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
-	#else
+	soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
+#else
 	gp_reg_id = mx6sl_arm2_dvfscore_data.reg_id;
 	soc_reg_id = mx6sl_arm2_dvfscore_data.soc_id;
 	pu_reg_id = mx6sl_arm2_dvfscore_data.pu_id;
 	mx6_cpu_regulator_init();
-	#endif
+#endif
 
 	imx6q_add_imx_snvs_rtc();
 
@@ -1285,8 +1238,8 @@ static void __init mx6_arm2_init(void)
 	imx6q_add_mxc_pwm_backlight(0, &mx6_arm2_pwm_backlight_data);
 	imx6dl_add_imx_elcdif(&fb_data[0]);
 
-	gpio_request(MX6_ARM2_LCD_PWR_EN, "elcdif-power-on");
-	gpio_direction_output(MX6_ARM2_LCD_PWR_EN, 1);
+	gpio_request(MX6_BRD_LCD_PWR_EN, "elcdif-power-on");
+	gpio_direction_output(MX6_BRD_LCD_PWR_EN, 1);
 	mxc_register_device(&lcd_wvga_device, NULL);
 
 	imx6dl_add_imx_pxp();
@@ -1309,6 +1262,11 @@ static void __init mx6_arm2_init(void)
 	imx6q_add_busfreq();
 	imx6sl_add_dcp();
 	imx6sl_add_rngb();
+	imx6sl_add_imx_pxp_v4l2();
+
+	imx6q_add_perfmon(0);
+	imx6q_add_perfmon(1);
+	imx6q_add_perfmon(2);
 
 	pm_power_off = mx6_snvs_poweroff;
 }
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_common.h
index 09a211690029..d005e02cb6ac 100755..100644
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.h
+++ b/arch/arm/mach-mx6/board-mx6sl_common.h
@@ -16,11 +16,68 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 
-#ifndef _BOARD_MX6SL_ARM2_H
-#define _BOARD_MX6SL_ARM2_H
+#ifndef _BOARD_MX6SL_COMMON_H
+#define _BOARD_MX6SL_COMMON_H
 #include <mach/iomux-mx6sl.h>
 
-static iomux_v3_cfg_t mx6sl_arm2_pads[] = {
+#define MX6_BRD_USBOTG1_PWR	IMX_GPIO_NR(4, 0)       /* KEY_COL4 */
+#define MX6_BRD_USBOTG2_PWR	IMX_GPIO_NR(4, 2)       /* KEY_COL5 */
+#define MX6_BRD_LCD_PWR_EN	IMX_GPIO_NR(4, 3)	/* KEY_ROW5 */
+#define MX6_BRD_SD1_WP		IMX_GPIO_NR(4, 6)	/* KEY_COL7 */
+#define MX6_BRD_SD1_CD		IMX_GPIO_NR(4, 7)	/* KEY_ROW7 */
+#define MX6_BRD_ECSPI1_CS0	IMX_GPIO_NR(4, 11)	/* ECSPI1_SS0 */
+#define MX6_BRD_HEADPHONE_DET	IMX_GPIO_NR(4, 19)	/* FEC_RX_ER */
+#define MX6_BRD_SD2_WP		IMX_GPIO_NR(4, 29)	/* SD2_DAT6 */
+#define MX6_BRD_SD2_CD		IMX_GPIO_NR(5, 0)	/* SD2_DAT7 */
+#define MX6_BRD_SD3_CD		IMX_GPIO_NR(3, 22)	/* REF_CLK_32K */
+#define MX6_BRD_FEC_PWR_EN	IMX_GPIO_NR(4, 21)	/* FEC_TX_CLK */
+
+/* EPDC GPIO pins */
+#define MX6SL_BRD_EPDC_SDDO_0		IMX_GPIO_NR(1, 7)
+#define MX6SL_BRD_EPDC_SDDO_1		IMX_GPIO_NR(1, 8)
+#define MX6SL_BRD_EPDC_SDDO_2		IMX_GPIO_NR(1, 9)
+#define MX6SL_BRD_EPDC_SDDO_3		IMX_GPIO_NR(1, 10)
+#define MX6SL_BRD_EPDC_SDDO_4		IMX_GPIO_NR(1, 11)
+#define MX6SL_BRD_EPDC_SDDO_5		IMX_GPIO_NR(1, 12)
+#define MX6SL_BRD_EPDC_SDDO_6		IMX_GPIO_NR(1, 13)
+#define MX6SL_BRD_EPDC_SDDO_7		IMX_GPIO_NR(1, 14)
+#define MX6SL_BRD_EPDC_SDDO_8		IMX_GPIO_NR(1, 15)
+#define MX6SL_BRD_EPDC_SDDO_9		IMX_GPIO_NR(1, 16)
+#define MX6SL_BRD_EPDC_SDDO_10		IMX_GPIO_NR(1, 17)
+#define MX6SL_BRD_EPDC_SDDO_11		IMX_GPIO_NR(1, 18)
+#define MX6SL_BRD_EPDC_SDDO_12		IMX_GPIO_NR(1, 19)
+#define MX6SL_BRD_EPDC_SDDO_13		IMX_GPIO_NR(1, 20)
+#define MX6SL_BRD_EPDC_SDDO_14		IMX_GPIO_NR(1, 21)
+#define MX6SL_BRD_EPDC_SDDO_15		IMX_GPIO_NR(1, 22)
+#define MX6SL_BRD_EPDC_GDCLK		IMX_GPIO_NR(1, 31)
+#define MX6SL_BRD_EPDC_GDSP		IMX_GPIO_NR(2, 2)
+#define MX6SL_BRD_EPDC_GDOE		IMX_GPIO_NR(2, 0)
+#define MX6SL_BRD_EPDC_GDRL		IMX_GPIO_NR(2, 1)
+#define MX6SL_BRD_EPDC_SDCLK		IMX_GPIO_NR(1, 23)
+#define MX6SL_BRD_EPDC_SDOE		IMX_GPIO_NR(1, 25)
+#define MX6SL_BRD_EPDC_SDLE		IMX_GPIO_NR(1, 24)
+#define MX6SL_BRD_EPDC_SDSHR		IMX_GPIO_NR(1, 26)
+#define MX6SL_BRD_EPDC_PWRCOM		IMX_GPIO_NR(2, 11)
+#define MX6SL_BRD_EPDC_PWRSTAT		IMX_GPIO_NR(2, 13)
+#define MX6SL_BRD_EPDC_PWRCTRL0		IMX_GPIO_NR(2, 7)
+#define MX6SL_BRD_EPDC_PWRCTRL1		IMX_GPIO_NR(2, 8)
+#define MX6SL_BRD_EPDC_PWRCTRL2		IMX_GPIO_NR(2, 9)
+#define MX6SL_BRD_EPDC_PWRCTRL3		IMX_GPIO_NR(2, 10)
+#define MX6SL_BRD_EPDC_BDR0		IMX_GPIO_NR(2, 5)
+#define MX6SL_BRD_EPDC_BDR1		IMX_GPIO_NR(2, 6)
+#define MX6SL_BRD_EPDC_SDCE0		IMX_GPIO_NR(1, 27)
+#define MX6SL_BRD_EPDC_SDCE1		IMX_GPIO_NR(1, 28)
+#define MX6SL_BRD_EPDC_SDCE2		IMX_GPIO_NR(1, 29)
+#define MX6SL_BRD_EPDC_SDCE3		IMX_GPIO_NR(1, 30)
+#define MX6SL_BRD_EPDC_PMIC_WAKE	IMX_GPIO_NR(2, 14) /* EPDC_PWRWAKEUP */
+#define MX6SL_BRD_EPDC_PMIC_INT		IMX_GPIO_NR(2, 12) /* EPDC_PWRINT */
+#define MX6SL_BRD_EPDC_VCOM		IMX_GPIO_NR(2, 3)
+/* ELAN TS */
+#define MX6SL_BRD_ELAN_CE		IMX_GPIO_NR(2, 9)
+#define MX6SL_BRD_ELAN_INT		IMX_GPIO_NR(2, 10)
+#define MX6SL_BRD_ELAN_RST		IMX_GPIO_NR(4, 4)
+
+static iomux_v3_cfg_t mx6sl_brd_pads[] = {
 
 	/* AUDMUX */
 	MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC,
@@ -158,7 +215,7 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = {
 	MX6SL_PAD_WDOG_B__WDOG1_WDOG_B,
 };
 
-static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = {
+static iomux_v3_cfg_t mx6sl_brd_epdc_enable_pads[] = {
 	/* EPDC */
 	MX6SL_PAD_EPDC_D0__EPDC_SDDO_0,
 	MX6SL_PAD_EPDC_D1__EPDC_SDDO_1,
@@ -197,7 +254,7 @@ static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = {
 	MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
 };
 
-static iomux_v3_cfg_t mx6sl_arm2_epdc_disable_pads[] = {
+static iomux_v3_cfg_t mx6sl_brd_epdc_disable_pads[] = {
 	/* EPDC */
 	MX6SL_PAD_EPDC_D0__GPIO_1_7,
 	MX6SL_PAD_EPDC_D1__GPIO_1_8,
@@ -236,7 +293,7 @@ static iomux_v3_cfg_t mx6sl_arm2_epdc_disable_pads[] = {
 	MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
 };
 
-static iomux_v3_cfg_t mx6sl_arm2_spdc_enable_pads[] = {
+static iomux_v3_cfg_t mx6sl_brd_spdc_enable_pads[] = {
 	/* SPDC data*/
 	MX6SL_PAD_EPDC_D0__TCON_E_DATA_0,
 	MX6SL_PAD_EPDC_D1__TCON_E_DATA_1,
@@ -280,7 +337,7 @@ static iomux_v3_cfg_t mx6sl_arm2_spdc_enable_pads[] = {
 	MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
 };
 
-static iomux_v3_cfg_t mx6sl_arm2_spdc_disable_pads[] = {
+static iomux_v3_cfg_t mx6sl_brd_spdc_disable_pads[] = {
 	MX6SL_PAD_EPDC_D0__GPIO_1_7,
 	MX6SL_PAD_EPDC_D1__GPIO_1_8,
 	MX6SL_PAD_EPDC_D2__GPIO_1_9,
@@ -315,7 +372,7 @@ static iomux_v3_cfg_t mx6sl_arm2_spdc_disable_pads[] = {
 	MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
 };
 
-static iomux_v3_cfg_t mx6sl_arm2_elan_pads[] = {
+static iomux_v3_cfg_t mx6sl_brd_elan_pads[] = {
 	MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10,	/* INT */
 	MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9,	/* CE */
 	MX6SL_PAD_KEY_COL6__GPIO_4_4,		/* RST */
diff --git a/arch/arm/mach-mx6/board-mx6sl_evk.c b/arch/arm/mach-mx6/board-mx6sl_evk.c
new file mode 100644
index 000000000000..81654a0c99fd
--- /dev/null
+++ b/arch/arm/mach-mx6/board-mx6sl_evk.c
@@ -0,0 +1,1320 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/nodemask.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/smsc911x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/ata.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include <linux/mxcfb.h>
+#include <linux/pwm_backlight.h>
+#include <linux/fec.h>
+#include <linux/memblock.h>
+#include <linux/gpio.h>
+#include <linux/etherdevice.h>
+#include <linux/regulator/anatop-regulator.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max17135.h>
+#include <sound/wm8962.h>
+#include <sound/pcm.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/memory.h>
+#include <mach/iomux-mx6sl.h>
+#include <mach/imx-uart.h>
+#include <mach/viv_gpu.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "usb.h"
+#include "devices-imx6q.h"
+#include "crm_regs.h"
+#include "cpu_op-mx6.h"
+#include "board-mx6sl_common.h"
+
+
+static int spdc_sel;
+static int max17135_regulator_init(struct max17135 *max17135);
+struct clk *extern_audio_root;
+
+extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
+extern int __init mx6sl_evk_init_pfuze100(u32 int_gpio);
+
+enum sd_pad_mode {
+	SD_PAD_MODE_LOW_SPEED,
+	SD_PAD_MODE_MED_SPEED,
+	SD_PAD_MODE_HIGH_SPEED,
+};
+
+static int plt_sd_pad_change(unsigned int index, int clock)
+{
+	/* LOW speed is the default state of SD pads */
+	static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
+
+	iomux_v3_cfg_t *sd_pads_200mhz = NULL;
+	iomux_v3_cfg_t *sd_pads_100mhz = NULL;
+	iomux_v3_cfg_t *sd_pads_50mhz = NULL;
+
+	u32 sd_pads_200mhz_cnt;
+	u32 sd_pads_100mhz_cnt;
+	u32 sd_pads_50mhz_cnt;
+
+	switch (index) {
+	case 0:
+		sd_pads_200mhz = mx6sl_sd1_200mhz;
+		sd_pads_100mhz = mx6sl_sd1_100mhz;
+		sd_pads_50mhz = mx6sl_sd1_50mhz;
+
+		sd_pads_200mhz_cnt = ARRAY_SIZE(mx6sl_sd1_200mhz);
+		sd_pads_100mhz_cnt = ARRAY_SIZE(mx6sl_sd1_100mhz);
+		sd_pads_50mhz_cnt = ARRAY_SIZE(mx6sl_sd1_50mhz);
+		break;
+	case 1:
+		sd_pads_200mhz = mx6sl_sd2_200mhz;
+		sd_pads_100mhz = mx6sl_sd2_100mhz;
+		sd_pads_50mhz = mx6sl_sd2_50mhz;
+
+		sd_pads_200mhz_cnt = ARRAY_SIZE(mx6sl_sd2_200mhz);
+		sd_pads_100mhz_cnt = ARRAY_SIZE(mx6sl_sd2_100mhz);
+		sd_pads_50mhz_cnt = ARRAY_SIZE(mx6sl_sd2_50mhz);
+		break;
+	case 2:
+		sd_pads_200mhz = mx6sl_sd3_200mhz;
+		sd_pads_100mhz = mx6sl_sd3_100mhz;
+		sd_pads_50mhz = mx6sl_sd3_50mhz;
+
+		sd_pads_200mhz_cnt = ARRAY_SIZE(mx6sl_sd3_200mhz);
+		sd_pads_100mhz_cnt = ARRAY_SIZE(mx6sl_sd3_100mhz);
+		sd_pads_50mhz_cnt = ARRAY_SIZE(mx6sl_sd3_50mhz);
+		break;
+	default:
+		printk(KERN_ERR "no such SD host controller index %d\n", index);
+		return -EINVAL;
+	}
+
+	if (clock > 100000000) {
+		if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
+			return 0;
+		BUG_ON(!sd_pads_200mhz);
+		pad_mode = SD_PAD_MODE_HIGH_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(sd_pads_200mhz,
+							sd_pads_200mhz_cnt);
+	} else if (clock > 52000000) {
+		if (pad_mode == SD_PAD_MODE_MED_SPEED)
+			return 0;
+		BUG_ON(!sd_pads_100mhz);
+		pad_mode = SD_PAD_MODE_MED_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(sd_pads_100mhz,
+							sd_pads_100mhz_cnt);
+	} else {
+		if (pad_mode == SD_PAD_MODE_LOW_SPEED)
+			return 0;
+		BUG_ON(!sd_pads_50mhz);
+		pad_mode = SD_PAD_MODE_LOW_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz,
+							sd_pads_50mhz_cnt);
+	}
+}
+
+static const struct esdhc_platform_data mx6_evk_sd1_data __initconst = {
+	.cd_gpio		= MX6_BRD_SD1_CD,
+	.wp_gpio		= MX6_BRD_SD1_WP,
+	.support_8bit		= 1,
+	.support_18v		= 1,
+	.keep_power_at_suspend	= 1,
+	.delay_line		= 0,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
+static const struct esdhc_platform_data mx6_evk_sd2_data __initconst = {
+	.cd_gpio		= MX6_BRD_SD2_CD,
+	.wp_gpio		= MX6_BRD_SD2_WP,
+	.keep_power_at_suspend	= 1,
+	.delay_line		= 0,
+	.support_18v		= 1,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
+static const struct esdhc_platform_data mx6_evk_sd3_data __initconst = {
+	.cd_gpio		= MX6_BRD_SD3_CD,
+	.wp_gpio		= -1,
+	.keep_power_at_suspend	= 1,
+	.delay_line		= 0,
+	.support_18v		= 1,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
+#define mV_to_uV(mV) (mV * 1000)
+#define uV_to_mV(uV) (uV / 1000)
+#define V_to_uV(V) (mV_to_uV(V * 1000))
+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
+
+static struct regulator_consumer_supply evk_vmmc_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
+};
+
+static struct regulator_init_data evk_vmmc_init = {
+	.num_consumer_supplies = ARRAY_SIZE(evk_vmmc_consumers),
+	.consumer_supplies = evk_vmmc_consumers,
+};
+
+static struct fixed_voltage_config evk_vmmc_reg_config = {
+	.supply_name	= "vmmc",
+	.microvolts	= 3300000,
+	.gpio		= -1,
+	.init_data	= &evk_vmmc_init,
+};
+
+static struct platform_device evk_vmmc_reg_devices = {
+	.name		= "reg-fixed-voltage",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &evk_vmmc_reg_config,
+	},
+};
+
+static struct regulator_consumer_supply display_consumers[] = {
+	{
+		/* MAX17135 */
+		.supply = "DISPLAY",
+	},
+};
+
+static struct regulator_consumer_supply vcom_consumers[] = {
+	{
+		/* MAX17135 */
+		.supply = "VCOM",
+	},
+};
+
+static struct regulator_consumer_supply v3p3_consumers[] = {
+	{
+		/* MAX17135 */
+		.supply = "V3P3",
+	},
+};
+
+static struct regulator_init_data max17135_init_data[] = {
+	{
+		.constraints = {
+			.name = "DISPLAY",
+			.valid_ops_mask =  REGULATOR_CHANGE_STATUS,
+		},
+		.num_consumer_supplies = ARRAY_SIZE(display_consumers),
+		.consumer_supplies = display_consumers,
+	}, {
+		.constraints = {
+			.name = "GVDD",
+			.min_uV = V_to_uV(20),
+			.max_uV = V_to_uV(20),
+		},
+	}, {
+		.constraints = {
+			.name = "GVEE",
+			.min_uV = V_to_uV(-22),
+			.max_uV = V_to_uV(-22),
+		},
+	}, {
+		.constraints = {
+			.name = "HVINN",
+			.min_uV = V_to_uV(-22),
+			.max_uV = V_to_uV(-22),
+		},
+	}, {
+		.constraints = {
+			.name = "HVINP",
+			.min_uV = V_to_uV(20),
+			.max_uV = V_to_uV(20),
+		},
+	}, {
+		.constraints = {
+			.name = "VCOM",
+			.min_uV = mV_to_uV(-4325),
+			.max_uV = mV_to_uV(-500),
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+		},
+		.num_consumer_supplies = ARRAY_SIZE(vcom_consumers),
+		.consumer_supplies = vcom_consumers,
+	}, {
+		.constraints = {
+			.name = "VNEG",
+			.min_uV = V_to_uV(-15),
+			.max_uV = V_to_uV(-15),
+		},
+	}, {
+		.constraints = {
+			.name = "VPOS",
+			.min_uV = V_to_uV(15),
+			.max_uV = V_to_uV(15),
+		},
+	}, {
+		.constraints = {
+			.name = "V3P3",
+			.valid_ops_mask =  REGULATOR_CHANGE_STATUS,
+		},
+		.num_consumer_supplies = ARRAY_SIZE(v3p3_consumers),
+		.consumer_supplies = v3p3_consumers,
+	},
+};
+
+static const struct anatop_thermal_platform_data
+	mx6sl_anatop_thermal_data __initconst = {
+			.name = "anatop_thermal",
+	};
+
+static struct platform_device max17135_sensor_device = {
+	.name = "max17135_sensor",
+	.id = 0,
+};
+
+static struct max17135_platform_data max17135_pdata __initdata = {
+	.vneg_pwrup = 1,
+	.gvee_pwrup = 1,
+	.vpos_pwrup = 2,
+	.gvdd_pwrup = 1,
+	.gvdd_pwrdn = 1,
+	.vpos_pwrdn = 2,
+	.gvee_pwrdn = 1,
+	.vneg_pwrdn = 1,
+	.gpio_pmic_pwrgood = MX6SL_BRD_EPDC_PWRSTAT,
+	.gpio_pmic_vcom_ctrl = MX6SL_BRD_EPDC_VCOM,
+	.gpio_pmic_wakeup = MX6SL_BRD_EPDC_PMIC_WAKE,
+	.gpio_pmic_v3p3 = MX6SL_BRD_EPDC_PWRCTRL0,
+	.gpio_pmic_intr = MX6SL_BRD_EPDC_PMIC_INT,
+	.regulator_init = max17135_init_data,
+	.init = max17135_regulator_init,
+};
+
+static int __init max17135_regulator_init(struct max17135 *max17135)
+{
+	struct max17135_platform_data *pdata = &max17135_pdata;
+	int i, ret;
+
+	max17135->gvee_pwrup = pdata->gvee_pwrup;
+	max17135->vneg_pwrup = pdata->vneg_pwrup;
+	max17135->vpos_pwrup = pdata->vpos_pwrup;
+	max17135->gvdd_pwrup = pdata->gvdd_pwrup;
+	max17135->gvdd_pwrdn = pdata->gvdd_pwrdn;
+	max17135->vpos_pwrdn = pdata->vpos_pwrdn;
+	max17135->vneg_pwrdn = pdata->vneg_pwrdn;
+	max17135->gvee_pwrdn = pdata->gvee_pwrdn;
+
+	max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup +
+		pdata->gvdd_pwrup + pdata->gvee_pwrup;
+
+	max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood;
+	max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl;
+	max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup;
+	max17135->gpio_pmic_v3p3 = pdata->gpio_pmic_v3p3;
+	max17135->gpio_pmic_intr = pdata->gpio_pmic_intr;
+
+	gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake");
+	gpio_direction_output(max17135->gpio_pmic_wakeup, 0);
+
+	gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom");
+	gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0);
+
+	gpio_request(max17135->gpio_pmic_v3p3, "epdc-v3p3");
+	gpio_direction_output(max17135->gpio_pmic_v3p3, 0);
+
+	gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int");
+	gpio_direction_input(max17135->gpio_pmic_intr);
+
+	gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat");
+	gpio_direction_input(max17135->gpio_pmic_pwrgood);
+
+	max17135->vcom_setup = false;
+	max17135->init_done = false;
+
+	for (i = 0; i < MAX17135_NUM_REGULATORS; i++) {
+		ret = max17135_register_regulator(max17135, i,
+			&pdata->regulator_init[i]);
+		if (ret != 0) {
+			printk(KERN_ERR"max17135 regulator init failed: %d\n",
+				ret);
+			return ret;
+		}
+	}
+
+	/*
+	 * TODO: We cannot enable full constraints for now, since
+	 * it results in the PFUZE regulators being disabled
+	 * at the end of boot, which disables critical regulators.
+	 */
+	/*regulator_has_full_constraints();*/
+
+	return 0;
+}
+
+static int mx6_evk_spi_cs[] = {
+	MX6_BRD_ECSPI1_CS0,
+};
+
+static const struct spi_imx_master mx6_evk_spi_data __initconst = {
+	.chipselect     = mx6_evk_spi_cs,
+	.num_chipselect = ARRAY_SIZE(mx6_evk_spi_cs),
+};
+
+#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+static struct mtd_partition m25p32_partitions[] = {
+	{
+		.name	= "bootloader",
+		.offset	= 0,
+		.size	= 0x00100000,
+	}, {
+		.name	= "kernel",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= MTDPART_SIZ_FULL,
+	},
+};
+
+static struct flash_platform_data m25p32_spi_flash_data = {
+	.name		= "m25p32",
+	.parts		= m25p32_partitions,
+	.nr_parts	= ARRAY_SIZE(m25p32_partitions),
+	.type		= "m25p32",
+};
+
+static struct spi_board_info m25p32_spi0_board_info[] __initdata = {
+	{
+	/* The modalias must be the same as spi device driver name */
+	.modalias	= "m25p80",
+	.max_speed_hz	= 20000000,
+	.bus_num	= 0,
+	.chip_select	= 0,
+	.platform_data	= &m25p32_spi_flash_data,
+	},
+};
+#endif
+
+static void spi_device_init(void)
+{
+#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+	spi_register_board_info(m25p32_spi0_board_info,
+				ARRAY_SIZE(m25p32_spi0_board_info));
+#endif
+}
+
+static struct imx_ssi_platform_data mx6_sabresd_ssi_pdata = {
+	.flags = IMX_SSI_DMA | IMX_SSI_SYN,
+};
+
+static struct mxc_audio_platform_data wm8962_data;
+
+static struct platform_device mx6_sabresd_audio_wm8962_device = {
+	.name = "imx-wm8962",
+};
+
+static struct wm8962_pdata wm8962_config_data = {
+
+};
+
+static int wm8962_clk_enable(int enable)
+{
+	if (enable)
+		clk_enable(extern_audio_root);
+	else
+		clk_disable(extern_audio_root);
+
+	return 0;
+}
+
+static int mxc_wm8962_init(void)
+{
+	struct clk *pll4;
+	int rate;
+
+	extern_audio_root = clk_get(NULL, "extern_audio_clk");
+	if (IS_ERR(extern_audio_root)) {
+		pr_err("can't get extern_audio_root clock.\n");
+		return PTR_ERR(extern_audio_root);
+	}
+
+	pll4 = clk_get(NULL, "pll4");
+	if (IS_ERR(pll4)) {
+		pr_err("can't get pll4 clock.\n");
+		return PTR_ERR(pll4);
+	}
+
+	clk_set_parent(extern_audio_root, pll4);
+
+	rate = clk_round_rate(extern_audio_root, 26000000);
+	clk_set_rate(extern_audio_root, rate);
+
+	wm8962_data.sysclk = rate;
+	/* set AUDMUX pads to 1.8v */
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_AUD_MCLK,
+					PAD_CTL_LVE, PAD_CTL_LVE_MASK);
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_AUD_RXD,
+					PAD_CTL_LVE, PAD_CTL_LVE_MASK);
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_AUD_TXC,
+					PAD_CTL_LVE, PAD_CTL_LVE_MASK);
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_AUD_TXD,
+					PAD_CTL_LVE, PAD_CTL_LVE_MASK);
+	mxc_iomux_set_specialbits_register(MX6SL_PAD_AUD_TXFS,
+					PAD_CTL_LVE, PAD_CTL_LVE_MASK);
+
+	return 0;
+}
+
+static struct mxc_audio_platform_data wm8962_data = {
+	.ssi_num = 1,
+	.src_port = 2,
+	.ext_port = 3,
+	.hp_gpio = MX6_BRD_HEADPHONE_DET,
+	.hp_active_low = 1,
+	.mic_gpio = -1,
+	.mic_active_low = 1,
+	.init = mxc_wm8962_init,
+	.clock_enable = wm8962_clk_enable,
+};
+
+static struct regulator_consumer_supply sabresd_vwm8962_consumers[] = {
+	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
+	REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+};
+
+static struct regulator_init_data sabresd_vwm8962_init = {
+	.constraints = {
+		.name = "SPKVDD",
+		.valid_ops_mask =  REGULATOR_CHANGE_STATUS,
+		.boot_on = 1,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(sabresd_vwm8962_consumers),
+	.consumer_supplies = sabresd_vwm8962_consumers,
+};
+
+static struct fixed_voltage_config sabresd_vwm8962_reg_config = {
+	.supply_name	= "SPKVDD",
+	.microvolts		= 4325000,
+	.gpio			= -1,
+	.enabled_at_boot = 1,
+	.init_data		= &sabresd_vwm8962_init,
+};
+
+static struct platform_device sabresd_vwm8962_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id		= 4,
+	.dev	= {
+		.platform_data = &sabresd_vwm8962_reg_config,
+	},
+};
+
+static int __init imx6q_init_audio(void)
+{
+	platform_device_register(&sabresd_vwm8962_reg_devices);
+	mxc_register_device(&mx6_sabresd_audio_wm8962_device,
+			    &wm8962_data);
+	imx6q_add_imx_ssi(1, &mx6_sabresd_ssi_pdata);
+
+	return 0;
+}
+
+static struct imxi2c_platform_data mx6_evk_i2c0_data = {
+	.bitrate = 100000,
+};
+
+static struct imxi2c_platform_data mx6_evk_i2c1_data = {
+	.bitrate = 100000,
+};
+
+static struct imxi2c_platform_data mx6_evk_i2c2_data = {
+	.bitrate = 400000,
+};
+
+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("max17135", 0x48),
+		.platform_data = &max17135_pdata,
+	}, {
+		I2C_BOARD_INFO("elan-touch", 0x10),
+		.irq = gpio_to_irq(MX6SL_BRD_ELAN_INT),
+	}, {
+		I2C_BOARD_INFO("mma8450", 0x1c),
+	},
+};
+
+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("wm8962", 0x1a),
+		.platform_data = &wm8962_config_data,
+	},
+};
+
+static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+	{
+	},
+};
+
+static struct mxc_dvfs_platform_data mx6sl_evk_dvfscore_data = {
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.reg_id			= "VDDCORE",
+	.soc_id			= "VDDSOC",
+#else
+	.reg_id			= "cpu_vddgp",
+	.soc_id			= "cpu_vddsoc",
+	.pu_id			= "cpu_vddvpu",
+#endif
+	.clk1_id		= "cpu_clk",
+	.clk2_id		= "gpc_dvfs_clk",
+	.gpc_cntr_offset	= MXC_GPC_CNTR_OFFSET,
+	.ccm_cdcr_offset	= MXC_CCM_CDCR_OFFSET,
+	.ccm_cacrr_offset	= MXC_CCM_CACRR_OFFSET,
+	.ccm_cdhipr_offset	= MXC_CCM_CDHIPR_OFFSET,
+	.prediv_mask		= 0x1F800,
+	.prediv_offset		= 11,
+	.prediv_val		= 3,
+	.div3ck_mask		= 0xE0000000,
+	.div3ck_offset		= 29,
+	.div3ck_val		= 2,
+	.emac_val		= 0x08,
+	.upthr_val		= 25,
+	.dnthr_val		= 9,
+	.pncthr_val		= 33,
+	.upcnt_val		= 10,
+	.dncnt_val		= 10,
+	.delay_time		= 80,
+};
+
+static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
+	.reserved_mem_size = SZ_128M,
+};
+
+void __init early_console_setup(unsigned long base, struct clk *clk);
+
+static inline void mx6_evk_init_uart(void)
+{
+	imx6q_add_imx_uart(0, NULL); /* DEBUG UART1 */
+}
+
+static int mx6sl_evk_fec_phy_init(struct phy_device *phydev)
+{
+	int val;
+
+	/* power on FEC phy and reset phy */
+	gpio_request(MX6_BRD_FEC_PWR_EN, "fec-pwr");
+	gpio_direction_output(MX6_BRD_FEC_PWR_EN, 0);
+	/* wait RC ms for hw reset */
+	msleep(1);
+	gpio_direction_output(MX6_BRD_FEC_PWR_EN, 1);
+
+	/* check phy power */
+	val = phy_read(phydev, 0x0);
+	if (val & BMCR_PDOWN)
+		phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));
+
+	return 0;
+}
+
+static struct fec_platform_data fec_data __initdata = {
+	.init = mx6sl_evk_fec_phy_init,
+	.phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static int epdc_get_pins(void)
+{
+	int ret = 0;
+
+	/* Claim GPIOs for EPDC pins - used during power up/down */
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_0, "epdc_d0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_1, "epdc_d1");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_2, "epdc_d2");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_3, "epdc_d3");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_4, "epdc_d4");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_5, "epdc_d5");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_6, "epdc_d6");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_7, "epdc_d7");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDCLK, "epdc_gdclk");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDSP, "epdc_gdsp");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDOE, "epdc_gdoe");
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDRL, "epdc_gdrl");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCLK, "epdc_sdclk");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDOE, "epdc_sdoe");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDLE, "epdc_sdle");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDSHR, "epdc_sdshr");
+	ret |= gpio_request(MX6SL_BRD_EPDC_BDR0, "epdc_bdr0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE0, "epdc_sdce0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE1, "epdc_sdce1");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE2, "epdc_sdce2");
+
+	return ret;
+}
+
+static void epdc_put_pins(void)
+{
+	gpio_free(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_7);
+	gpio_free(MX6SL_BRD_EPDC_GDCLK);
+	gpio_free(MX6SL_BRD_EPDC_GDSP);
+	gpio_free(MX6SL_BRD_EPDC_GDOE);
+	gpio_free(MX6SL_BRD_EPDC_GDRL);
+	gpio_free(MX6SL_BRD_EPDC_SDCLK);
+	gpio_free(MX6SL_BRD_EPDC_SDOE);
+	gpio_free(MX6SL_BRD_EPDC_SDLE);
+	gpio_free(MX6SL_BRD_EPDC_SDSHR);
+	gpio_free(MX6SL_BRD_EPDC_BDR0);
+	gpio_free(MX6SL_BRD_EPDC_SDCE0);
+	gpio_free(MX6SL_BRD_EPDC_SDCE1);
+	gpio_free(MX6SL_BRD_EPDC_SDCE2);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* Configure MUX settings to enable EPDC use */
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_epdc_enable_pads, \
+				ARRAY_SIZE(mx6sl_brd_epdc_enable_pads));
+
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_7);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDSP);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDOE);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDRL);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDOE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDLE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDSHR);
+	gpio_direction_input(MX6SL_BRD_EPDC_BDR0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE2);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to
+	 * GPIO and drive to 0. */
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_epdc_disable_pads, \
+				ARRAY_SIZE(mx6sl_brd_epdc_disable_pads));
+
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_2, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_3, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_4, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_5, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_6, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_7, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDSP, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDOE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDRL, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDOE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDLE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDSHR, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_BDR0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE2, 0);
+}
+
+static struct fb_videomode e60_v110_mode = {
+	.name = "E60_V110",
+	.refresh = 50,
+	.xres = 800,
+	.yres = 600,
+	.pixclock = 18604700,
+	.left_margin = 8,
+	.right_margin = 178,
+	.upper_margin = 4,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+static struct fb_videomode e60_v220_mode = {
+	.name = "E60_V220",
+	.refresh = 85,
+	.xres = 800,
+	.yres = 600,
+	.pixclock = 30000000,
+	.left_margin = 8,
+	.right_margin = 164,
+	.upper_margin = 4,
+	.lower_margin = 8,
+	.hsync_len = 4,
+	.vsync_len = 1,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+	.refresh = 85,
+	.xres = 800,
+	.yres = 600,
+};
+static struct fb_videomode e060scm_mode = {
+	.name = "E060SCM",
+	.refresh = 85,
+	.xres = 800,
+	.yres = 600,
+	.pixclock = 26666667,
+	.left_margin = 8,
+	.right_margin = 100,
+	.upper_margin = 4,
+	.lower_margin = 8,
+	.hsync_len = 4,
+	.vsync_len = 1,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+static struct fb_videomode e97_v110_mode = {
+	.name = "E97_V110",
+	.refresh = 50,
+	.xres = 1200,
+	.yres = 825,
+	.pixclock = 32000000,
+	.left_margin = 12,
+	.right_margin = 128,
+	.upper_margin = 4,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+
+static struct imx_epdc_fb_mode panel_modes[] = {
+	{
+		&e60_v110_mode,
+		4,      /* vscan_holdoff */
+		10,     /* sdoed_width */
+		20,     /* sdoed_delay */
+		10,     /* sdoez_width */
+		20,     /* sdoez_delay */
+		428,    /* gdclk_hp_offs */
+		20,     /* gdsp_offs */
+		0,      /* gdoe_offs */
+		1,      /* gdclk_offs */
+		1,      /* num_ce */
+	},
+	{
+		&e60_v220_mode,
+		4,      /* vscan_holdoff */
+		10,     /* sdoed_width */
+		20,     /* sdoed_delay */
+		10,     /* sdoez_width */
+		20,     /* sdoez_delay */
+		465,    /* gdclk_hp_offs */
+		20,     /* gdsp_offs */
+		0,      /* gdoe_offs */
+		9,      /* gdclk_offs */
+		1,      /* num_ce */
+	},
+	{
+		&e060scm_mode,
+		4,      /* vscan_holdoff */
+		10,     /* sdoed_width */
+		20,     /* sdoed_delay */
+		10,     /* sdoez_width */
+		20,     /* sdoez_delay */
+		419,    /* gdclk_hp_offs */
+		20,     /* gdsp_offs */
+		0,      /* gdoe_offs */
+		5,      /* gdclk_offs */
+		1,      /* num_ce */
+	},
+	{
+		&e97_v110_mode,
+		8,      /* vscan_holdoff */
+		10,     /* sdoed_width */
+		20,     /* sdoed_delay */
+		10,     /* sdoez_width */
+		20,     /* sdoez_delay */
+		632,    /* gdclk_hp_offs */
+		20,     /* gdsp_offs */
+		0,      /* gdoe_offs */
+		1,      /* gdclk_offs */
+		3,      /* num_ce */
+	}
+};
+
+static struct imx_epdc_fb_platform_data epdc_data = {
+	.epdc_mode = panel_modes,
+	.num_modes = ARRAY_SIZE(panel_modes),
+	.get_pins = epdc_get_pins,
+	.put_pins = epdc_put_pins,
+	.enable_pins = epdc_enable_pins,
+	.disable_pins = epdc_disable_pins,
+};
+
+static int spdc_get_pins(void)
+{
+	int ret = 0;
+
+	/* Claim GPIOs for SPDC pins - used during power up/down */
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_0, "SPDC_D0");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_1, "SPDC_D1");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_2, "SPDC_D2");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_3, "SPDC_D3");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_4, "SPDC_D4");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_5, "SPDC_D5");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_6, "SPDC_D6");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_7, "SPDC_D7");
+
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDOE, "SIPIX_YOE");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_9, "SIPIX_PWR_RDY");
+
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDSP, "SIPIX_YDIO");
+
+	ret |= gpio_request(MX6SL_BRD_EPDC_GDCLK, "SIPIX_YCLK");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDSHR, "SIPIX_XDIO");
+
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDLE, "SIPIX_LD");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE1, "SIPIX_SOE");
+
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCLK, "SIPIX_XCLK");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDDO_10, "SIPIX_SHD_N");
+	ret |= gpio_request(MX6SL_BRD_EPDC_SDCE0, "SIPIX2_CE");
+
+	return ret;
+}
+
+static void spdc_put_pins(void)
+{
+	gpio_free(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_7);
+
+	gpio_free(MX6SL_BRD_EPDC_GDOE);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_9);
+	gpio_free(MX6SL_BRD_EPDC_GDSP);
+	gpio_free(MX6SL_BRD_EPDC_GDCLK);
+	gpio_free(MX6SL_BRD_EPDC_SDSHR);
+	gpio_free(MX6SL_BRD_EPDC_SDLE);
+	gpio_free(MX6SL_BRD_EPDC_SDCE1);
+	gpio_free(MX6SL_BRD_EPDC_SDCLK);
+	gpio_free(MX6SL_BRD_EPDC_SDDO_10);
+	gpio_free(MX6SL_BRD_EPDC_SDCE0);
+}
+
+static void spdc_enable_pins(void)
+{
+	/* Configure MUX settings to enable SPDC use */
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_spdc_enable_pads, \
+				ARRAY_SIZE(mx6sl_brd_spdc_enable_pads));
+
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_0);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_2);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_3);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_4);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_5);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_6);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_7);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDOE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_9);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDSP);
+	gpio_direction_input(MX6SL_BRD_EPDC_GDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDSHR);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDLE);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE1);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCLK);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDDO_10);
+	gpio_direction_input(MX6SL_BRD_EPDC_SDCE0);
+}
+
+static void spdc_disable_pins(void)
+{
+	/* Configure MUX settings for SPDC pins to
+	 * GPIO and drive to 0. */
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_spdc_disable_pads, \
+				ARRAY_SIZE(mx6sl_brd_spdc_disable_pads));
+
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_0, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_2, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_3, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_4, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_5, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_6, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_7, 0);
+
+	gpio_direction_output(MX6SL_BRD_EPDC_GDOE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_9, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDSP, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_GDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDSHR, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDLE, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE1, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCLK, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDDO_10, 0);
+	gpio_direction_output(MX6SL_BRD_EPDC_SDCE0, 0);
+}
+
+static struct imx_spdc_panel_init_set spdc_init_set = {
+	.yoe_pol = false,
+	.dual_gate = false,
+	.resolution = 0,
+	.ud = false,
+	.rl = false,
+	.data_filter_n = true,
+	.power_ready = true,
+	.rgbw_mode_enable = false,
+	.hburst_len_en = true,
+};
+
+static struct fb_videomode erk_1_4_a01 = {
+	.name = "ERK_1_4_A01",
+	.refresh = 50,
+	.xres = 800,
+	.yres = 600,
+	.pixclock = 40000000,
+	.vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct imx_spdc_fb_mode spdc_panel_modes[] = {
+	{
+		&erk_1_4_a01,
+		&spdc_init_set,
+		.wave_timing = "pvi"
+	},
+};
+
+static struct imx_spdc_fb_platform_data spdc_data = {
+	.spdc_mode = spdc_panel_modes,
+	.num_modes = ARRAY_SIZE(spdc_panel_modes),
+	.get_pins = spdc_get_pins,
+	.put_pins = spdc_put_pins,
+	.enable_pins = spdc_enable_pins,
+	.disable_pins = spdc_disable_pins,
+};
+
+static int __init early_use_spdc_sel(char *p)
+{
+	spdc_sel = 1;
+	return 0;
+}
+early_param("spdc", early_use_spdc_sel);
+
+static void setup_spdc(void)
+{
+	/* GPR0[8]: 0:EPDC, 1:SPDC */
+	if (spdc_sel)
+		mxc_iomux_set_gpr_register(0, 8, 1, 1);
+}
+
+static void imx6_evk_usbotg_vbus(bool on)
+{
+	if (on)
+		gpio_set_value(MX6_BRD_USBOTG1_PWR, 1);
+	else
+		gpio_set_value(MX6_BRD_USBOTG1_PWR, 0);
+}
+
+static void __init mx6_evk_init_usb(void)
+{
+	int ret = 0;
+
+	imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
+
+	/* disable external charger detect,
+	 * or it will affect signal quality at dp.
+	 */
+
+	ret = gpio_request(MX6_BRD_USBOTG1_PWR, "usbotg-pwr");
+	if (ret) {
+		pr_err("failed to get GPIO MX6_BRD_USBOTG1_PWR:%d\n", ret);
+		return;
+	}
+	gpio_direction_output(MX6_BRD_USBOTG1_PWR, 0);
+
+	ret = gpio_request(MX6_BRD_USBOTG2_PWR, "usbh1-pwr");
+	if (ret) {
+		pr_err("failed to get GPIO MX6_BRD_USBOTG2_PWR:%d\n", ret);
+		return;
+	}
+	gpio_direction_output(MX6_BRD_USBOTG2_PWR, 1);
+
+	mx6_set_otghost_vbus_func(imx6_evk_usbotg_vbus);
+	mx6_usb_dr_init();
+#ifdef CONFIG_USB_EHCI_ARC_HSIC
+	mx6_usb_h2_init();
+#endif
+}
+
+static struct platform_pwm_backlight_data mx6_evk_pwm_backlight_data = {
+	.pwm_id		= 0,
+	.max_brightness	= 255,
+	.dft_brightness	= 128,
+	.pwm_period_ns	= 50000,
+};
+static struct fb_videomode video_modes[] = {
+	{
+	 /* 800x480 @ 57 Hz , pixel clk @ 32MHz */
+	 "SEIKO-WVGA", 60, 800, 480, 29850, 99, 164, 33, 10, 10, 10,
+	 FB_SYNC_CLK_LAT_FALL,
+	 FB_VMODE_NONINTERLACED,
+	 0,},
+};
+
+static struct mxc_fb_platform_data fb_data[] = {
+	{
+	 .interface_pix_fmt = V4L2_PIX_FMT_RGB24,
+	 .mode_str = "SEIKO-WVGA",
+	 .mode = video_modes,
+	 .num_modes = ARRAY_SIZE(video_modes),
+	 },
+};
+
+static struct platform_device lcd_wvga_device = {
+	.name = "lcd_seiko",
+};
+
+static int mx6sl_evk_keymap[] = {
+	KEY(0, 0, KEY_SELECT),
+	KEY(0, 1, KEY_BACK),
+	KEY(0, 2, KEY_F1),
+	KEY(0, 3, KEY_F2),
+
+	KEY(1, 0, KEY_F3),
+	KEY(1, 1, KEY_F4),
+	KEY(1, 2, KEY_F5),
+	KEY(1, 3, KEY_MENU),
+
+	KEY(2, 0, KEY_PREVIOUS),
+	KEY(2, 1, KEY_NEXT),
+	KEY(2, 2, KEY_HOME),
+	KEY(2, 3, KEY_NEXT),
+
+	KEY(3, 0, KEY_UP),
+	KEY(3, 1, KEY_LEFT),
+	KEY(3, 2, KEY_RIGHT),
+	KEY(3, 3, KEY_DOWN),
+};
+
+static const struct matrix_keymap_data mx6sl_evk_map_data __initconst = {
+	.keymap		= mx6sl_evk_keymap,
+	.keymap_size	= ARRAY_SIZE(mx6sl_evk_keymap),
+};
+static void __init elan_ts_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_elan_pads,
+					ARRAY_SIZE(mx6sl_brd_elan_pads));
+
+	/* ELAN Touchscreen */
+	gpio_request(MX6SL_BRD_ELAN_INT, "elan-interrupt");
+	gpio_direction_input(MX6SL_BRD_ELAN_INT);
+
+	gpio_request(MX6SL_BRD_ELAN_CE, "elan-cs");
+	gpio_direction_output(MX6SL_BRD_ELAN_CE, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_CE, 0);
+
+	gpio_request(MX6SL_BRD_ELAN_RST, "elan-rst");
+	gpio_direction_output(MX6SL_BRD_ELAN_RST, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_RST, 0);
+	mdelay(1);
+	gpio_direction_output(MX6SL_BRD_ELAN_RST, 1);
+	gpio_direction_output(MX6SL_BRD_ELAN_CE, 1);
+}
+
+#define SNVS_LPCR 0x38
+static void mx6_snvs_poweroff(void)
+{
+	u32 value;
+	void __iomem *mx6_snvs_base = MX6_IO_ADDRESS(MX6Q_SNVS_BASE_ADDR);
+
+	value = readl(mx6_snvs_base + SNVS_LPCR);
+	/* set TOP and DP_EN bit */
+	writel(value | 0x60, mx6_snvs_base + SNVS_LPCR);
+}
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mx6_evk_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_pads,
+					ARRAY_SIZE(mx6sl_brd_pads));
+
+	elan_ts_init();
+
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	gp_reg_id = mx6sl_evk_dvfscore_data.reg_id;
+	soc_reg_id = mx6sl_evk_dvfscore_data.soc_id;
+#else
+	gp_reg_id = mx6sl_evk_dvfscore_data.reg_id;
+	soc_reg_id = mx6sl_evk_dvfscore_data.soc_id;
+	pu_reg_id = mx6sl_evk_dvfscore_data.pu_id;
+	mx6_cpu_regulator_init();
+#endif
+
+	imx6q_add_imx_snvs_rtc();
+
+	imx6q_add_imx_i2c(0, &mx6_evk_i2c0_data);
+	imx6q_add_imx_i2c(1, &mx6_evk_i2c1_data);
+	i2c_register_board_info(0, mxc_i2c0_board_info,
+			ARRAY_SIZE(mxc_i2c0_board_info));
+	i2c_register_board_info(1, mxc_i2c1_board_info,
+			ARRAY_SIZE(mxc_i2c1_board_info));
+	imx6q_add_imx_i2c(2, &mx6_evk_i2c2_data);
+	i2c_register_board_info(2, mxc_i2c2_board_info,
+			ARRAY_SIZE(mxc_i2c2_board_info));
+
+	/* SPI */
+	imx6q_add_ecspi(0, &mx6_evk_spi_data);
+	spi_device_init();
+
+	mx6sl_evk_init_pfuze100(0);
+
+	imx6q_add_anatop_thermal_imx(1, &mx6sl_anatop_thermal_data);
+
+	mx6_evk_init_uart();
+	/* get enet tx reference clk from FEC_REF_CLK pad.
+	 * GPR1[14] = 0, GPR1[18:17] = 00
+	 */
+	mxc_iomux_set_gpr_register(1, 14, 1, 0);
+	mxc_iomux_set_gpr_register(1, 17, 2, 0);
+
+	imx6_init_fec(fec_data);
+
+	platform_device_register(&evk_vmmc_reg_devices);
+	imx6q_add_sdhci_usdhc_imx(0, &mx6_evk_sd1_data);
+	imx6q_add_sdhci_usdhc_imx(1, &mx6_evk_sd2_data);
+	imx6q_add_sdhci_usdhc_imx(2, &mx6_evk_sd3_data);
+
+	mx6_evk_init_usb();
+	imx6q_add_otp();
+	imx6q_add_mxc_pwm(0);
+	imx6q_add_mxc_pwm_backlight(0, &mx6_evk_pwm_backlight_data);
+	imx6dl_add_imx_elcdif(&fb_data[0]);
+
+	gpio_request(MX6_BRD_LCD_PWR_EN, "elcdif-power-on");
+	gpio_direction_output(MX6_BRD_LCD_PWR_EN, 1);
+	mxc_register_device(&lcd_wvga_device, NULL);
+
+	imx6dl_add_imx_pxp();
+	imx6dl_add_imx_pxp_client();
+	mxc_register_device(&max17135_sensor_device, NULL);
+	setup_spdc();
+	if (!spdc_sel)
+		imx6dl_add_imx_epdc(&epdc_data);
+	else
+		imx6sl_add_imx_spdc(&spdc_data);
+	imx6q_add_dvfs_core(&mx6sl_evk_dvfscore_data);
+
+	imx6q_init_audio();
+
+	imx6q_add_viim();
+	imx6q_add_imx2_wdt(0, NULL);
+
+	imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
+	imx6sl_add_imx_keypad(&mx6sl_evk_map_data);
+	imx6q_add_busfreq();
+	imx6sl_add_dcp();
+	imx6sl_add_rngb();
+	imx6sl_add_imx_pxp_v4l2();
+
+	imx6q_add_perfmon(0);
+	imx6q_add_perfmon(1);
+	imx6q_add_perfmon(2);
+
+	pm_power_off = mx6_snvs_poweroff;
+}
+
+extern void __iomem *twd_base;
+static void __init mx6_timer_init(void)
+{
+	struct clk *uart_clk;
+#ifdef CONFIG_LOCAL_TIMERS
+	twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
+	BUG_ON(!twd_base);
+#endif
+	mx6sl_clocks_init(32768, 24000000, 0, 0);
+
+	uart_clk = clk_get_sys("imx-uart.0", NULL);
+	early_console_setup(UART1_BASE_ADDR, uart_clk);
+}
+
+static struct sys_timer mxc_timer = {
+	.init   = mx6_timer_init,
+};
+
+static void __init mx6_evk_reserve(void)
+{
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
+	phys_addr_t phys;
+
+	if (imx6q_gpu_pdata.reserved_mem_size) {
+		phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
+					   SZ_4K, MEMBLOCK_ALLOC_ACCESSIBLE);
+		memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
+		imx6q_gpu_pdata.reserved_mem_base = phys;
+	}
+#endif
+}
+
+MACHINE_START(MX6SL_EVK, "Freescale i.MX 6SoloLite EVK Board")
+	.boot_params	= MX6SL_PHYS_OFFSET + 0x100,
+	.map_io		= mx6_map_io,
+	.init_irq	= mx6_init_irq,
+	.init_machine	= mx6_evk_init,
+	.timer		= &mxc_timer,
+	.reserve	= mx6_evk_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index 9304c48361fa..151b4ee27eb6 100644
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -47,12 +47,13 @@
 #include <linux/suspend.h>
 
 #define LPAPM_CLK		24000000
+#define DDR_AUDIO_CLK	50000000
 #define DDR_MED_CLK		400000000
 #define DDR3_NORMAL_CLK		528000000
 #define GPC_PGC_GPU_PGCR_OFFSET	0x260
 #define GPC_CNTR_OFFSET		0x0
 
-DEFINE_SPINLOCK(ddr_freq_lock);
+static DEFINE_SPINLOCK(freq_lock);
 
 int low_bus_freq_mode;
 int audio_bus_freq_mode;
@@ -69,18 +70,25 @@ int bus_freq_scaling_is_active;
 int lp_high_freq;
 int lp_med_freq;
 int lp_audio_freq;
+int high_cpu_freq;
 unsigned int ddr_low_rate;
 unsigned int ddr_med_rate;
 unsigned int ddr_normal_rate;
 
 int low_freq_bus_used(void);
 void set_ddr_freq(int ddr_freq);
+void *mx6sl_wfi_iram_base;
+void (*mx6sl_wfi_iram)(int arm_podf, unsigned long wfi_iram_addr) = NULL;
+extern void mx6sl_wait (int arm_podf, unsigned long wfi_iram_addr);
+
+void *mx6sl_ddr_freq_base;
+void (*mx6sl_ddr_freq_change_iram)(int ddr_freq, int low_bus_freq_mode) = NULL;
+extern void mx6sl_ddr_iram(int ddr_freq);
 
 extern int init_mmdc_settings(void);
 extern struct cpu_op *(*get_cpu_op)(int *op);
 extern int update_ddr_freq(int ddr_rate);
 extern int chip_rev;
-extern bool arm_mem_clked_in_wait;
 
 DEFINE_MUTEX(bus_freq_mutex);
 
@@ -88,6 +96,7 @@ struct timeval start_time;
 struct timeval end_time;
 
 static int cpu_op_nr;
+static u32 org_arm_podf;
 static struct cpu_op *cpu_op_tbl;
 static struct clk *pll2_400;
 static struct clk *axi_clk;
@@ -97,18 +106,17 @@ static struct clk *osc_clk;
 static struct clk *cpu_clk;
 static struct clk *pll3;
 static struct clk *pll2;
+static struct clk *pll1;
+static struct clk *pll1_sw_clk;
 static struct clk *pll3_sw_clk;
 static struct clk *pll2_200;
 static struct clk *mmdc_ch0_axi;
-struct regulator *vddsoc_cap_regulator;
 static struct clk *pll3_540;
 
 static struct delayed_work low_bus_freq_handler;
 
 static void reduce_bus_freq_handler(struct work_struct *work)
 {
-	int ret;
-
 	mutex_lock(&bus_freq_mutex);
 	if (low_bus_freq_mode || !low_freq_bus_used()) {
 		mutex_unlock(&bus_freq_mutex);
@@ -133,13 +141,13 @@ static void reduce_bus_freq_handler(struct work_struct *work)
 		if (lp_audio_freq) {
 			/* Need to ensure that PLL2_PFD_400M is kept ON. */
 			clk_enable(pll2_400);
-			update_ddr_freq(50000000);
+			update_ddr_freq(DDR_AUDIO_CLK);
 			/* Make sure periph clk's parent also got updated */
 			clk_set_parent(periph_clk, pll2_200);
 			audio_bus_freq_mode = 1;
 			low_bus_freq_mode = 0;
 		} else {
-			update_ddr_freq(24000000);
+			update_ddr_freq(LPAPM_CLK);
 			/* Make sure periph clk's parent also got updated */
 			clk_set_parent(periph_clk, osc_clk);
 			if (audio_bus_freq_mode)
@@ -154,43 +162,77 @@ static void reduce_bus_freq_handler(struct work_struct *work)
 		clk_disable(pll3);
 		med_bus_freq_mode = 0;
 	} else {
-		/* Set VDDSOC_CAP to 1.1V */
-		ret = regulator_set_voltage(vddsoc_cap_regulator, 1100000,
-					    1100000);
-		if (ret < 0) {
-			printk(KERN_DEBUG
-			       "COULD NOT DECREASE VDDSOC_CAP VOLTAGE!!!!\n");
-			return;
-		}
-
-		udelay(150);
+		u32 reg;
+		u32  div;
+		unsigned long flags;
 
-		arm_mem_clked_in_wait = true;
+		spin_lock_irqsave(&freq_lock, flags);
 
-		/* Set periph_clk to be sourced from OSC_CLK */
-		/* Set MMDC clk to 25MHz. */
-		/* First need to set the divider before changing the parent */
-		/* if parent clock is larger than previous one */
-		clk_set_rate(mmdc_ch0_axi, clk_get_rate(mmdc_ch0_axi) / 2);
-		clk_set_parent(mmdc_ch0_axi, pll3_sw_clk);
-		clk_set_parent(mmdc_ch0_axi, pll2_200);
-		clk_set_rate(mmdc_ch0_axi,
-			     clk_round_rate(mmdc_ch0_axi, LPAPM_CLK));
-
-		/* Set AXI to 24MHz. */
-		clk_set_parent(periph_clk, osc_clk);
-		clk_set_rate(axi_clk, clk_round_rate(axi_clk, LPAPM_CLK));
-		/* Set AHB to 24MHz. */
-		clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, LPAPM_CLK));
+		if (high_bus_freq_mode) {
+			/* Set periph_clk to be sourced from OSC_CLK */
+			/* Set AXI to 24MHz. */
+			clk_set_parent(periph_clk, osc_clk);
+			clk_set_rate(axi_clk,
+				clk_round_rate(axi_clk, LPAPM_CLK));
+			/* Set AHB to 24MHz. */
+			clk_set_rate(ahb_clk,
+				clk_round_rate(ahb_clk, LPAPM_CLK));
+		}
+		if (lp_audio_freq) {
+			/* PLL2 is on in this mode, as DDR is at 50MHz. */
+			/* Now change DDR freq while running from IRAM. */
+			mx6sl_ddr_freq_change_iram(DDR_AUDIO_CLK,
+							low_bus_freq_mode);
+
+			if (low_bus_freq_mode) {
+				/* Swtich ARM to run off PLL2_PFD2_400MHz
+				 * since DDR is anway at 50MHz.
+				 */
+				clk_set_parent(pll1_sw_clk, pll2_400);
+
+				/* Ensure that the clock will be
+				  * at original speed.
+				  */
+				reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR);
+				while (__raw_readl(MXC_CCM_CDHIPR))
+					;
+			}
+			low_bus_freq_mode = 0;
+			audio_bus_freq_mode = 1;
+		} else {
+			/* Set MMDC clk to 24MHz. */
+			/* Since we are going to set PLL2 in bypass mode,
+			  * move the CPU clock off PLL2.
+			  */
+			/* Ensure that the clock will be at
+			  * lowest possible freq.
+			  */
+			org_arm_podf = __raw_readl(MXC_CCM_CACRR);
+			/* Need to enable PLL1 before setting its rate. */
+			clk_enable(pll1);
+			clk_set_rate(pll1,
+				cpu_op_tbl[cpu_op_nr - 1].pll_lpm_rate);
+			div = clk_get_rate(pll1) /
+					cpu_op_tbl[cpu_op_nr - 1].cpu_rate;
+
+			reg = __raw_writel(div - 1, MXC_CCM_CACRR);
+			while (__raw_readl(MXC_CCM_CDHIPR))
+				;
+			clk_set_parent(pll1_sw_clk, pll1);
+
+			/* Now change DDR freq while running from IRAM. */
+			mx6sl_ddr_freq_change_iram(LPAPM_CLK,
+					low_bus_freq_mode);
 
-		low_bus_freq_mode = 1;
-		audio_bus_freq_mode = 0;
+			low_bus_freq_mode = 1;
+			audio_bus_freq_mode = 0;
+		}
+		spin_unlock_irqrestore(&freq_lock, flags);
 	}
-
 	high_bus_freq_mode = 0;
-	med_bus_freq_mode = 0;
 	mutex_unlock(&bus_freq_mutex);
 }
+
 /* Set the DDR, AHB to 24MHz.
   * This mode will be activated only when none of the modules that
   * need a higher DDR or AHB frequency are active.
@@ -215,61 +257,43 @@ int set_low_bus_freq(void)
  */
 int set_high_bus_freq(int high_bus_freq)
 {
-	int ret;
-
 	if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
 		cancel_delayed_work_sync(&low_bus_freq_handler);
-	mutex_lock(&bus_freq_mutex);
-	if (busfreq_suspended) {
-		mutex_unlock(&bus_freq_mutex);
+
+	if (busfreq_suspended)
 		return 0;
-	}
 
-	if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) {
-		mutex_unlock(&bus_freq_mutex);
+
+	if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
 		return 0;
-	}
 
-	if (high_bus_freq_mode && high_bus_freq) {
-		mutex_unlock(&bus_freq_mutex);
+
+	if (high_bus_freq_mode && high_bus_freq)
 		return 0;
-	}
 
-	if (med_bus_freq_mode && !high_bus_freq) {
-		mutex_unlock(&bus_freq_mutex);
+
+	/* medium bus freq is only supported for MX6DQ */
+	if (cpu_is_mx6q() && med_bus_freq_mode && !high_bus_freq)
 		return 0;
-	}
 
 	if (cpu_is_mx6dl() && high_bus_freq)
 		high_bus_freq = 0;
 
-	if (cpu_is_mx6dl() && med_bus_freq_mode) {
-		mutex_unlock(&bus_freq_mutex);
+	if (cpu_is_mx6dl() && med_bus_freq_mode)
 		return 0;
-	}
+
 	if ((high_bus_freq_mode && (high_bus_freq || lp_high_freq)) ||
 	    (med_bus_freq_mode && !high_bus_freq && lp_med_freq &&
-	     !lp_high_freq)) {
-		mutex_unlock(&bus_freq_mutex);
+	     !lp_high_freq))
 		return 0;
-	}
+
 	if (cpu_is_mx6sl()) {
-		/* Set the voltage of VDDSOC to 1.2V as in normal mode. */
-		ret = regulator_set_voltage(vddsoc_cap_regulator, 1200000,
-					    1200000);
-		if (ret < 0) {
-			printk(KERN_DEBUG
-			       "COULD NOT INCREASE VDDSOC_CAP VOLTAGE!!!!\n");
-			return ret;
-		}
+		u32 reg;
+		unsigned long flags;
 
-		/* Need to wait for the regulator to come back up */
-		/*
-		 * Delay time is based on the number of 24MHz clock cycles
-		 * programmed in the ANA_MISC2_BASE_ADDR for each
-		 * 25mV step.
-		 */
-		udelay(150);
+		spin_lock_irqsave(&freq_lock, flags);
+		/* Change DDR freq in IRAM. */
+		mx6sl_ddr_freq_change_iram(ddr_normal_rate, low_bus_freq_mode);
 
 		/* Set periph_clk to be sourced from pll2_pfd2_400M */
 		/* First need to set the divider before changing the */
@@ -280,17 +304,20 @@ int set_high_bus_freq(int high_bus_freq)
 			     clk_round_rate(axi_clk, LPAPM_CLK / 2));
 		clk_set_parent(periph_clk, pll2_400);
 
-		/* Set mmdc_clk_root to be sourced */
-		/* from pll2_pfd2_400M */
-		clk_set_rate(mmdc_ch0_axi,
-		     clk_round_rate(mmdc_ch0_axi, LPAPM_CLK / 2));
-		clk_set_parent(mmdc_ch0_axi, pll3_sw_clk);
-		clk_set_parent(mmdc_ch0_axi, pll2_400);
-		clk_set_rate(mmdc_ch0_axi,
-		     clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK));
+		if (low_bus_freq_mode) {
+			/* Now move ARM to be sourced from PLL2_400 too. */
+			clk_set_parent(pll1_sw_clk, pll2_400);
 
+			/* Ensure that the clock will be at original speed. */
+			reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR);
+			while (__raw_readl(MXC_CCM_CDHIPR))
+				;
+			clk_disable(pll1);
+		}
 		high_bus_freq_mode = 1;
-		med_bus_freq_mode = 0;
+		low_bus_freq_mode = 0;
+		audio_bus_freq_mode = 0;
+		spin_unlock_irqrestore(&freq_lock, flags);
 	} else {
 		clk_enable(pll3);
 		if (high_bus_freq) {
@@ -317,18 +344,11 @@ int set_high_bus_freq(int high_bus_freq)
 			clk_get_parent(axi_clk) != pll3_540)
 			clk_set_parent(axi_clk, pll3_540);
 
+		low_bus_freq_mode = 0;
+		audio_bus_freq_mode = 0;
+
 		clk_disable(pll3);
 	}
-
-	low_bus_freq_mode = 0;
-	audio_bus_freq_mode = 0;
-
-	/* Ensure that WAIT mode can be entered in high bus freq mode. */
-
-	if (cpu_is_mx6sl())
-		arm_mem_clked_in_wait = false;
-
-	mutex_unlock(&bus_freq_mutex);
 	return 0;
 }
 
@@ -340,11 +360,8 @@ int low_freq_bus_used(void)
 	/* We only go the lowest setpoint if ARM is also
 	 * at the lowest setpoint.
 	 */
-	if ((clk_get_rate(cpu_clk) >
-			cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
-		|| (cpu_op_nr == 1)) {
+	if (high_cpu_freq)
 		return 0;
-	}
 
 	if ((lp_high_freq == 0)
 	    && (lp_med_freq == 0))
@@ -356,62 +373,80 @@ int low_freq_bus_used(void)
 void bus_freq_update(struct clk *clk, bool flag)
 {
 	mutex_lock(&bus_freq_mutex);
+
 	if (flag) {
-		/* Update count */
-		if (clk->flags & AHB_HIGH_SET_POINT)
-			lp_high_freq++;
-		else if (clk->flags & AHB_MED_SET_POINT)
-			lp_med_freq++;
-		else if (clk->flags & AHB_AUDIO_SET_POINT)
-			lp_audio_freq++;
-		/* Update bus freq */
-		if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
-			&& (clk_get_usecount(clk) == 0)) {
-			if (!(clk->flags &
-				(AHB_HIGH_SET_POINT | AHB_MED_SET_POINT)))  {
-			if (low_freq_bus_used()) {
-				if ((clk->flags & AHB_AUDIO_SET_POINT) & !audio_bus_freq_mode)
-					set_low_bus_freq();
-				else if (!low_bus_freq_mode)
-					set_low_bus_freq();
-			}
-		} else {
-			if ((clk->flags & AHB_MED_SET_POINT)
-				&& !med_bus_freq_mode) {
-				/* Set to Medium setpoint */
-				mutex_unlock(&bus_freq_mutex);
+		if (clk == cpu_clk) {
+			/* The CPU freq is being increased.
+			  * check if we need to increase the bus freq
+			  */
+			high_cpu_freq = 1;
+			if (low_bus_freq_mode || audio_bus_freq_mode)
 				set_high_bus_freq(0);
-				return;
-			}
-			else if ((clk->flags & AHB_HIGH_SET_POINT)
-				&& !high_bus_freq_mode) {
-				/* Currently at low or medium set point,
-				* need to set to high setpoint
-				*/
-				mutex_unlock(&bus_freq_mutex);
-				set_high_bus_freq(1);
-				return;
-			}
+		} else {
+			/* Update count */
+			if (clk->flags & AHB_HIGH_SET_POINT)
+				lp_high_freq++;
+			else if (clk->flags & AHB_MED_SET_POINT)
+				lp_med_freq++;
+			else if (clk->flags & AHB_AUDIO_SET_POINT)
+				lp_audio_freq++;
+			/* Update bus freq */
+			if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
+				&& (clk_get_usecount(clk) == 0)) {
+				if (!(clk->flags &
+					(AHB_HIGH_SET_POINT | AHB_MED_SET_POINT))) {
+					if (low_freq_bus_used()) {
+						if ((clk->flags & AHB_AUDIO_SET_POINT) &
+								!audio_bus_freq_mode)
+							set_low_bus_freq();
+						else if (!low_bus_freq_mode)
+							set_low_bus_freq();
+					}
+				} else {
+					if ((clk->flags & AHB_MED_SET_POINT)
+						&& !med_bus_freq_mode) {
+						/* Set to Medium setpoint */
+						set_high_bus_freq(0);
+					} else if ((clk->flags & AHB_HIGH_SET_POINT)
+						&& !high_bus_freq_mode) {
+						/* Currently at low or medium
+						  * set point, need to set to
+						  * high setpoint
+						  */
+						set_high_bus_freq(1);
+					}
+				}
 			}
 		}
 	} else {
-		/* Update count */
-		if (clk->flags & AHB_HIGH_SET_POINT)
-			lp_high_freq--;
-		else if (clk->flags & AHB_MED_SET_POINT)
-			lp_med_freq--;
-		else if (clk->flags & AHB_AUDIO_SET_POINT)
-			lp_audio_freq--;
-		/* Update bus freq */
-		if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
-			&& (clk_get_usecount(clk) == 0)) {
-			if (low_freq_bus_used() && !low_bus_freq_mode)
+		if (clk == cpu_clk) {
+			/* CPU freq is dropped, check if we can
+			  * lower the bus freq.
+			  */
+			high_cpu_freq = 0;
+
+			if (low_freq_bus_used() &&
+				!(low_bus_freq_mode || audio_bus_freq_mode))
 				set_low_bus_freq();
-			else {
-				/* Set to either high or medium setpoint. */
-				mutex_unlock(&bus_freq_mutex);
-				set_high_bus_freq(0);
-				return;
+		} else {
+			/* Update count */
+			if (clk->flags & AHB_HIGH_SET_POINT)
+				lp_high_freq--;
+			else if (clk->flags & AHB_MED_SET_POINT)
+				lp_med_freq--;
+			else if (clk->flags & AHB_AUDIO_SET_POINT)
+				lp_audio_freq--;
+			/* Update bus freq */
+			if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
+				&& (clk_get_usecount(clk) == 0)) {
+				if (low_freq_bus_used())
+					set_low_bus_freq();
+				else {
+					/* Set to either high or
+					  * medium setpoint.
+					  */
+					set_high_bus_freq(0);
+				}
 			}
 		}
 	}
@@ -436,7 +471,15 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev,
 				 const char *buf, size_t size)
 {
 	if (strncmp(buf, "1", 1) == 0) {
+#ifdef CONFIG_MX6_VPU_352M
+		if (cpu_is_mx6q())
+			/*do not enable bus freq*/
+			bus_freq_scaling_is_active = 0;
+		printk(KERN_WARNING "Bus frequency can't be enabled if using VPU 352M!\n");
+		return size;
+#else
 		bus_freq_scaling_is_active = 1;
+#endif
 		set_high_bus_freq(0);
 		/* Make sure system can enter low bus mode if it should be in
 		low bus mode */
@@ -458,6 +501,8 @@ static int busfreq_suspend(struct platform_device *pdev, pm_message_t message)
 static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
 	void *dummy)
 {
+	mutex_lock(&bus_freq_mutex);
+
 	if (event == PM_SUSPEND_PREPARE) {
 		set_high_bus_freq(1);
 		busfreq_suspended = 1;
@@ -465,6 +510,8 @@ static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
 		busfreq_suspended = 0;
 	}
 
+	mutex_unlock(&bus_freq_mutex);
+
 	return NOTIFY_OK;
 }
 static int busfreq_resume(struct platform_device *pdev)
@@ -486,6 +533,7 @@ static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
  * @return         The function returns 0 on success
  *
  */
+
 static int __devinit busfreq_probe(struct platform_device *pdev)
 {
 	u32 err;
@@ -513,6 +561,28 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(pll2);
 	}
 
+	pll1 = clk_get(NULL, "pll1_main_clk");
+	if (IS_ERR(pll1)) {
+		printk(KERN_DEBUG "%s: failed to get pll1\n",
+		       __func__);
+		return PTR_ERR(pll1);
+	}
+
+	pll1_sw_clk = clk_get(NULL, "pll1_sw_clk");
+	if (IS_ERR(pll1_sw_clk)) {
+		printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n",
+		       __func__);
+		return PTR_ERR(pll1_sw_clk);
+	}
+
+
+	if (IS_ERR(pll2)) {
+		printk(KERN_DEBUG "%s: failed to get pll2\n",
+		       __func__);
+		return PTR_ERR(pll2);
+	}
+
+
 	cpu_clk = clk_get(NULL, "cpu_clk");
 	if (IS_ERR(cpu_clk)) {
 		printk(KERN_DEBUG "%s: failed to get cpu_clk\n",
@@ -576,13 +646,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(mmdc_ch0_axi);
 	}
 
-	vddsoc_cap_regulator = regulator_get(NULL, "cpu_vddsoc");
-	if (IS_ERR(vddsoc_cap_regulator)) {
-		printk(KERN_ERR "%s: failed to get vddsoc_cap regulator\n",
-				__func__);
-		return PTR_ERR(vddsoc_cap_regulator);
-	}
-
 	err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
 	if (err) {
 		printk(KERN_ERR
@@ -598,6 +661,11 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		/* To make pll2_400 use count right, as when
 		system enter 24M, it will disable pll2_400 */
 		clk_enable(pll2_400);
+	} else if (cpu_is_mx6sl()) {
+		/* Set med_bus_freq_mode to 1 since med_bus_freq_mode
+		is not supported as yet for MX6SL */
+		high_bus_freq_mode = 1;
+		med_bus_freq_mode = 1;
 	} else {
 		high_bus_freq_mode = 1;
 		med_bus_freq_mode = 0;
@@ -620,6 +688,33 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 
 	if (!cpu_is_mx6sl())
 		init_mmdc_settings();
+	else {
+		unsigned long iram_paddr;
+
+		/* Allocate IRAM for WFI code when system is
+		  * in low freq mode.
+		  */
+		iram_alloc(SZ_4K, &iram_paddr);
+		/* Need to remap the area here since we want
+		   * the memory region to be executable.
+		   */
+		mx6sl_wfi_iram_base = __arm_ioremap(iram_paddr,
+						SZ_4K, MT_MEMORY_NONCACHED);
+		memcpy(mx6sl_wfi_iram_base, mx6sl_wait, SZ_4K);
+		mx6sl_wfi_iram = (void *)mx6sl_wfi_iram_base;
+
+		/* Allocate IRAM for WFI code when system is
+		  *in low freq mode.
+		  */
+		iram_alloc(SZ_4K, &iram_paddr);
+		/* Need to remap the area here since we want the memory region
+			 to be executable. */
+		mx6sl_ddr_freq_base = __arm_ioremap(iram_paddr,
+					SZ_4K, MT_MEMORY_NONCACHED);
+		memcpy(mx6sl_ddr_freq_base, mx6sl_ddr_iram, SZ_4K);
+		mx6sl_ddr_freq_change_iram = (void *)mx6sl_ddr_freq_base;
+
+	}
 
 	return 0;
 }
@@ -648,19 +743,19 @@ static int __init busfreq_init(void)
 
 	printk(KERN_INFO "Bus freq driver module loaded\n");
 
+#ifdef CONFIG_MX6_VPU_352M
+	if (cpu_is_mx6q())
+		bus_freq_scaling_is_active = 0;/*disable bus_freq*/
+
+#else
 	/* Enable busfreq by default. */
 	bus_freq_scaling_is_active = 1;
-
+#endif
 	if (cpu_is_mx6q())
 		set_high_bus_freq(1);
-	else
+	else if (cpu_is_mx6dl())
 		set_high_bus_freq(0);
 
-	/* Make sure system can enter low bus mode if it should be in
-	low bus mode */
-	if (low_freq_bus_used() && !low_bus_freq_mode)
-		set_low_bus_freq();
-
 	printk(KERN_INFO "Bus freq driver Enabled\n");
 	return 0;
 }
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 86587b5eb2e2..80781a6869ad 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -472,7 +472,6 @@ static int _clk_pll_enable(struct clk *clk)
 	pllbase = _get_pll_base(clk);
 
 	reg = __raw_readl(pllbase);
-	reg &= ~ANADIG_PLL_BYPASS;
 	reg &= ~ANADIG_PLL_POWER_DOWN;
 
 	/* The 480MHz PLLs have the opposite definition for power bit. */
@@ -492,6 +491,7 @@ static int _clk_pll_enable(struct clk *clk)
 
 	/* Enable the PLL output now*/
 	reg = __raw_readl(pllbase);
+	reg &= ~ANADIG_PLL_BYPASS;
 	reg |= ANADIG_PLL_ENABLE;
 	__raw_writel(reg, pllbase);
 
@@ -505,6 +505,15 @@ static void _clk_pll_disable(struct clk *clk)
 
 	if ((arm_needs_pll2_400) && (clk == &pll2_528_bus_main_clk))
 		return;
+	/*
+	 * To support USB remote wake up, need always keep power and enable bit
+	 * BM_ANADIG_ANA_MISC2_CONTROL0 will power off PLL3's power
+	 * Please see TKT064178 for detail.
+	 */
+	if (clk == &pll3_usb_otg_main_clk) {
+		__raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET);
+		return;
+	}
 
 	pllbase = _get_pll_base(clk);
 
@@ -514,12 +523,6 @@ static void _clk_pll_disable(struct clk *clk)
 
 	__raw_writel(reg, pllbase);
 
-	/*
-	 * It will power off PLL3's power, it is the TO1.1 fix
-	 * Please see TKT064178 for detail.
-	 */
-	if (clk == &pll3_usb_otg_main_clk)
-		__raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET);
 }
 
 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
@@ -1258,15 +1261,27 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 		  * PLL2_PFD_400M.
 		  */
 		if (pll1_sw_clk.parent != &pll2_pfd_400M) {
-			pll2_pfd_400M.enable(&pll2_pfd_400M);
+			if (pll2_pfd_400M.usecount == 0) {
+				/* Check if PLL2 needs to be enabled also. */
+				if (pll2_528_bus_main_clk.usecount == 0)
+					pll2_528_bus_main_clk.enable(&pll2_528_bus_main_clk);
+				/* Ensure parent usecount is
+				  * also incremented.
+				  */
+				pll2_528_bus_main_clk.usecount++;
+				pll2_pfd_400M.enable(&pll2_pfd_400M);
+			}
+			pll2_pfd_400M.usecount++;
 			arm_needs_pll2_400 = true;
 			pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
 			pll1_sw_clk.parent = &pll2_pfd_400M;
 		}
 	} else {
 		/* Make sure PLL1 is enabled */
-		if (!pll1_enabled)
+		if (!pll1_enabled) {
 			pll1_sys_main_clk.enable(&pll1_sys_main_clk);
+			pll1_sys_main_clk.usecount = 1;
+		}
 		/* Make sure PLL1 rate is what we want */
 		if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 			/* If pll1_sw_clk is from pll1_sys_main_clk, switch it */
@@ -1282,9 +1297,19 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 		/* Make sure pll1_sw_clk is from pll1_sys_main_clk */
 		pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 		pll1_sw_clk.parent = &pll1_sys_main_clk;
+		if (arm_needs_pll2_400) {
+			pll2_pfd_400M.usecount--;
+			if (pll2_pfd_400M.usecount == 0) {
+				pll2_pfd_400M.disable(&pll2_pfd_400M);
+				/* Ensure parent usecount is
+				  * also decremented.
+				  */
+				pll2_528_bus_main_clk.usecount--;
+				if (pll2_528_bus_main_clk.usecount == 0)
+					pll2_528_bus_main_clk.disable(&pll2_528_bus_main_clk);
+			}
+		}
 		arm_needs_pll2_400 = false;
-		if (pll2_pfd_400M.usecount == 0)
-			pll2_pfd_400M.disable(&pll2_pfd_400M);
 	}
 	parent_rate = clk_get_rate(clk->parent);
 	div = parent_rate / rate;
@@ -1320,8 +1345,10 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 	while (__raw_readl(MXC_CCM_CDHIPR))
 		;
 
-	if (pll1_sys_main_clk.usecount == 1 && arm_needs_pll2_400)
+	if (pll1_sys_main_clk.usecount == 1 && arm_needs_pll2_400) {
 		pll1_sys_main_clk.disable(&pll1_sys_main_clk);
+		pll1_sys_main_clk.usecount = 0;
+	}
 
 	spin_unlock_irqrestore(&clk_lock, flags);
 
@@ -5301,6 +5328,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 {
 	__iomem void *base;
 	int i, reg;
+	u32 parent_rate, rate;
+	unsigned long ipg_clk_rate, max_arm_wait_clk;
 
 	external_low_reference = ckil;
 	external_high_reference = ckih1;
@@ -5336,6 +5365,12 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 
 	clk_tree_init();
 
+#ifdef CONFIG_MX6_VPU_352M
+	if (cpu_is_mx6q()) {
+		clk_set_rate(&pll2_pfd_400M, 352000000);
+		clk_set_parent(&vpu_clk[0], &pll2_pfd_400M);
+	}
+#endif
 	/* keep correct count. */
 	clk_enable(&cpu_clk);
 	clk_enable(&periph_clk);
@@ -5504,6 +5539,20 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 	lp_med_freq = 0;
 	lp_audio_freq = 0;
 
+	/* Get current ARM_PODF value */
+	rate = clk_get_rate(&cpu_clk);
+	parent_rate = clk_get_rate(&pll1_sw_clk);
+	cur_arm_podf = parent_rate / rate;
+
+	/* Calculate the ARM_PODF to be applied when the system
+	  * enters WAIT state.
+	  * The max ARM clk is decided by the ipg_clk and has to
+	  * follow the ratio of ARM_CLK:IPG_CLK of 12:5.
+	  */
+	ipg_clk_rate = clk_get_rate(&ipg_clk);
+	max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
+	wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
+
 	/* Turn OFF all unnecessary PHYs. */
 	if (cpu_is_mx6q()) {
 		/* Turn off SATA PHY. */
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 3b2d9e527625..9742db4907f5 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -67,6 +67,7 @@ static struct clk pll7_usb_host_main_clk;
 static struct clk usdhc3_clk;
 static struct clk ipg_clk;
 static struct clk gpt_clk[];
+static struct clk ahb_clk;
 
 static struct cpu_op *cpu_op_tbl;
 static int cpu_op_nr;
@@ -100,7 +101,9 @@ DEFINE_SPINLOCK(mx6sl_clk_lock);
 	u32 gpt_ticks; \
 	u32 gpt_cnt; \
 	u32 reg; \
+	unsigned long flags; \
 	int result = 1; \
+	spin_lock_irqsave(&mx6sl_clk_lock, flags); \
 	gpt_rate = clk_get_rate(&gpt_clk[0]); \
 	gpt_ticks = timeout / (1000000000 / gpt_rate); \
 	reg = __raw_readl(timer_base + V2_TSTAT);\
@@ -130,6 +133,7 @@ DEFINE_SPINLOCK(mx6sl_clk_lock);
 			} \
 		} \
 	} \
+	spin_unlock_irqrestore(&mx6sl_clk_lock, flags); \
 	result; \
 })
 
@@ -409,6 +413,7 @@ static int _clk_pfd_enable(struct clk *clk)
 	__raw_writel((1 << (clk->enable_shift + 7)),
 			(int)clk->enable_reg + 8);
 
+	udelay(3);
 	return 0;
 }
 
@@ -427,7 +432,6 @@ static int _clk_pll_enable(struct clk *clk)
 	pllbase = _get_pll_base(clk);
 
 	reg = __raw_readl(pllbase);
-	reg &= ~ANADIG_PLL_BYPASS;
 	reg &= ~ANADIG_PLL_POWER_DOWN;
 
 	/* The 480MHz PLLs have the opposite definition for power bit. */
@@ -447,6 +451,7 @@ static int _clk_pll_enable(struct clk *clk)
 
 	/* Enable the PLL output now*/
 	reg = __raw_readl(pllbase);
+	reg &= ~ANADIG_PLL_BYPASS;
 	reg |= ANADIG_PLL_ENABLE;
 	__raw_writel(reg, pllbase);
 
@@ -466,7 +471,18 @@ static void _clk_pll_disable(struct clk *clk)
 
 	reg = __raw_readl(pllbase);
 	reg |= ANADIG_PLL_BYPASS;
-	reg &= ~ANADIG_PLL_ENABLE;
+	reg |= ANADIG_PLL_POWER_DOWN;
+
+	/* The 480MHz PLLs have the opposite definition for power bit. */
+	if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
+		reg &= ~ANADIG_PLL_POWER_DOWN;
+
+	/* PLL1, PLL2, PLL3, PLL7 should not disable the ENABLE bit.
+	  * The output of these PLLs maybe used even if they are bypassed.
+	  */
+	if (clk == &pll4_audio_main_clk || clk == &pll5_video_main_clk ||
+		clk == &pll6_enet_main_clk)
+		reg &= ~ANADIG_PLL_ENABLE;
 
 	__raw_writel(reg, pllbase);
 
@@ -505,7 +521,7 @@ static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 	/* Wait for PLL1 to lock */
 	if (!WAIT((__raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_LOCK),
 				SPIN_DELAY))
-		panic("pll1 enable failed\n");
+		panic("pll1 set rate failed\n");
 
 	return 0;
 }
@@ -531,8 +547,7 @@ static void _clk_pll1_main_disable(struct clk *clk)
 	  * requires PLL1 to be enabled.
 	  */
 	reg = __raw_readl(pllbase);
-	reg |= ANADIG_PLL_BYPASS;
-
+	reg |= (ANADIG_PLL_BYPASS | ANADIG_PLL_POWER_DOWN);
 	__raw_writel(reg, pllbase);
 }
 
@@ -1140,6 +1155,11 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 	if (i >= cpu_op_nr)
 		return -EINVAL;
 
+	if (clk_get_rate(&ahb_clk) == 24000000) {
+		printk(KERN_INFO "we should not be here!!!!! AHB is at 24MHz....cpu_rate requested = %ld\n", rate);
+		dump_stack();
+		BUG();
+	}
 	spin_lock_irqsave(&mx6sl_clk_lock, flags);
 
 	if (rate <= clk_get_rate(&pll2_pfd2_400M)) {
@@ -1147,15 +1167,27 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 		  * PLL2_PFD2_400M.
 		  */
 		if (pll1_sw_clk.parent != &pll2_pfd2_400M) {
-			pll2_pfd2_400M.enable(&pll2_pfd2_400M);
+			if (pll2_pfd2_400M.usecount == 0) {
+				/* Check if PLL2 needs to be enabled also. */
+				if (pll2_528_bus_main_clk.usecount == 0)
+					pll2_528_bus_main_clk.enable(&pll2_528_bus_main_clk);
+				/* Ensure parent usecount is
+				  * also incremented.
+				  */
+				pll2_528_bus_main_clk.usecount++;
+				pll2_pfd2_400M.enable(&pll2_pfd2_400M);
+			}
 			arm_needs_pll2_400 = true;
+			pll2_pfd2_400M.usecount++;
 			pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd2_400M);
 			pll1_sw_clk.parent = &pll2_pfd2_400M;
 		}
 	} else {
 		/* Make sure PLL1 is enabled */
-		if (!pll1_enabled)
+		if (!pll1_enabled) {
 			pll1_sys_main_clk.enable(&pll1_sys_main_clk);
+			pll1_sys_main_clk.usecount = 1;
+		}
 		if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 			if (pll1_sw_clk.parent == &pll1_sys_main_clk) {
 				/* Change the PLL1 rate. */
@@ -1173,9 +1205,20 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 		}
 		pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 		pll1_sw_clk.parent = &pll1_sys_main_clk;
+
+		if (arm_needs_pll2_400) {
+			pll2_pfd2_400M.usecount--;
+			if (pll2_pfd2_400M.usecount == 0) {
+				pll2_pfd2_400M.disable(&pll2_pfd2_400M);
+				/* Ensure parent usecount is
+				  * also decremented.
+				  */
+				pll2_528_bus_main_clk.usecount--;
+				if (pll2_528_bus_main_clk.usecount == 0)
+					pll2_528_bus_main_clk.disable(&pll2_528_bus_main_clk);
+			}
+		}
 		arm_needs_pll2_400 = false;
-		if (pll2_pfd2_400M.usecount == 0)
-			pll2_pfd2_400M.disable(&pll2_pfd2_400M);
 	}
 	parent_rate = clk_get_rate(clk->parent);
 	div = parent_rate / rate;
@@ -1211,8 +1254,10 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 	while (__raw_readl(MXC_CCM_CDHIPR))
 		;
 
-	if (pll1_sys_main_clk.usecount == 1 && arm_needs_pll2_400)
+	if (pll1_sys_main_clk.usecount == 1 && arm_needs_pll2_400) {
 		pll1_sys_main_clk.disable(&pll1_sys_main_clk);
+		pll1_sys_main_clk.usecount = 0;
+	}
 
 	spin_unlock_irqrestore(&mx6sl_clk_lock, flags);
 
@@ -1266,7 +1311,7 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 		reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 		reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 		__raw_writel(reg, MXC_CCM_CBCMR);
-
+		udelay(5);
 		/* Set the periph_clk_sel multiplexer. */
 		reg = __raw_readl(MXC_CCM_CBCDR);
 		reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
@@ -1433,6 +1478,7 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 	div = parent_rate / rate;
 	if (div == 0)
 		div++;
+
 	if (((parent_rate / div) != rate) || (div > 8))
 		return -EINVAL;
 
@@ -2080,6 +2126,7 @@ static struct clk usdhc1_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc1_set_rate,
 	.get_rate = _clk_usdhc1_get_rate,
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
@@ -2137,6 +2184,7 @@ static struct clk usdhc2_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc2_set_rate,
 	.get_rate = _clk_usdhc2_get_rate,
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
@@ -2195,6 +2243,7 @@ static struct clk usdhc3_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc3_set_rate,
 	.get_rate = _clk_usdhc3_get_rate,
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
@@ -2253,6 +2302,7 @@ static struct clk usdhc4_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc4_set_rate,
 	.get_rate = _clk_usdhc4_get_rate,
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi_round_rate(struct clk *clk,
@@ -2424,7 +2474,7 @@ static struct clk ssi1_clk = {
 #else
 	 .secondary = &mmdc_ch1_axi_clk[0],
 #endif
-	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags  = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
@@ -2498,7 +2548,7 @@ static struct clk ssi2_clk = {
 #else
 	 .secondary = &mmdc_ch1_axi_clk[0],
 #endif
-	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags  = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
@@ -2571,7 +2621,7 @@ static struct clk ssi3_clk = {
 #else
 	 .secondary = &mmdc_ch1_axi_clk[0],
 #endif
-	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags  = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_epdc_lcdif_pix_round_rate(struct clk *clk,
@@ -2908,7 +2958,7 @@ static struct clk lcdif_pix_clk = {
 	.set_rate = _clk_lcdif_pix_set_rate,
 	.round_rate = _clk_epdc_lcdif_pix_round_rate,
 	.get_rate = _clk_lcdif_pix_get_rate,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static struct clk epdc_pix_clk = {
@@ -2923,7 +2973,7 @@ static struct clk epdc_pix_clk = {
 	.set_rate = _clk_epdc_pix_set_rate,
 	.round_rate = _clk_epdc_lcdif_pix_round_rate,
 	.get_rate = _clk_epdc_pix_get_rate,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 static unsigned long _clk_spdif_round_rate(struct clk *clk,
 						unsigned long rate)
@@ -3321,6 +3371,10 @@ static unsigned long _clk_uart_get_rate(struct clk *clk)
 	div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
 	val = clk_get_rate(clk->parent) / div;
 
+	/* If the parent is OSC, there is an in-built divide by 6. */
+	if (clk->parent == &osc_clk)
+		val = val / 6;
+
 	return val;
 }
 
@@ -3335,7 +3389,7 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
 	else
 		mux = 0; /* osc */
 
-	reg |= mux << MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET;
+	reg |= mux << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET;
 
 	__raw_writel(reg, MXC_CCM_CSCDR1);
 
@@ -3960,6 +4014,8 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 	unsigned long ckih1, unsigned long ckih2)
 {
 	int i;
+	u32 parent_rate, rate;
+	unsigned long ipg_clk_rate, max_arm_wait_clk;
 
 	external_low_reference = ckil;
 	external_high_reference = ckih1;
@@ -3978,6 +4034,12 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 	 * should be from OSC24M */
 	clk_set_parent(&ipg_perclk, &osc_clk);
 
+	/* Need to set IPG_PERCLK to 3MHz, so that we can
+	  * satisfy the 2.5:1 AHB:IPG_PERCLK ratio. Since AHB
+	  * can be dropped to as low as 8MHz in low power mode.
+	  */
+	clk_set_rate(&ipg_perclk, 3000000);
+
 	gpt_clk[0].parent = &ipg_perclk;
 	gpt_clk[0].get_rate = NULL;
 
@@ -4024,7 +4086,6 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 			     3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
 	} else {
 		__raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
-			     3 << MXC_CCM_CCGRx_CG2_OFFSET |
 			     3 << MXC_CCM_CCGRx_CG1_OFFSET |
 			     3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
 	}
@@ -4032,9 +4093,9 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 		     3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR1);
 	__raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
 		     1 << MXC_CCM_CCGRx_CG11_OFFSET |
-		     3 << MXC_CCM_CCGRx_CG10_OFFSET |
-		     3 << MXC_CCM_CCGRx_CG9_OFFSET |
-		     3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
+		     1 << MXC_CCM_CCGRx_CG10_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG9_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
 	__raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
 		     3 << MXC_CCM_CCGRx_CG13_OFFSET |
 		     3 << MXC_CCM_CCGRx_CG12_OFFSET |
@@ -4067,6 +4128,20 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 	lp_high_freq = 0;
 	lp_med_freq = 0;
 
+	/* Get current ARM_PODF value */
+	rate = clk_get_rate(&cpu_clk);
+	parent_rate = clk_get_rate(&pll1_sw_clk);
+	cur_arm_podf = parent_rate / rate;
+
+	/* Calculate the ARM_PODF to be applied when the system
+	  * enters WAIT state.
+	  * The max ARM clk is decided by the ipg_clk and has to
+	  * follow the ratio of ARM_CLK:IPG_CLK of 12:5.
+	  */
+	ipg_clk_rate = clk_get_rate(&ipg_clk);
+	max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
+	wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
+
 	return 0;
 
 }
diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
index b8d06e2ad09a..7e054c1d743c 100644
--- a/arch/arm/mach-mx6/cpu_op-mx6.c
+++ b/arch/arm/mach-mx6/cpu_op-mx6.c
@@ -24,70 +24,127 @@ extern u32 arm_max_freq;
 static int num_cpu_op;
 
 /* working point(wp): 0 - 1.2GHz; 1 - 792MHz, 2 - 498MHz 3 - 396MHz */
-static struct cpu_op mx6_cpu_op_1_2G[] = {
+static struct cpu_op mx6q_cpu_op_1_2G[] = {
 	{
 	 .pll_rate = 1200000000,
 	 .cpu_rate = 1200000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1250000,
-	 .soc_voltage = 1250000,
+	 .pu_voltage = 1275000,
+	 .soc_voltage = 1275000,
 	 .cpu_voltage = 1275000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1150000,
-	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1100000,},
+#ifdef CONFIG_MX6_VPU_352M
+	/*VPU 352Mhz need voltage 1.25V*/
+	.pu_voltage = 1250000,
+	.soc_voltage = 1250000,
+#else
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+#endif
+	 .cpu_voltage = 1150000,},
+#ifdef CONFIG_MX6_VPU_352M
+	/*pll2_pfd_400M will be fix on 352M,to avoid modify other code
+	which assume ARM clock sourcing from pll2_pfd_400M, change cpu
+	freq from 396M to 352M.*/
+	 {
+	  .pll_rate = 352000000,
+	  .cpu_rate = 352000000,
+	  .cpu_podf = 0,
+	  .pu_voltage = 1250000,
+	  .soc_voltage = 1250000,
+	  .cpu_voltage = 950000,},
+#else
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .pu_voltage = 1150000,
-	  .soc_voltage = 1150000,
-	  .cpu_voltage = 925000,},
+	  .pu_voltage = 1175000,
+	  .soc_voltage = 1175000,
+	  .cpu_voltage = 950000,},
+#endif
 };
 
 /* working point(wp): 0 - 1GHz; 1 - 792MHz, 2 - 498MHz 3 - 396MHz */
-static struct cpu_op mx6_cpu_op_1G[] = {
+static struct cpu_op mx6q_cpu_op_1G[] = {
 	{
 	 .pll_rate = 996000000,
 	 .cpu_rate = 996000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1200000,
-	 .soc_voltage = 1200000,
-	 .cpu_voltage = 1225000,},
+	 .pu_voltage = 1250000,
+	 .soc_voltage = 1250000,
+	 .cpu_voltage = 1250000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1150000,
-	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1100000,},
+#ifdef CONFIG_MX6_VPU_352M
+	/*VPU 352Mhz need voltage 1.25V*/
+	 .pu_voltage = 1250000,
+	 .soc_voltage = 1250000,
+#else
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+#endif
+	 .cpu_voltage = 1150000,},
+#ifdef CONFIG_MX6_VPU_352M
+	/*pll2_pfd_400M will be fix on 352M,to avoid modify other code
+	which assume ARM clock sourcing from pll2_pfd_400M, change cpu
+	freq from 396M to 352M.*/
+	 {
+	  .pll_rate = 352000000,
+	  .cpu_rate = 352000000,
+	  .cpu_podf = 0,
+	  .pu_voltage = 1250000,
+	  .soc_voltage = 1250000,
+	  .cpu_voltage = 950000,},
+#else
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .pu_voltage = 1150000,
-	  .soc_voltage = 1150000,
-	  .cpu_voltage = 925000,},
+	  .pu_voltage = 1175000,
+	  .soc_voltage = 1175000,
+	  .cpu_voltage = 950000,},
+#endif
 };
 
-static struct cpu_op mx6_cpu_op[] = {
+static struct cpu_op mx6q_cpu_op[] = {
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1150000,
-	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1100000,},
+#ifdef CONFIG_MX6_VPU_352M
+	/*VPU 352Mhz need voltage 1.25V*/
+	 .pu_voltage = 1250000,
+	 .soc_voltage = 1250000,
+#else
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+#endif
+	 .cpu_voltage = 1150000,},
+#ifdef CONFIG_MX6_VPU_352M
+	/*pll2_pfd_400M will be fix on 352M,to avoid modify other code
+	which assume ARM clock sourcing from pll2_pfd_400M, change cpu
+	freq from 396M to 352M.*/
+	 {
+	  .pll_rate = 352000000,
+	  .cpu_rate = 352000000,
+	  .cpu_podf = 0,
+	  .pu_voltage = 1250000,
+	  .soc_voltage = 1250000,
+	  .cpu_voltage = 950000,},
+#else
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .pu_voltage = 1150000,
-	  .soc_voltage = 1150000,
-	  .cpu_voltage = 925000,},
+	  .pu_voltage = 1175000,
+	  .soc_voltage = 1175000,
+	  .cpu_voltage = 950000,},
+#endif
 };
 
 /* working point(wp): 0 - 1.2GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
@@ -96,23 +153,23 @@ static struct cpu_op mx6dl_cpu_op_1_2G[] = {
 	 .pll_rate = 1200000000,
 	 .cpu_rate = 1200000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1250000,
-	 .soc_voltage = 1250000,
+	 .pu_voltage = 1275000,
+	 .soc_voltage = 1275000,
 	 .cpu_voltage = 1275000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1150000,
-	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1100000,},
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+	 .cpu_voltage = 1150000,},
 	 {
 	  .pll_rate = 396000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .pu_voltage = 1150000,
-	  .soc_voltage = 1150000,
-	  .cpu_voltage = 1025000,},
+	  .pu_voltage = 1175000,
+	  .soc_voltage = 1175000,
+	  .cpu_voltage = 1075000,},
 };
 /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
 static struct cpu_op mx6dl_cpu_op_1G[] = {
@@ -120,39 +177,98 @@ static struct cpu_op mx6dl_cpu_op_1G[] = {
 	 .pll_rate = 996000000,
 	 .cpu_rate = 996000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1200000,
-	 .soc_voltage = 1200000,
-	 .cpu_voltage = 1225000,},
+	 .pu_voltage = 1250000,
+	 .soc_voltage = 1250000,
+	 .cpu_voltage = 1250000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1150000,
-	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1100000,},
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+	 .cpu_voltage = 1150000,},
 	{
 	 .pll_rate = 396000000,
 	 .cpu_rate = 396000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1150000,
-	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1025000,},
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+	 .cpu_voltage = 1075000,},
 };
 static struct cpu_op mx6dl_cpu_op[] = {
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
+	 .pu_voltage = 1175000,
+	 .soc_voltage = 1175000,
+	 .cpu_voltage = 1150000,},
+	 {
+	  .pll_rate = 396000000,
+	  .cpu_rate = 396000000,
+	  .cpu_podf = 0,
+	  .pu_voltage = 1175000,
+	  .soc_voltage = 1175000,
+	  .cpu_voltage = 1075000,},
+};
+
+static struct cpu_op mx6sl_cpu_op_1G[] = {
+	{
+	 .pll_rate = 996000000,
+	 .cpu_rate = 996000000,
+	 .cpu_podf = 0,
+	 .pu_voltage = 1225000,
+	 .soc_voltage = 1225000,
+	 .cpu_voltage = 1275000,},
+	{
+	 .pll_rate = 792000000,
+	 .cpu_rate = 792000000,
+	 .cpu_podf = 0,
 	 .pu_voltage = 1150000,
 	 .soc_voltage = 1150000,
+	 .cpu_voltage = 1200000,},
+	{
+	 .pll_rate = 396000000,
+	 .pll_lpm_rate = 792000000,
+	 .cpu_rate = 396000000,
+	 .cpu_podf = 0,
+	 .pu_voltage = 1050000,
+	 .soc_voltage = 1050000,
 	 .cpu_voltage = 1100000,},
 	 {
 	  .pll_rate = 396000000,
+	 .pll_lpm_rate = 792000000,
+	  .cpu_rate = 198000000,
+	  .cpu_podf = 1,
+	  .pu_voltage = 1050000,
+	  .soc_voltage = 1050000,
+	  .cpu_voltage = 1050000,},
+};
+
+static struct cpu_op mx6sl_cpu_op[] = {
+	{
+	 .pll_rate = 792000000,
+	 .cpu_rate = 792000000,
+	 .cpu_podf = 0,
+	 .pu_voltage = 1150000,
+	 .soc_voltage = 1150000,
+	 .cpu_voltage = 1200000,},
+	 {
+	  .pll_rate = 396000000,
+	 .pll_lpm_rate = 792000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	  .pu_voltage = 1150000,
-	  .soc_voltage = 1150000,
-	  .cpu_voltage = 1025000,},
+	 .pu_voltage = 1050000,
+	 .soc_voltage = 1050000,
+	 .cpu_voltage = 1100000,},
+	{
+	 .pll_rate = 396000000,
+	 .pll_lpm_rate = 792000000,
+	 .cpu_rate = 198000000,
+	 .cpu_podf = 1,
+	  .pu_voltage = 1050000,
+	  .soc_voltage = 1050000,
+	  .cpu_voltage = 1050000,},
 };
 
 static struct dvfs_op dvfs_core_setpoint_1_2G[] = {
@@ -201,16 +317,24 @@ struct cpu_op *mx6_get_cpu_op(int *op)
 			*op =  num_cpu_op = ARRAY_SIZE(mx6dl_cpu_op);
 			return mx6dl_cpu_op;
 		}
-	} else {
+	} else if (cpu_is_mx6q()) {
 		if (arm_max_freq == CPU_AT_1_2GHz) {
-			*op =  num_cpu_op = ARRAY_SIZE(mx6_cpu_op_1_2G);
-			return mx6_cpu_op_1_2G;
+			*op =  num_cpu_op = ARRAY_SIZE(mx6q_cpu_op_1_2G);
+			return mx6q_cpu_op_1_2G;
 		} else if (arm_max_freq == CPU_AT_1GHz) {
-			*op =  num_cpu_op = ARRAY_SIZE(mx6_cpu_op_1G);
-			return mx6_cpu_op_1G;
+			*op =  num_cpu_op = ARRAY_SIZE(mx6q_cpu_op_1G);
+			return mx6q_cpu_op_1G;
+		} else {
+			*op =  num_cpu_op = ARRAY_SIZE(mx6q_cpu_op);
+			return mx6q_cpu_op;
+		}
+	} else {
+		if (arm_max_freq == CPU_AT_1GHz) {
+			*op =  num_cpu_op = ARRAY_SIZE(mx6sl_cpu_op_1G);
+			return mx6sl_cpu_op_1G;
 		} else {
-			*op =  num_cpu_op = ARRAY_SIZE(mx6_cpu_op);
-			return mx6_cpu_op;
+			*op =  num_cpu_op = ARRAY_SIZE(mx6sl_cpu_op);
+			return mx6sl_cpu_op;
 		}
 	}
 }
diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index 105e1f6d0a0e..bd948cecbcd2 100644
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -158,10 +158,6 @@ extern const struct imx_imx_asrc_data imx6q_imx_asrc_data[] __initconst;
 #define imx6q_add_asrc(pdata)	\
 	imx_add_imx_asrc(imx6q_imx_asrc_data, pdata)
 
-extern const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst;
-#define imx6q_add_ecspi(id, pdata)      \
-	imx_add_spi_imx(&imx6q_ecspi_data[id], pdata)
-
 extern const struct imx_dvfs_core_data imx6q_dvfs_core_data __initconst;
 #define imx6q_add_dvfs_core(pdata)	\
 	imx_add_dvfs_core(&imx6q_dvfs_core_data, pdata)
@@ -220,6 +216,9 @@ extern const struct imx_pxp_data imx6dl_pxp_data __initconst;
 #define imx6dl_add_imx_pxp_client()   \
 	imx_add_imx_pxp_client()
 
+#define imx6sl_add_imx_pxp_v4l2()   \
+	imx_add_imx_pxp_v4l2()
+
 extern const struct imx_epdc_data imx6dl_epdc_data __initconst;
 #define imx6dl_add_imx_epdc(pdata)	\
 	imx_add_imx_epdc(&imx6dl_epdc_data, pdata)
diff --git a/arch/arm/mach-mx6/irq.c b/arch/arm/mach-mx6/irq.c
index 5131eae3a040..0498cd90e8e8 100644
--- a/arch/arm/mach-mx6/irq.c
+++ b/arch/arm/mach-mx6/irq.c
@@ -65,6 +65,14 @@ static struct irq_tuner mxc_irq_tuner[] = {
 	 .up_threshold = 0,
 	 .enable = 0,},
 	{
+	 .irq_number = 42, /* GPU 2D */
+	 .up_threshold = 40,
+	 .enable = 1,},
+	{
+	 .irq_number = 43, /* GPU VG */
+	 .up_threshold = 0,
+	 .enable = 1,},
+	{
 	 .irq_number = 54, /* uSDHC1 */
 	 .up_threshold = 4,
 	 .enable = 1,},
@@ -103,6 +111,7 @@ void mx6_init_irq(void)
 	void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
 	struct irq_desc *desc;
 	unsigned int i;
+	u32 reg;
 
 	/* start offset if private timer irq id, which is 29.
 	 * ID table:
@@ -121,6 +130,13 @@ void mx6_init_irq(void)
 		__raw_writel(0x20000000, gpc_base + 0x10);
 	}
 
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	/* Mask the ANATOP brown out interrupt in the GPC. */
+	reg = __raw_readl(gpc_base + 0x14);
+	reg |= 0x80000000;
+	__raw_writel(reg, gpc_base + 0x14);
+#endif
+
 	for (i = MXC_INT_START; i <= MXC_INT_END; i++) {
 		desc = irq_to_desc(i);
 		desc->irq_data.chip->irq_set_wake = mx6_gic_irq_set_wake;
diff --git a/arch/arm/mach-mx6/mx6_anatop_regulator.c b/arch/arm/mach-mx6/mx6_anatop_regulator.c
index 06755dc7a4ee..945adbdb759a 100644
--- a/arch/arm/mach-mx6/mx6_anatop_regulator.c
+++ b/arch/arm/mach-mx6/mx6_anatop_regulator.c
@@ -125,10 +125,12 @@ static int pu_enable(struct anatop_regulator *sreg)
 	reg |= ANADIG_ANA_MISC2_REG1_BO_EN;
 	__raw_writel(reg, ANA_MISC2_BASE_ADDR);
 
+#ifndef CONFIG_MX6_INTER_LDO_BYPASS
 	/* Unmask the ANATOP brown out interrupt in the GPC. */
 	reg = __raw_readl(gpc_base + 0x14);
 	reg &= ~0x80000000;
 	__raw_writel(reg, gpc_base + 0x14);
+#endif
 
 	return 0;
 }
@@ -162,10 +164,12 @@ static int pu_disable(struct anatop_regulator *sreg)
 	while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
 			;
 
+#ifndef CONFIG_MX6_INTER_LDO_BYPASS
 	/* Mask the ANATOP brown out interrupt in the GPC. */
 	reg = __raw_readl(gpc_base + 0x14);
 	reg |= 0x80000000;
 	__raw_writel(reg, gpc_base + 0x14);
+#endif
 
 	/* PU power gating. */
 	reg = __raw_readl(ANADIG_REG_CORE);
diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S
index 59b676038427..a9b7e30cd85a 100644
--- a/arch/arm/mach-mx6/mx6_suspend.S
+++ b/arch/arm/mach-mx6/mx6_suspend.S
@@ -85,8 +85,7 @@ r2: suspend_iram_base
 	ldr	r4, [r1, #0x330] /* DRAM_SDCKE0 */
 	ldr	r5, [r1, #0x334] /* DRAM_SDCKE1 */
 	ldr	r6, [r1, #0x320] /* DRAM_RESET */
-	ldr	r7, [r1, #0x5c8] /* GPR_CTLDS */
-	stmfd	r0!, {r4-r7}
+	stmfd	r0!, {r4-r6}
 
 	.endm
 
@@ -122,11 +121,10 @@ r2: suspend_iram_base
 	str	r6, [r1, #0x33c] /* DRAM_SODT0*/
 	str	r7, [r1, #0x340] /* DRAM_SODT1*/
 
-	ldmea	r0!, {r4-r7}
+	ldmea	r0!, {r4-r6}
 	str	r4, [r1, #0x330] /* DRAM_SDCKE0 */
 	str	r5, [r1, #0x334] /* DRAM_SDCKE1 */
 	str	r6, [r1, #0x320] /* DRAM_RESET */
-	str	r7, [r1, #0x5c8] /* GPR_CTLDS */
 
 	.endm
 
@@ -138,6 +136,13 @@ r2: suspend_iram_base
 	str	r0, [r1, #0x314] /* DRAM_DQM2 */
 	str	r0, [r1, #0x318] /* DRAM_DQM3 */
 
+	/* Make sure the Pull Ups are enabled.
+	 * So only reduce the drive stength, but
+	 * leave the pull-ups in the original state.
+	 * This is required for LPDDR2.
+	 */
+	ldr	r0, [r1, #0x344]
+	orr	r0, r0, #0x3000
 	str	r0, [r1, #0x344] /* DRAM_SDQS0 */
 	str	r0, [r1, #0x348] /* DRAM_SDQS1 */
 	str	r0, [r1, #0x34c] /* DRAM_SDQS2 */
@@ -158,7 +163,6 @@ r2: suspend_iram_base
 	str	r0, [r1, #0x33c] /* DRAM_SODT0*/
 	str	r0, [r1, #0x340] /* DRAM_SODT1*/
 
-	str	r0, [r1, #0x5c8] /* GPR_CTLDS */
 	mov	r0, #0x80000
 	str	r0, [r1, #0x320] /* DRAM_RESET */
 	mov	r0, #0x1000
diff --git a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
index cc12a0224ab2..8cb4ffcc78fa 100644
--- a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
@@ -41,13 +41,13 @@
 
  /*SWBST*/
 #define PFUZE100_SW1ASTANDBY    33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x18)
+#define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x19)
 #define PFUZE100_SW1ASTANDBY_STBY_M     (0x3f<<0)
 #define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x18)
+#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
 #define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
 #define PFUZE100_SW1CSTANDBY    47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x18)
+#define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x19)
 #define PFUZE100_SW1CSTANDBY_STBY_M     (0x3f<<0)
 #define PFUZE100_SW2STANDBY     54
 #define PFUZE100_SW2STANDBY_STBY_VAL    0x0
diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
index f7e7099468c1..69daddf14000 100644
--- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
@@ -48,13 +48,13 @@
 #define PFUZE100_SW1CVOL	46
 #define PFUZE100_SW1CVOL_VSEL_M	(0x3f<<0)
 #define PFUZE100_SW1ASTANDBY	33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL	(0x18)
+#define PFUZE100_SW1ASTANDBY_STBY_VAL	(0x19)
 #define PFUZE100_SW1ASTANDBY_STBY_M	(0x3f<<0)
 #define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x18)
+#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
 #define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
 #define PFUZE100_SW1CSTANDBY	47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL	(0x18)
+#define PFUZE100_SW1CSTANDBY_STBY_VAL	(0x19)
 #define PFUZE100_SW1CSTANDBY_STBY_M	(0x3f<<0)
 #define PFUZE100_SW2STANDBY     54
 #define PFUZE100_SW2STANDBY_STBY_VAL    0x0
@@ -74,6 +74,9 @@
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
 
 extern u32 arm_max_freq;
 
@@ -83,6 +86,11 @@ static struct regulator_consumer_supply sw1_consumers[] = {
 		.supply	   = "VDDCORE",
 	}
 };
+static struct regulator_consumer_supply sw1c_consumers[] = {
+	{
+		.supply	   = "VDDSOC",
+	},
+};
 #endif
 
 static struct regulator_consumer_supply sw2_consumers[] = {
@@ -160,10 +168,10 @@ static struct regulator_init_data sw1a_init = {
 			.always_on = 1,
 			},
 
-	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
-	#endif
+#endif
 };
 
 static struct regulator_init_data sw1b_init = {
@@ -188,6 +196,10 @@ static struct regulator_init_data sw1c_init = {
 			.always_on = 1,
 			.boot_on = 1,
 			},
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
+	.consumer_supplies = sw1c_consumers,
+#endif
 };
 
 static struct regulator_init_data sw2_init = {
@@ -421,12 +433,17 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 			    PFUZE100_SW1CSTANDBY_STBY_VAL);
 	if (ret)
 		goto err;
-	/*set SW1ABDVSPEED as 25mV step each 4us,quick than 16us before.*/
+	/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
 	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
 			    PFUZE100_SW1ACON_SPEED_M,
 			    PFUZE100_SW1ACON_SPEED_VAL);
 	if (ret)
 		goto err;
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+			    PFUZE100_SW1CCON_SPEED_M,
+			    PFUZE100_SW1CCON_SPEED_VAL);
+	if (ret)
+		goto err;
 	return 0;
 err:
 	printk(KERN_ERR "pfuze100 init error!\n");
diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
index 0c3f1b20d361..134700a6d200 100644
--- a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
@@ -66,6 +66,9 @@
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
 
 
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
@@ -74,6 +77,11 @@ static struct regulator_consumer_supply sw1_consumers[] = {
 		.supply	   = "VDDCORE",
 	}
 };
+static struct regulator_consumer_supply sw1c_consumers[] = {
+	{
+		.supply	   = "VDDSOC",
+	},
+};
 #endif
 
 static struct regulator_consumer_supply sw2_consumers[] = {
@@ -151,10 +159,10 @@ static struct regulator_init_data sw1a_init = {
 			.boot_on = 1,
 			.always_on = 1,
 			},
-	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
-	#endif
+#endif
 };
 
 static struct regulator_init_data sw1b_init = {
@@ -179,6 +187,10 @@ static struct regulator_init_data sw1c_init = {
 			.always_on = 1,
 			.boot_on = 1,
 			},
+	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
+	.consumer_supplies = sw1c_consumers,
+	#endif
 };
 
 static struct regulator_init_data sw2_init = {
@@ -298,8 +310,8 @@ static struct regulator_init_data vgen1_init = {
 			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 			REGULATOR_CHANGE_STATUS,
 			.valid_modes_mask = 0,
-			.always_on = 0,
-			.boot_on = 0,
+			.always_on = 1,
+			.boot_on = 1,
 			},
 	.num_consumer_supplies = ARRAY_SIZE(vgen1_consumers),
 	.consumer_supplies = vgen1_consumers,
@@ -345,6 +357,8 @@ static struct regulator_init_data vgen4_init = {
 			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 			REGULATOR_CHANGE_STATUS,
 			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
 			},
 	.num_consumer_supplies = ARRAY_SIZE(vgen4_consumers),
 	.consumer_supplies = vgen4_consumers,
@@ -389,12 +403,17 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 			    PFUZE100_SW1CSTANDBY_STBY_VAL);
 	if (ret)
 		goto err;
-	/*set SW1ABDVSPEED as 25mV step each 4us,quick than 16us before.*/
+	/*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
 	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
 			    PFUZE100_SW1ACON_SPEED_M,
 			    PFUZE100_SW1ACON_SPEED_VAL);
 	if (ret)
 		goto err;
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+			    PFUZE100_SW1CCON_SPEED_M,
+			    PFUZE100_SW1CCON_SPEED_VAL);
+	if (ret)
+		goto err;
 	return 0;
 err:
 	printk(KERN_ERR "pfuze100 init error!\n");
diff --git a/arch/arm/mach-mx6/mx6sl_ddr.S b/arch/arm/mach-mx6/mx6sl_ddr.S
new file mode 100644
index 000000000000..3059f3aa3c8c
--- /dev/null
+++ b/arch/arm/mach-mx6/mx6sl_ddr.S
@@ -0,0 +1,432 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/linkage.h>
+#include <mach/hardware.h>
+
+
+	 .macro    mx6sl_switch_to_24MHz
+
+      /* Set MMDC clock to be sourced from PLL3. */
+      /* Ensure first periph2_clk2 is sourced from PLL3. */
+      /* Set the PERIPH2_CLK2_PODF to divide by 2. */
+     ldr    r6, [r2, #0x14]
+     bic    r6, r6, #0x7
+     orr    r6, r6, #0x1
+     str     r6, [r2, #0x14]
+
+     /* Select PLL3 to source MMDC. */
+     ldr    r6, [r2, #0x18]
+     bic    r6, r6, #0x100000
+     str    r6, [r2, #0x18]
+
+     /* Swtich periph2_clk_sel to run from PLL3. */
+      ldr     r6, [r2, #0x14]
+      orr     r6, r6, #0x4000000
+      str     r6, [r2, #0x14]
+
+periph2_clk_switch1:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     periph2_clk_switch1
+
+    /* Need to clock gate the 528 PFDs before
+      * powering down PLL2.
+      * Only the PLL2_PFD2_400M should be ON
+      * as it feeds the MMDC
+      */
+     ldr     r6, [r3, #0x100]
+     orr    r6, r6, #0x800000
+     str     r6, [r3, #0x100]
+
+    /* Set PLL2 to bypass state. We should be here
+      *only if MMDC is not sourced from PLL2.*/
+     ldr    r6, [r3, #0x30]
+     orr    r6, r6, #0x10000
+     str     r6, [r3, #0x30]
+
+     ldr    r6, [r3, #0x30]
+     orr    r6, r6, #0x1000
+     str     r6, [r3, #0x30]
+
+    /* Ensure pre_periph2_clk_mux is set to pll2 */
+     ldr     r6, [r2, #0x18]
+     bic     r6, r6, #0x600000
+     str     r6, [r2, #0x18]
+
+     /* Set MMDC clock to be sourced from the bypassed PLL2. */
+     ldr    r6, [r2, #0x14]
+     bic    r6, r6, #0x4000000
+     str    r6, [r2, #0x14]
+
+periph2_clk_switch2:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     periph2_clk_switch2
+
+    /* Now move MMDC back to periph2_clk2 source.
+      * after selecting PLL2 as the option.
+      */
+     /* Select PLL2 as the source. */
+     ldr    r6, [r2, #0x18]
+     orr    r6, r6, #0x100000
+     str    r6, [r2, #0x18]
+
+    /* set periph2_clk2_podf to divide by 1. */
+     ldr    r6, [r2, #0x14]
+     bic    r6, r6, #0x7
+     str     r6, [r2, #0x14]
+
+     /* Now move periph2_clk to periph2_clk2 source */
+     ldr    r6, [r2, #0x14]
+     orr    r6, r6, #0x4000000
+     str    r6, [r2, #0x14]
+
+periph2_clk_switch3:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     periph2_clk_switch3
+
+     /* Now set the MMDC PODF back to 1.*/
+      ldr    r6, [r2, #0x14]
+      bic    r6, r6, #0x38
+      str    r6, [r2, #0x14]
+
+mmdc_podf0:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     mmdc_podf0
+
+	.endm
+
+	  .macro	ddr_switch_400MHz
+
+     /* Check if we are switching between
+       * 400Mhz <-> 50MHz. If so, we only need to
+       * update MMDC divider.
+       */
+      cmp    r1, #0
+      beq     change_divider_only
+
+    /* Set MMDC divider first, in case PLL3 is at 480MHz. */
+      ldr     r6, [r3, #0x10]
+      and    r6, r6, #0x10000
+      cmp   r6, #0x10000
+      beq    pll3_in_bypass
+      /* Set MMDC divder to divide by 2. */
+      ldr    r6, [r2, #0x14]
+      bic    r6, r6, #0x38
+      orr    r6, r6, #0x8
+      str    r6, [r2, #0x14]
+
+mmdc_podf:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     mmdc_podf
+
+pll3_in_bypass:
+
+     /* Ensure that MMDC is sourced from PLL2 mux first. */
+     ldr     r6, [r2, #0x14]
+     bic     r6, r6, #0x4000000
+     str     r6, [r2, #0x14]
+
+periph2_clk_switch4:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     periph2_clk_switch4
+
+     /* Now ensure periph2_clk2_sel mux is set to PLL3 */
+     ldr     r6, [r2, #0x18]
+     bic     r6, r6, #0x100000
+     str     r6, [r2, #0x18]
+
+      /* Now switch MMDC to PLL3. */
+     ldr     r6, [r2, #0x14]
+     orr     r6, r6, #0x4000000
+     str     r6, [r2, #0x14]
+
+periph2_clk_switch5:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     periph2_clk_switch5
+
+     /* Now power up PLL2 and unbypass it. */
+     ldr    r6, [r3, #0x30]
+     bic    r6, r6, #0x1000
+     str     r6, [r3, #0x30]
+
+     /* Make sure PLL2 has locked.*/
+wait_for_pll_lock:
+     ldr    r6, [r3, #0x30]
+     and   r6, r6, #0x80000000
+     cmp  r6, #0x80000000
+     bne   wait_for_pll_lock
+
+      ldr    r6, [r3, #0x30]
+     bic    r6, r6, #0x10000
+     str     r6, [r3, #0x30]
+
+    /* Need to enable the 528 PFDs after
+      * powering up PLL2.
+      * Only the PLL2_PFD2_400M should be ON
+      * as it feeds the MMDC. Rest should have
+      * been managed by clock code.
+      */
+     ldr     r6, [r3, #0x100]
+     bic    r6, r6, #0x800000
+     str     r6, [r3, #0x100]
+
+    /* Now switch MMDC clk back to pll2_mux option. */
+    /* Ensure pre_periph2_clk2 is set to pll2_pfd_400M */
+     ldr     r6, [r2, #0x18]
+     bic     r6, r6, #0x600000
+     orr     r6, r6, #0x200000
+     str     r6, [r2, #0x18]
+
+     ldr     r6, [r2, #0x14]
+     bic     r6, r6, #0x4000000
+     str     r6, [r2, #0x14]
+
+periph2_clk_switch6:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     periph2_clk_switch6
+
+change_divider_only:
+    /* Calculate the MMDC divider
+     * based on the requested freq.
+     */
+    ldr    r6, =400000000
+    ldr    r4, =0
+Loop2:
+    sub    r6, r6, r0
+    cmp   r6, r0
+    blt     Div_Found
+    add    r4, r4, #1
+    bgt     Loop2
+
+     /* Shift divider into correct offset. */
+     lsl    r4, r4, #3
+Div_Found:
+     /* Set the MMDC PODF. */
+      ldr    r6, [r2, #0x14]
+      bic    r6, r6, #0x38
+      orr    r6, r6, r4
+      str    r6, [r2, #0x14]
+
+mmdc_podf1:
+     ldr     r6, [r2, #0x48]
+     cmp     r6, #0
+     bne     mmdc_podf1
+
+    .endm
+
+      .macro   mmdc_clk_lower_100MHz
+
+      /* Prior to reducing the DDR frequency (at 528/400 MHz),
+      read the Measure unit count bits (MU_UNIT_DEL_NUM) */
+      ldr     r5, =0x8B8
+      ldr     r6, [r8, r5]
+      /* Original MU unit count */
+      mov   r6, r6, LSR #16
+      ldr     r4, =0x3FF
+      and    r6, r6, r4
+      /* Original MU unit count * 2 */
+      mov    r7, r6, LSL #1
+      /* Bypass the automatic measure unit when below 100 MHz
+      by setting the Measure unit bypass enable bit (MU_BYP_EN) */
+      ldr     r6, [r8, r5]
+      orr     r6, r6, #0x400
+      str     r6, [r8, r5]
+      /* Double the measure count value read in step 1 and program it in the
+        * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
+        * Register for the reduced frequency operation below 100 MHz
+        */
+       ldr    r6, [r8, r5]
+       ldr    r4, =0x3FF
+       bic    r6, r6, r4
+       orr    r6, r6, r7
+       str     r6, [r8, r5]
+      /* Now perform a Force Measurement. */
+      ldr     r6, [r8, r5]
+      orr    r6, r6, #0x800
+      str     r6, [r8, r5]
+      /* Wait for FRC_MSR to clear. */
+force_measure:
+      ldr     r6, [r8, r5]
+      and    r6, r6, #0x800
+      cmp   r6, #0x0
+      bne    force_measure
+
+       .endm
+
+      .macro   mmdc_clk_above_100MHz
+
+      /* Make sure that the PHY measurement unit is NOT in bypass mode */
+      ldr     r5, =0x8B8
+      ldr     r6, [r8, r5]
+      bic    r6, r6, #0x400
+      str     r6, [r8, r5]
+      /* Now perform a Force Measurement. */
+      ldr     r6, [r8, r5]
+      orr    r6, r6, #0x800
+      str     r6, [r8, r5]
+      /* Wait for FRC_MSR to clear. */
+force_measure1:
+      ldr     r6, [r8, r5]
+      and    r6, r6, #0x800
+      cmp   r6, #0x0
+      bne    force_measure1
+      .endm
+
+/*
+ *  mx6sl_ddr_iram
+ *
+ *  Idle the processor (eg, wait for interrupt).
+ *  Make sure DDR is in self-refresh.
+ *  IRQs are already disabled.
+ * r0 : DDR freq.
+ * r1: low_bus_freq_mode flag
+ */
+ENTRY(mx6sl_ddr_iram)
+
+    push {r4, r5, r6, r7, r8, r9, r10 }
+
+mx6sl_ddr_freq_change:
+    ldr     r3, =ANATOP_BASE_ADDR
+    add   r3, r3, #PERIPBASE_VIRT
+
+    ldr     r2, =CCM_BASE_ADDR
+    add   r2, r2, #PERIPBASE_VIRT
+
+    ldr     r8, =MMDC_P0_BASE_ADDR
+    add   r8, r8, #PERIPBASE_VIRT
+
+    /* Prime all TLB entries. */
+    adr   r7, mx6sl_ddr_freq_change               @Address in this function.
+
+    ldr     r6, [r7]
+    ldr     r6, [r8]
+    ldr     r6, [r3]
+    ldr     r6, [r2]
+
+     dsb
+     isb
+
+     /* Disable Automatic power savings. */
+     ldr    r6, [r8, #0x404]
+     orr    r6, r6, #0x01
+     str    r6, [r8, #0x404]
+
+     /* Disable MMDC power down timer. */
+     /*MMDC0_MDPDC disable power down timer */
+     ldr    r6, [r8, #0x4]
+     bic    r6, r6, #0xff00
+     str    r6, [r8, #0x4]
+
+     /* Delay for a while */
+     ldr      r10, =10
+delay1:
+     ldr      r7, =0
+cont1:
+     ldr      r6, [r8, r7]
+     add     r7, r7, #4
+     cmp    r7, #16
+     bne     cont1
+     sub     r10, r10, #1
+     cmp    r10, #0
+     bgt     delay1
+
+     /* Make the DDR explicitly enter self-refresh. */
+     ldr     r6, [r8, #0x404]
+     orr    r6, r6, #0x200000
+     str     r6, [r8, #0x404]
+
+poll_dvfs_set_1:
+     ldr     r6, [r8, #0x404]
+     and     r6, r6, #0x2000000
+     cmp    r6, #0x2000000
+     bne     poll_dvfs_set_1
+
+     /* set SBS step-by-step mode */
+     ldr     r6, [r8, #0x410]
+     orr     r6, r6, #0x100
+     str     r6, [r8, #0x410]
+
+     ldr     r10, =100000000
+     cmp   r0, r10
+     bgt    set_ddr_mu_above_100
+     mmdc_clk_lower_100MHz
+
+set_ddr_mu_above_100:
+     ldr     r10, =24000000
+     cmp    r0, r10
+     beq     set_to_24MHz
+
+     ddr_switch_400MHz
+     ldr     r10,  =100000000
+     cmp  r0, r10
+     blt     done
+     mmdc_clk_above_100MHz
+     b    done
+
+set_to_24MHz:
+     mx6sl_switch_to_24MHz
+
+done:
+     /* clear DVFS - exit from self refresh mode */
+     ldr     r6, [r8, #0x404]
+     bic     r6, r6, #0x200000
+     str     r6, [r8, #0x404]
+
+poll_dvfs_clear_1:
+     ldr     r6, [r8, #0x404]
+     and     r6, r6, #0x2000000
+     cmp     r6, #0x2000000
+     beq     poll_dvfs_clear_1
+
+     /* Enable Automatic power savings. */
+     ldr    r6, [r8, #0x404]
+     bic    r6, r6, #0x01
+     str    r6, [r8, #0x404]
+
+     ldr     r10, =24000000
+     cmp    r0, r10
+     beq     skip_power_down
+
+     /* Enable MMDC power down timer. */
+     ldr    r6, [r8, #0x4]
+     orr    r6, r6, #0x5500
+     str    r6, [r8, #0x4]
+
+skip_power_down:
+     /* clear SBS - unblock DDR accesses */
+     ldr     r6, [r8, #0x410]
+     bic     r6, r6, #0x100
+     str     r6, [r8, #0x410]
+
+    pop {r4,r5, r6, r7, r8, r9, r10}
+
+    /* Restore registers */
+    mov     pc, lr
+
+    .type   mx6sl_ddr_do_iram, #object
+ENTRY(mx6sl_ddr_do_iram)
+    .word   mx6sl_ddr_iram
+    .size    mx6sl_ddr_iram, . - mx6sl_ddr_iram
diff --git a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
new file mode 100644
index 000000000000..ee66541f8bff
--- /dev/null
+++ b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/pfuze.h>
+#include <mach/irqs.h>
+
+/*
+ * Convenience conversion.
+ * Here atm, maybe there is somewhere better for this.
+ */
+#define mV_to_uV(mV) (mV * 1000)
+#define uV_to_mV(uV) (uV / 1000)
+#define V_to_uV(V) (mV_to_uV(V * 1000))
+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
+
+#define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR         (0x08)
+ /*SWBST*/
+#define PFUZE100_SW1ASTANDBY	33
+#define PFUZE100_SW1ASTANDBY_STBY_VAL	(0x16)
+#define PFUZE100_SW1ASTANDBY_STBY_M	(0x3f<<0)
+#define PFUZE100_SW1BSTANDBY   40
+#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x16)
+#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
+#define PFUZE100_SW1CSTANDBY	47
+#define PFUZE100_SW1CSTANDBY_STBY_VAL	(0x16)
+#define PFUZE100_SW1CSTANDBY_STBY_M	(0x3f<<0)
+#define PFUZE100_SW2STANDBY     54
+#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
+#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
+#define PFUZE100_SW3ASTANDBY    61
+#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
+#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
+#define PFUZE100_SW3BSTANDBY    68
+#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
+#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
+#define PFUZE100_SW4STANDBY     75
+#define PFUZE100_SW4STANDBY_STBY_VAL    0
+#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
+#define PFUZE100_SWBSTCON1	102
+#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL	(0x1<<2)
+#define PFUZE100_SWBSTCON1_SWBSTMOD_M	(0x3<<2)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+static struct regulator_consumer_supply sw1_consumers[] = {
+	{
+		.supply	   = "VDDCORE",
+	}
+};
+static struct regulator_consumer_supply sw1c_consumers[] = {
+	{
+		.supply	   = "VDDSOC",
+	},
+};
+#endif
+
+static struct regulator_consumer_supply sw2_consumers[] = {
+	{
+		.supply		= "MICVDD",
+		.dev_name	= "1-001a",
+	}
+};
+static struct regulator_consumer_supply sw4_consumers[] = {
+       {
+	.supply = "AUD_1V8",
+	}
+};
+static struct regulator_consumer_supply swbst_consumers[] = {
+       {
+	.supply = "SWBST_5V",
+	}
+};
+static struct regulator_consumer_supply vgen1_consumers[] = {
+       {
+	.supply = "VGEN1_1V5",
+	}
+};
+static struct regulator_consumer_supply vgen2_consumers[] = {
+       {
+	.supply = "VGEN2_1V5",
+	}
+};
+static struct regulator_consumer_supply vgen3_consumers[] = {
+	{
+		.supply    = "AVDD",
+		.dev_name	= "1-001a",
+	},
+	{
+		.supply    = "DCVDD",
+		.dev_name	= "1-001a",
+	},
+	{
+		.supply    = "CPVDD",
+		.dev_name	= "1-001a",
+	},
+	{
+		.supply    = "PLLVDD",
+		.dev_name	= "1-001a",
+	},
+	{
+		.supply		= "DBVDD",
+		.dev_name	= "1-001a",
+	}
+};
+static struct regulator_consumer_supply vgen4_consumers[] = {
+       {
+	.supply = "VGEN4_1V8",
+	}
+};
+static struct regulator_consumer_supply vgen5_consumers[] = {
+       {
+	.supply = "VGEN5_2V8",
+	}
+};
+static struct regulator_consumer_supply vgen6_consumers[] = {
+       {
+	.supply = "VGEN6_3V3",
+	}
+};
+
+static struct regulator_init_data sw1a_init = {
+	.constraints = {
+			.name = "PFUZE100_SW1A",
+#ifdef PFUZE100_FIRST_VERSION
+			.min_uV = 650000,
+			.max_uV = 1437500,
+#else
+			.min_uV = 300000,
+			.max_uV = 1875000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.boot_on = 1,
+			.always_on = 1,
+			},
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+	.consumer_supplies = sw1_consumers,
+#endif
+};
+
+static struct regulator_init_data sw1b_init = {
+	.constraints = {
+			.name = "PFUZE100_SW1B",
+			.min_uV = 300000,
+			.max_uV = 1875000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+};
+
+static struct regulator_init_data sw1c_init = {
+	.constraints = {
+			.name = "PFUZE100_SW1C",
+			.min_uV = 300000,
+			.max_uV = 1875000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
+	.consumer_supplies = sw1c_consumers,
+#endif
+};
+
+static struct regulator_init_data sw2_init = {
+	.constraints = {
+			.name = "PFUZE100_SW2",
+#if PFUZE100_SW2_VOL6
+			.min_uV = 800000,
+			.max_uV = 3950000,
+#else
+			.min_uV = 400000,
+			.max_uV = 1975000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(sw2_consumers),
+	.consumer_supplies = sw2_consumers,
+};
+
+static struct regulator_init_data sw3a_init = {
+	.constraints = {
+			.name = "PFUZE100_SW3A",
+#if PFUZE100_SW3_VOL6
+			.min_uV = 800000,
+			.max_uV = 3950000,
+#else
+			.min_uV = 400000,
+			.max_uV = 1975000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+};
+
+static struct regulator_init_data sw3b_init = {
+	.constraints = {
+			.name = "PFUZE100_SW3B",
+#if PFUZE100_SW3_VOL6
+			.min_uV = 800000,
+			.max_uV = 3950000,
+#else
+			.min_uV = 400000,
+			.max_uV = 1975000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+};
+
+static struct regulator_init_data sw4_init = {
+	.constraints = {
+			.name = "PFUZE100_SW4",
+#if PFUZE100_SW4_VOL6
+			.min_uV = 800000,
+			.max_uV = 3950000,
+#else
+			.min_uV = 400000,
+			.max_uV = 1975000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(sw4_consumers),
+	.consumer_supplies = sw4_consumers,
+};
+
+static struct regulator_init_data swbst_init = {
+	.constraints = {
+			.name = "PFUZE100_SWBST",
+			.min_uV = 5000000,
+			.max_uV = 5150000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(swbst_consumers),
+	.consumer_supplies = swbst_consumers,
+};
+
+static struct regulator_init_data vsnvs_init = {
+	.constraints = {
+			.name = "PFUZE100_VSNVS",
+			.min_uV = 1200000,
+			.max_uV = 3000000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+};
+
+static struct regulator_init_data vrefddr_init = {
+	.constraints = {
+			.name = "PFUZE100_VREFDDR",
+			.always_on = 1,
+			.boot_on = 1,
+			},
+};
+
+static struct regulator_init_data vgen1_init = {
+	.constraints = {
+			.name = "PFUZE100_VGEN1",
+#ifdef PFUZE100_FIRST_VERSION
+			.min_uV = 1200000,
+			.max_uV = 1550000,
+#else
+			.min_uV = 800000,
+			.max_uV = 1550000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(vgen1_consumers),
+	.consumer_supplies = vgen1_consumers,
+};
+
+static struct regulator_init_data vgen2_init = {
+	.constraints = {
+			.name = "PFUZE100_VGEN2",
+#ifdef PFUZE100_FIRST_VERSION
+			.min_uV = 1200000,
+			.max_uV = 1550000,
+#else
+			.min_uV = 800000,
+			.max_uV = 1550000,
+#endif
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+			.valid_modes_mask = 0,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(vgen2_consumers),
+	.consumer_supplies = vgen2_consumers,
+
+};
+
+static struct regulator_init_data vgen3_init = {
+	.constraints = {
+			.name = "PFUZE100_VGEN3",
+			.min_uV = 1800000,
+			.max_uV = 3300000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+			.valid_modes_mask = 0,
+			.always_on = 0,
+			.boot_on = 0,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(vgen3_consumers),
+	.consumer_supplies = vgen3_consumers,
+};
+
+static struct regulator_init_data vgen4_init = {
+	.constraints = {
+			.name = "PFUZE100_VGEN4",
+			.min_uV = 1800000,
+			.max_uV = 3300000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+			.valid_modes_mask = 0,
+			.always_on = 1,
+			.boot_on = 1,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(vgen4_consumers),
+	.consumer_supplies = vgen4_consumers,
+};
+
+static struct regulator_init_data vgen5_init = {
+	.constraints = {
+			.name = "PFUZE100_VGEN5",
+			.min_uV = 1800000,
+			.max_uV = 3300000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+			.valid_modes_mask = 0,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(vgen5_consumers),
+	.consumer_supplies = vgen5_consumers,
+};
+
+static struct regulator_init_data vgen6_init = {
+	.constraints = {
+			.name = "PFUZE100_VGEN6",
+			.min_uV = 1800000,
+			.max_uV = 3300000,
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+			.valid_modes_mask = 0,
+			},
+	.num_consumer_supplies = ARRAY_SIZE(vgen6_consumers),
+	.consumer_supplies = vgen6_consumers,
+};
+
+static int pfuze100_init(struct mc_pfuze *pfuze)
+{
+	int ret;
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
+			    PFUZE100_SW1ASTANDBY_STBY_M,
+			    PFUZE100_SW1ASTANDBY_STBY_VAL);
+	if (ret)
+		goto err;
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
+			    PFUZE100_SW1CSTANDBY_STBY_M,
+			    PFUZE100_SW1CSTANDBY_STBY_VAL);
+	if (ret)
+		goto err;
+	/*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+			    PFUZE100_SW1ACON_SPEED_M,
+			    PFUZE100_SW1ACON_SPEED_VAL);
+	if (ret)
+		goto err;
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+			    PFUZE100_SW1CCON_SPEED_M,
+			    PFUZE100_SW1CCON_SPEED_VAL);
+	if (ret)
+		goto err;
+	return 0;
+err:
+	printk(KERN_ERR "pfuze100 init error!\n");
+	return -1;
+}
+
+static struct pfuze_regulator_init_data mx6q_sabreauto_pfuze100_regulators[] = {
+	{.id = PFUZE100_SW1A,	.init_data = &sw1a_init},
+	{.id = PFUZE100_SW1B,	.init_data = &sw1b_init},
+	{.id = PFUZE100_SW1C,	.init_data = &sw1c_init},
+	{.id = PFUZE100_SW2,	.init_data = &sw2_init},
+	{.id = PFUZE100_SW3A,	.init_data = &sw3a_init},
+	{.id = PFUZE100_SW3B,	.init_data = &sw3b_init},
+	{.id = PFUZE100_SW4,	.init_data = &sw4_init},
+	{.id = PFUZE100_SWBST,	.init_data = &swbst_init},
+	{.id = PFUZE100_VSNVS,	.init_data = &vsnvs_init},
+	{.id = PFUZE100_VREFDDR,	.init_data = &vrefddr_init},
+	{.id = PFUZE100_VGEN1,	.init_data = &vgen1_init},
+	{.id = PFUZE100_VGEN2,	.init_data = &vgen2_init},
+	{.id = PFUZE100_VGEN3,	.init_data = &vgen3_init},
+	{.id = PFUZE100_VGEN4,	.init_data = &vgen4_init},
+	{.id = PFUZE100_VGEN5,	.init_data = &vgen5_init},
+	{.id = PFUZE100_VGEN6,	.init_data = &vgen6_init},
+};
+
+static struct pfuze_platform_data pfuze100_plat = {
+	.flags = PFUZE_USE_REGULATOR,
+	.num_regulators = ARRAY_SIZE(mx6q_sabreauto_pfuze100_regulators),
+	.regulators = mx6q_sabreauto_pfuze100_regulators,
+	.pfuze_init = pfuze100_init,
+};
+
+static struct i2c_board_info __initdata pfuze100_i2c_device = {
+	I2C_BOARD_INFO(PFUZE100_I2C_DEVICE_NAME, PFUZE100_I2C_ADDR),
+	.platform_data = &pfuze100_plat,
+};
+
+int __init mx6sl_evk_init_pfuze100(u32 int_gpio)
+{
+	if (int_gpio)
+		pfuze100_i2c_device.irq = gpio_to_irq(int_gpio); /*update INT gpio */
+	return i2c_register_board_info(0, &pfuze100_i2c_device, 1);
+}
diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S
new file mode 100644
index 000000000000..89fe4e292352
--- /dev/null
+++ b/arch/arm/mach-mx6/mx6sl_wfi.S
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/linkage.h>
+#include <mach/hardware.h>
+#define IRAM_WAIT_SIZE 	(1 << 11)
+
+
+	.macro	sl_ddr_io_save
+
+	ldr	r4, [r1, #0x30c] /* DRAM_DQM0 */
+	ldr	r5, [r1, #0x310] /* DRAM_DQM1 */
+	ldr	r6, [r1, #0x314] /* DRAM_DQM2 */
+	ldr	r7, [r1, #0x318] /* DRAM_DQM3 */
+	stmfd	r9!, {r4-r7}
+
+	ldr	r4, [r1, #0x344] /* DRAM_SDQS0 */
+	ldr	r5, [r1, #0x348] /* DRAM_SDQS1 */
+	ldr	r6, [r1, #0x34c] /* DRAM_SDQS2 */
+	ldr	r7, [r1, #0x350] /* DRAM_SDQS3 */
+	stmfd	r9!, {r4-r7}
+
+	ldr	r4, [r1, #0x5c4] /* GPR_B0DS */
+	ldr	r5, [r1, #0x5cc] /* GPR_B1DS */
+	ldr	r6, [r1, #0x5d4] /* GPR_B2DS */
+	ldr	r7, [r1, #0x5d8] /* GPR_B3DS */
+	stmfd	r9!, {r4-r7}
+
+	ldr	r4, [r1, #0x300] /* DRAM_CAS */
+	ldr	r5, [r1, #0x31c] /* DRAM_RAS */
+	ldr	r6, [r1, #0x338] /* DRAM_SDCLK_0 */
+	ldr r7, [r1, #0x5ac] /* GPR_ADDS*/
+	stmfd	r9!, {r4-r7}
+
+	ldr	r4, [r1, #0x5b0] /* DDRMODE_CTL */
+	ldr	r5, [r1, #0x5c0] /* DDRMODE */
+	ldr	r6, [r1, #0x33c] /* DRAM_SODT0*/
+	ldr	r7, [r1, #0x340] /* DRAM_SODT1*/
+	stmfd	r9!, {r4-r7}
+
+	ldr	r4, [r1, #0x330] /* DRAM_SDCKE0 */
+	ldr	r5, [r1, #0x334] /* DRAM_SDCKE1 */
+	ldr	r6, [r1, #0x320] /* DRAM_RESET */
+	ldr	r7, [r1, #0x5c8] /* GPR_CTLDS */
+	stmfd	r9!, {r4-r7}
+
+	.endm
+
+	.macro	sl_ddr_io_restore
+
+	ldmea	r9!, {r4-r7}
+	str	r4, [r1, #0x30c] /* DRAM_DQM0 */
+	str	r5, [r1, #0x310] /* DRAM_DQM1 */
+	str	r6, [r1, #0x314] /* DRAM_DQM2 */
+	str	r7, [r1, #0x318] /* DRAM_DQM3 */
+
+	ldmea	r9!, {r4-r7}
+	str	r4, [r1, #0x344] /* DRAM_SDQS0 */
+	str	r5, [r1, #0x348] /* DRAM_SDQS1 */
+	str	r6, [r1, #0x34c] /* DRAM_SDQS2 */
+	str	r7, [r1, #0x350] /* DRAM_SDQS3 */
+
+	ldmea	r9!, {r4-r7}
+	str	r4, [r1, #0x5c4] /* GPR_B0DS */
+	str	r5, [r1, #0x5cc] /* GPR_B1DS */
+	str r6, [r1, #0x5d4] /* GPR_B2DS */
+	str r7, [r1, #0x5d8] /* GPR_B3DS */
+
+	ldmea	r9!, {r4-r7}
+	str	r4, [r1, #0x300] /* DRAM_CAS */
+	str	r5, [r1, #0x31c] /* DRAM_RAS */
+	str	r6, [r1, #0x338] /* DRAM_SDCLK_0 */
+	str r7, [r1, #0x5ac] /* GPR_ADDS*/
+
+	ldmea	r9!, {r4-r7}
+	str	r4, [r1, #0x5b0] /* DDRMODE_CTL */
+	str	r5, [r1, #0x5c0] /* DDRMODE */
+	str	r6, [r1, #0x33c] /* DRAM_SODT0*/
+	str	r7, [r1, #0x340] /* DRAM_SODT1*/
+
+	ldmea	r9!, {r4-r7}
+	str	r4, [r1, #0x330] /* DRAM_SDCKE0 */
+	str	r5, [r1, #0x334] /* DRAM_SDCKE1 */
+	str	r6, [r1, #0x320] /* DRAM_RESET */
+	str	r7, [r1, #0x5c8] /* GPR_CTLDS */
+
+	.endm
+
+	.macro	sl_ddr_io_set_lpm
+
+	mov	r4, #0
+	str	r4, [r1, #0x30c] /* DRAM_DQM0 */
+	str	r4, [r1, #0x310] /* DRAM_DQM1 */
+	str	r4, [r1, #0x314] /* DRAM_DQM2 */
+	str	r4, [r1, #0x318] /* DRAM_DQM3 */
+
+	/* Make sure the Pull Ups are enabled.
+	 * So only reduce the drive stength, but
+	 * leave the pull-ups in the original state.
+	 * This is required for LPDDR2.
+	 */
+	ldr	r4, [r1, #0x344]
+	orr	r4, r4, #0x3000
+	str	r4, [r1, #0x344] /* DRAM_SDQS0 */
+	str	r4, [r1, #0x348] /* DRAM_SDQS1 */
+	str	r4, [r1, #0x34c] /* DRAM_SDQS2 */
+	str	r4, [r1, #0x350] /* DRAM_SDQS3 */
+
+	str	r4, [r1, #0x5c4] /* GPR_B0DS */
+	str	r4, [r1, #0x5cc] /* GPR_B1DS */
+	str r4, [r1, #0x5d4] /* GPR_B2DS */
+	str r4, [r1, #0x5d8] /* GPR_B3DS */
+
+	str	r4, [r1, #0x300] /* DRAM_CAS */
+	str	r4, [r1, #0x31c] /* DRAM_RAS */
+	str	r4, [r1, #0x338] /* DRAM_SDCLK_0 */
+	str r4, [r1, #0x5ac] /* GPR_ADDS*/
+
+	str	r4, [r1, #0x5b0] /* DDRMODE_CTL */
+	str	r4, [r1, #0x5c0] /* DDRMODE */
+	str	r4, [r1, #0x33c] /* DRAM_SODT0*/
+	str	r4, [r1, #0x340] /* DRAM_SODT1*/
+
+	mov	r4, #0x80000
+	str	r4, [r1, #0x320] /* DRAM_RESET */
+	mov	r4, #0x1000
+	str	r4, [r1, #0x330] /* DRAM_SDCKE0 */
+	str	r4, [r1, #0x334] /* DRAM_SDCKE1 */
+
+	.endm
+
+/*
+ *  mx6sl_wait
+ *
+ *  Idle the processor (eg, wait for interrupt).
+ *  Make sure DDR is in self-refresh.
+ *  IRQs are already disabled.
+ * r0 : arm_podf before WFI is entered
+ * r1: WFI IRAMcode base address.
+ */
+ENTRY(mx6sl_wait)
+
+    push {r4, r5, r6, r7, r8, r9, r10}
+
+mx6sl_lpm_wfi:
+    /* Get the IRAM data storage address. */
+    mov    r10, r1
+    mov	r9, r1 		/* get suspend_iram_base */
+     add	r9, r9, #IRAM_WAIT_SIZE	/* 4K */
+
+    ldr     r1, =MX6Q_IOMUXC_BASE_ADDR
+    add   r1, r1, #PERIPBASE_VIRT
+
+      /* Save the DDR IO state. */
+     sl_ddr_io_save
+
+    ldr     r3, =ANATOP_BASE_ADDR
+    add   r3, r3, #PERIPBASE_VIRT
+
+    ldr     r2, =CCM_BASE_ADDR
+    add   r2, r2, #PERIPBASE_VIRT
+
+    ldr     r8, =MMDC_P0_BASE_ADDR
+    add   r8, r8, #PERIPBASE_VIRT
+
+
+    /* Prime all TLB entries. */
+    adr   r7, mx6sl_lpm_wfi               @Address in this function.
+
+    ldr     r6, [r7]
+
+    ldr     r6, [r8]
+    ldr     r6, [r3]
+    ldr     r6, [r2]
+    ldr     r6, [r1]
+
+     dsb
+
+     /* Disable Automatic power savings. */
+     ldr    r6, [r8, #0x404]
+     orr    r6, r6, #0x01
+     str    r6, [r8, #0x404]
+
+     /* Make the DDR explicitly enter self-refresh. */
+     ldr     r6, [r8, #0x404]
+     orr    r6, r6, #0x200000
+     str     r6, [r8, #0x404]
+
+poll_dvfs_set_1:
+     ldr     r6, [r8, #0x404]
+     and     r6, r6, #0x2000000
+     cmp    r6, #0x2000000
+     bne     poll_dvfs_set_1
+
+     /* set SBS step-by-step mode */
+     ldr     r6, [r8, #0x410]
+     orr     r6, r6, #0x100
+     str     r6, [r8, #0x410]
+
+     /* Now set DDR rate to 1MHz. */
+     /* DDR is from bypassed PLL2 on periph2_clk2 path.
+       * Set the periph2_clk2_podf to divide by 8.
+       */
+     ldr    r6, [r2, #0x14]
+     orr   r6, r6, #0x07
+     str    r6, [r2, #0x14]
+
+     /* Now set MMDC PODF to divide by 3. */
+     ldr    r6, [r2, #0x14]
+     bic    r6, r6, #0x38
+     orr    r6, r6, #0x10
+     str     r6, [r2, #0x14]
+
+    /* Loop till podf is accepted. */
+mmdc_podf:
+     ldr     r6, [r2, #0x48]
+     cmp   r6, #0x0
+     bne   mmdc_podf
+
+      /* Set the DDR IO in LPM state. */
+     sl_ddr_io_set_lpm
+
+     /* Set AHB to 8MHz., AXI to 3MHz */
+     /* We want to ensure IPG_PERCLK to AHB
+      * clk ratio is 1:2.5
+      */
+     /* Store the AXI/AHB podfs. */
+     ldr    r9, [r2, #0x14]
+     mov   r6, r9
+     bic      r6, r6, #0x1c00
+     orr    r6, r6, #0x800
+     orr    r6, r6, #0x70000
+     str     r6, [r2, #0x14]
+
+    /* Loop till podf is accepted. */
+ahb_podf:
+     ldr     r6, [r2, #0x48]
+     cmp   r6, #0x0
+     bne   podf_loop
+
+    /* Now set ARM to 24MHz. */
+    /* Move ARM to be sourced from STEP_CLK
+     * after setting STEP_CLK to 24MHz.
+     */
+     ldr    r6, [r2, #0xc]
+     bic   r6, r6, #0x100
+     str    r6, [r2, #0x0c]
+     /* Now PLL1_SW_CLK to step_clk. */
+     ldr    r6, [r2, #0x0c]
+     orr    r6, r6, #0x4
+     str    r6, [r2, #0x0c]
+
+    /* Bypass PLL1 and power it down. */
+    ldr     r6, =(1 << 16)
+    orr    r6, r6, #0x1000
+    str     r6, [r3, #0x04]
+
+    /* Set the ARM PODF to divide by 8. */
+    /* IPG is at 4MHz here, we need ARM to
+     * run at the 12:5 ratio (WAIT mode issue).
+     */
+    ldr    r6, =0x7
+    str    r6, [r2, #0x10]
+
+    /* Loop till podf is accepted. */
+podf_loop:
+     ldr     r6, [r2, #0x48]
+     cmp   r6, #0x0
+     bne   podf_loop
+
+     /* Now do WFI. */
+     dsb
+
+     wfi
+
+     /* Set original ARM PODF back. */
+    str    r0, [r2, #0x10]
+
+    /* Loop till podf is accepted. */
+podf_loop1:
+     ldr     r6, [r2, #0x48]
+     cmp   r6, #0x0
+     bne   podf_loop1
+
+     /* Power up PLL1 and un-bypass it. */
+    ldr     r6, =(1 << 12)
+    str     r6, [r3, #0x08]
+
+    /* Wait for PLL1 to relock. */
+wait_for_pll_lock:
+    ldr    r6, [r3, #0x0]
+    and   r6, r6, #0x80000000
+    cmp  r6, #0x80000000
+    bne   wait_for_pll_lock
+
+    ldr     r6, =(1 << 16)
+    str     r6, [r3, #0x08]
+
+    /* Set PLL1_sw_clk back to PLL1. */
+    ldr    r6, [r2, #0x0c]
+    bic    r6, r6, #0x4
+    str    r6, [r2, #0xc]
+
+    /* Restore AHB/AXI back. */
+    str      r9, [r2, #0x14]
+
+    /* Loop till podf is accepted. */
+ahb_podf1:
+     ldr     r6, [r2, #0x48]
+     cmp   r6, #0x0
+     bne   podf_loop1
+
+    mov	r9, r10 		/* get suspend_iram_base */
+     add	r9, r9, #IRAM_WAIT_SIZE	/* 4K */
+
+    /* Restore the DDR IO before exiting self-refresh. */
+     sl_ddr_io_restore
+
+    /* Set MMDC back to 24MHz. */
+    /* Set periph2_clk2_podf to divide by 1. */
+     /* Now set MMDC PODF to divide by 1. */
+     ldr    r6, [r2, #0x14]
+     bic   r6, r6, #0x3f
+     str    r6, [r2, #0x14]
+
+mmdc_podf1:
+     ldr     r6, [r2, #0x48]
+     cmp   r6, #0x0
+     bne   mmdc_podf1
+
+     /* clear DVFS - exit from self refresh mode */
+     ldr     r6, [r8, #0x404]
+     bic     r6, r6, #0x200000
+     str     r6, [r8, #0x404]
+
+poll_dvfs_clear_1:
+     ldr     r6, [r8, #0x404]
+     and     r6, r6, #0x2000000
+     cmp     r6, #0x2000000
+     beq     poll_dvfs_clear_1
+
+     /* Add these nops so that the
+      * prefetcher will not try to get
+      * any instructions from DDR.
+      * The prefetch depth is about 23
+      * on A9, so adding 25 nops.
+      */
+     nop
+     nop
+     nop
+     nop
+     nop
+
+     nop
+     nop
+     nop
+     nop
+     nop
+
+     nop
+     nop
+     nop
+     nop
+     nop
+
+     nop
+     nop
+     nop
+     nop
+     nop
+
+     nop
+     nop
+     nop
+     nop
+     nop
+
+     /* Enable Automatic power savings. */
+     ldr    r6, [r8, #0x404]
+     bic    r6, r6, #0x01
+     str    r6, [r8, #0x404]
+
+     /* clear SBS - unblock DDR accesses */
+     ldr     r6, [r8, #0x410]
+     bic     r6, r6, #0x100
+     str     r6, [r8, #0x410]
+
+
+    pop {r4,r5, r6, r7, r8, r9, r10}
+
+    /* Restore registers */
+    mov     pc, lr
+
+    .type   mx6sl_do_wait, #object
+ENTRY(mx6sl_do_wait)
+    .word   mx6sl_wait
+    .size    mx6sl_wait, . - mx6sl_wait
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index b1d91e311b5e..c19d895139cf 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -38,6 +38,7 @@
 #endif
 #include "crm_regs.h"
 #include "src-reg.h"
+#include "regs-anadig.h"
 
 #define SCU_CTRL_OFFSET				0x00
 #define GPC_IMR1_OFFSET				0x08
@@ -118,6 +119,11 @@ static void usb_power_down_handler(void)
 {
 	u32 temp;
 	bool usb_oh3_clk_already_on;
+	if ((__raw_readl(anatop_base + HW_ANADIG_ANA_MISC0)
+		& BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) != 0) {
+			usb_vbus_wakeup_enabled = false;
+			return;
+	}
 	/* enable usb oh3 clock if needed*/
 	temp = __raw_readl(MXC_CCM_CCGR6);
 	usb_oh3_clk_already_on =	\
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index 57dee5f4c4c0..800c7cc4e8bd 100644
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -52,14 +52,14 @@ extern unsigned int gpc_wake_irq[4];
 
 static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
 
-int wait_mode_arm_podf;
 volatile unsigned int num_cpu_idle;
 volatile unsigned int num_cpu_idle_lock = 0x0;
 int wait_mode_arm_podf;
 int cur_arm_podf;
-bool arm_mem_clked_in_wait;
 void arch_idle_with_workaround(int cpu);
 
+extern void *mx6sl_wfi_iram_base;
+extern void (*mx6sl_wfi_iram)(int arm_podf, unsigned long wfi_iram_addr);
 extern void mx6_wait(void *num_cpu_idle_lock, void *num_cpu_idle, \
 				int wait_arm_podf, int cur_arm_podf);
 extern bool enable_wait_mode;
@@ -78,6 +78,7 @@ void gpc_set_wakeup(unsigned int irq[4])
 
 	return;
 }
+
 /* set cpu low power mode before WFI instruction */
 void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 {
@@ -194,7 +195,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 			__raw_writel(__raw_readl(MXC_CCM_CCR) &
 				(~MXC_CCM_CCR_WB_COUNT_MASK) &
 				(~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR);
-			udelay(60);
+			udelay(80);
 			/* Reconfigurate WB and RBC counter */
 			__raw_writel(__raw_readl(MXC_CCM_CCR) |
 				(0x1 << MXC_CCM_CCR_WB_COUNT_OFFSET) |
@@ -251,25 +252,54 @@ void arch_idle_single_core(void)
 
 		ca9_do_idle();
 	} else {
-		/*
-		  * Implement the 12:5 ARM:IPG_CLK ratio
-		  * workaround for the WAIT mode issue.
-		  * We can directly use the divider to drop the ARM
-		  * core freq in a single core environment.
-		  *  Set the ARM_PODF to get the max freq possible
-		  * to avoid the WAIT mode issue when IPG is at 66MHz.
-		  */
-		if (cpu_is_mx6sl()) {
-			reg = __raw_readl(MXC_CCM_CGPR);
-			reg |= MXC_CCM_CGPR_MEM_IPG_STOP_MASK;
-			__raw_writel(reg, MXC_CCM_CGPR);
-		}
-		__raw_writel(wait_mode_arm_podf, MXC_CCM_CACRR);
-		while (__raw_readl(MXC_CCM_CDHIPR))
-			;
-		ca9_do_idle();
+		if (low_bus_freq_mode || audio_bus_freq_mode) {
+			if (cpu_is_mx6sl() && low_bus_freq_mode) {
+				/* In this mode PLL2 i already in bypass,
+				  * ARM is sourced from PLL1. The code in IRAM
+				  * will set ARM to be sourced from STEP_CLK
+				  * at 24MHz. It will also set DDR to 1MHz to
+				  * reduce power.
+				  */
+				u32 org_arm_podf = __raw_readl(MXC_CCM_CACRR);
 
-		__raw_writel(cur_arm_podf - 1, MXC_CCM_CACRR);
+				/* Need to run WFI code from IRAM so that
+				  * we can lower DDR freq.
+				  */
+				mx6sl_wfi_iram(org_arm_podf,
+					(unsigned long)mx6sl_wfi_iram_base);
+			} else {
+				/* Need to set ARM to run at 24MHz since IPG
+				  * is at 12MHz. This is valid for audio mode on
+				  * MX6SL, and all low power modes on MX6DLS.
+				  */
+				/* PLL1_SW_CLK is sourced from PLL2_PFD2400MHz
+				  * at this point. Move it to bypassed PLL1.
+				  */
+				reg = __raw_readl(MXC_CCM_CCSR);
+				reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+				__raw_writel(reg, MXC_CCM_CCSR);
+
+				ca9_do_idle();
+
+				reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+				__raw_writel(reg, MXC_CCM_CCSR);
+			}
+		} else {
+			/*
+			  * Implement the 12:5 ARM:IPG_CLK ratio
+			  * workaround for the WAIT mode issue.
+			  * We can directly use the divider to drop the ARM
+			  * core freq in a single core environment.
+			  *  Set the ARM_PODF to get the max freq possible
+			  * to avoid the WAIT mode issue when IPG is at 66MHz.
+			  */
+			__raw_writel(wait_mode_arm_podf, MXC_CCM_CACRR);
+			while (__raw_readl(MXC_CCM_CDHIPR))
+				;
+			ca9_do_idle();
+
+			__raw_writel(cur_arm_podf - 1, MXC_CCM_CACRR);
+		}
 	}
 }
 
@@ -331,7 +361,7 @@ void arch_idle(void)
 {
 	if (enable_wait_mode) {
 		mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-		if ((mem_clk_on_in_wait || arm_mem_clked_in_wait)) {
+		if (mem_clk_on_in_wait) {
 			u32 reg;
 			/*
 			  * MX6SL, MX6Q (TO1.2 or later) and
diff --git a/arch/arm/mach-mx6/usb.h b/arch/arm/mach-mx6/usb.h
index f796e7dad87c..6914246826f6 100644
--- a/arch/arm/mach-mx6/usb.h
+++ b/arch/arm/mach-mx6/usb.h
@@ -30,6 +30,9 @@ extern void gpio_usbotg_utmi_inactive(void);
 
 extern void __init mx6_usb_dr_init(void);
 extern bool usb_icbug_swfix_need(void);
+extern int usb_stop_mode_refcount(bool enable);
+extern void usb_stop_mode_lock(void);
+extern void usb_stop_mode_unlock(void);
 extern void __init mx6_usb_h2_init(void);
 extern void __init mx6_usb_h3_init(void);
 
diff --git a/arch/arm/mach-mx6/usb_dr.c b/arch/arm/mach-mx6/usb_dr.c
index 1efac33aa7fc..8fe9700a658f 100644
--- a/arch/arm/mach-mx6/usb_dr.c
+++ b/arch/arm/mach-mx6/usb_dr.c
@@ -173,6 +173,9 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata)
 static int usbotg_init_ext(struct platform_device *pdev)
 {
 	struct clk *usb_clk;
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+	void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
+#endif
 	u32 ret;
 
 	/* at mx6q: this clock is AHB clock for usb core */
@@ -198,6 +201,12 @@ static int usbotg_init_ext(struct platform_device *pdev)
 		mdelay(3);
 	}
 	otg_used++;
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+	usb_stop_mode_lock();
+	if (usb_stop_mode_refcount(true) == 1)
+		__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
+	usb_stop_mode_unlock();
+#endif
 
 	return ret;
 }
@@ -205,6 +214,9 @@ static int usbotg_init_ext(struct platform_device *pdev)
 static void usbotg_uninit_ext(struct platform_device *pdev)
 {
 	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+	void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
+#endif
 
 	clk_disable(usb_phy1_clk);
 	clk_put(usb_phy1_clk);
@@ -214,6 +226,12 @@ static void usbotg_uninit_ext(struct platform_device *pdev)
 
 	usbotg_uninit(pdata);
 	otg_used--;
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+	usb_stop_mode_lock();
+	 if (usb_stop_mode_refcount(false) == 0)
+		__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_CLR);
+	 usb_stop_mode_unlock();
+#endif
 }
 
 static void usbotg_clock_gate(bool on)
@@ -424,18 +442,18 @@ static void _host_platform_rh_resume_swfix(struct fsl_usb2_platform_data *pdata)
 {
 	u32 index = 0;
 
-	if ((UOG_PORTSC1 & (3 << 26)) != (2 << 26))
+	if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
 		return ;
-
 	while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
 			&& (index < 1000)) {
 		udelay(500);
 		index++;
 	}
-
 	if (index >= 1000)
-		printk(KERN_INFO "%s big error\n", __func__);
-
+		printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+		__func__, __LINE__);
+	/* We should add some delay to wait for the device switch to
+	  * High-Speed 45ohm termination resistors mode. */
 	udelay(500);
 	fsl_platform_otg_set_usb_phy_dis(pdata, 1);
 }
@@ -451,9 +469,24 @@ static void _host_platform_rh_suspend(struct fsl_usb2_platform_data *pdata)
 
 static void _host_platform_rh_resume(struct fsl_usb2_platform_data *pdata)
 {
+	u32 index = 0;
+
 	/*for mx6sl ,we do not need any sw fix*/
 	if (cpu_is_mx6sl())
 		return ;
+	if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
+		return ;
+	while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
+			&& (index < 1000)) {
+		udelay(500);
+		index++;
+	}
+	if (index >= 1000)
+		printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+		__func__, __LINE__);
+	/* We should add some delay to wait for the device switch to
+	  * High-Speed 45ohm termination resistors mode. */
+	udelay(500);
 	__raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 		MX6_IO_ADDRESS(pdata->phy_regs)
 		+ HW_USBPHY_CTRL_SET);
diff --git a/arch/arm/mach-mx6/usb_h1.c b/arch/arm/mach-mx6/usb_h1.c
index 92ef0ec3c3f5..bece29f7d44b 100644
--- a/arch/arm/mach-mx6/usb_h1.c
+++ b/arch/arm/mach-mx6/usb_h1.c
@@ -134,6 +134,7 @@ static int fsl_usb_host_init_ext(struct platform_device *pdev)
 {
 	int ret;
 	struct clk *usb_clk;
+	void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 	usb_clk = clk_get(NULL, "usboh3_clk");
 	clk_enable(usb_clk);
 	usb_oh3_clk = usb_clk;
@@ -145,19 +146,25 @@ static int fsl_usb_host_init_ext(struct platform_device *pdev)
 	}
 	usbh1_internal_phy_clock_gate(true);
 	usb_phy_enable(pdev->dev.platform_data);
-
+	usb_stop_mode_lock();
+	if (usb_stop_mode_refcount(true) == 1)
+		__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
+	usb_stop_mode_unlock();
 	return 0;
 }
 
 static void fsl_usb_host_uninit_ext(struct platform_device *pdev)
 {
 	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
-
+	void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 	fsl_usb_host_uninit(pdata);
 
 	clk_disable(usb_oh3_clk);
 	clk_put(usb_oh3_clk);
-
+	usb_stop_mode_lock();
+	if (usb_stop_mode_refcount(false) == 0)
+		__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_CLR);
+	usb_stop_mode_unlock();
 }
 
 static void usbh1_clock_gate(bool on)
@@ -237,18 +244,18 @@ static void usbh1_platform_rh_resume_swfix(struct fsl_usb2_platform_data *pdata)
 {
 	u32 index = 0;
 
-	if ((UH1_PORTSC1 & (3 << 26)) != (2 << 26))
+	if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
 		return ;
-
 	while ((UH1_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
 			&& (index < 1000)) {
 		udelay(500);
 		index++;
 	}
-
 	if (index >= 1000)
-		printk(KERN_INFO "%s big error\n", __func__);
-
+		printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+		__func__, __LINE__);
+	/* We should add some delay to wait for the device switch to
+	  * High-Speed 45ohm termination resistors mode. */
 	udelay(500);
 	fsl_platform_h1_set_usb_phy_dis(pdata, 1);
 }
@@ -265,9 +272,24 @@ static void usbh1_platform_rh_suspend(struct fsl_usb2_platform_data *pdata)
 
 static void usbh1_platform_rh_resume(struct fsl_usb2_platform_data *pdata)
 {
+	u32 index = 0;
+
 	/*for mx6sl ,we do not need any sw fix*/
 	if (cpu_is_mx6sl())
 		return ;
+	if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
+		return ;
+	while ((UH1_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
+			&& (index < 1000)) {
+		udelay(500);
+		index++;
+	}
+	if (index >= 1000)
+		printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
+		__func__, __LINE__);
+	/* We should add some delay to wait for the device switch to
+	  * High-Speed 45ohm termination resistors mode. */
+	udelay(500);
 	__raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 		MX6_IO_ADDRESS(pdata->phy_regs)
 		+ HW_USBPHY_CTRL_SET);
diff --git a/arch/arm/mach-mx6/usb_h2.c b/arch/arm/mach-mx6/usb_h2.c
index 24083fd52d72..37cad034d173 100644
--- a/arch/arm/mach-mx6/usb_h2.c
+++ b/arch/arm/mach-mx6/usb_h2.c
@@ -227,9 +227,16 @@ void __init mx6_usb_h2_init(void)
 	struct platform_device *pdev, *pdev_wakeup;
 	static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 	usbh2_config.wakeup_pdata = &usbh2_wakeup_config;
-	pdev = imx6q_add_fsl_ehci_hs(2, &usbh2_config);
+	if (cpu_is_mx6sl())
+		pdev = imx6sl_add_fsl_ehci_hs(2, &usbh2_config);
+	else
+		pdev = imx6q_add_fsl_ehci_hs(2, &usbh2_config);
+
 	usbh2_wakeup_config.usb_pdata[0] = pdev->dev.platform_data;
-	pdev_wakeup = imx6q_add_fsl_usb2_hs_wakeup(2, &usbh2_wakeup_config);
+	if (cpu_is_mx6sl())
+		pdev_wakeup = imx6sl_add_fsl_usb2_hs_wakeup(2, &usbh2_wakeup_config);
+	else
+		pdev_wakeup = imx6q_add_fsl_usb2_hs_wakeup(2, &usbh2_wakeup_config);
 	((struct fsl_usb2_platform_data *)(pdev->dev.platform_data))->wakeup_pdata =
 		pdev_wakeup->dev.platform_data;
 	/* Some phy and power's special controls for host2
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e830a9cfaa91..feb83cb5e993 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -386,8 +386,6 @@ dma_alloc_writethrough(struct device *dev, size_t size, dma_addr_t *handle, gfp_
 }
 EXPORT_SYMBOL(dma_alloc_writethrough);
 
-
-#ifdef CONFIG_FSL_UTP
 /*
  *  Allocate noncacheable memory space and return both the kernel remapped
  * virtual and bus address for that space.
@@ -400,7 +398,6 @@ dma_alloc_noncacheable(struct device *dev, size_t size, dma_addr_t *handle, gfp_
 			  pgprot_noncached(pgprot_kernel));
 }
 EXPORT_SYMBOL(dma_alloc_noncacheable);
-#endif
 
 static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
 		    void *cpu_addr, dma_addr_t dma_addr, size_t size)
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index ee4ea63d9fdc..93347eb14c69 100755
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -225,10 +225,18 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 	    IS_ERR(parent) || clk->set_parent == NULL)
 		return ret;
 
-	if (clk->usecount)
-		clk_enable(parent);
-
 	mutex_lock(&clocks_mutex);
+
+	if (clk->usecount) {
+		if (in_interrupt()) {
+			printk(KERN_ERR " clk_enable cannot be called in an interrupt context\n");
+			dump_stack();
+			mutex_unlock(&clocks_mutex);
+			BUG();
+		}
+		__clk_enable(parent);
+	}
+
 	ret = clk->set_parent(clk, parent);
 	if (ret == 0) {
 		old = clk->parent;
@@ -236,10 +244,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 	} else {
 		old = parent;
 	}
-	mutex_unlock(&clocks_mutex);
-
 	if (clk->usecount)
-		clk_disable(old);
+		__clk_disable(old);
+
+	mutex_unlock(&clocks_mutex);
 
 	return ret;
 }
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 549f5c5c7ce0..bdc89f007349 100755
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -58,13 +58,7 @@ extern struct regulator *soc_regulator;
 extern struct regulator *pu_regulator;
 extern int dvfs_core_is_active;
 extern struct cpu_op *(*get_cpu_op)(int *op);
-extern int low_bus_freq_mode;
-extern int audio_bus_freq_mode;
-extern int high_bus_freq_mode;
-extern int set_low_bus_freq(void);
-extern int set_high_bus_freq(int high_bus_speed);
-extern int low_freq_bus_used(void);
-extern struct mutex bus_freq_mutex;
+extern void bus_freq_update(struct clk *clk, bool flag);
 
 int set_cpu_freq(int freq)
 {
@@ -95,24 +89,25 @@ int set_cpu_freq(int freq)
 #endif
 	/*Set the voltage for the GP domain. */
 	if (freq > org_cpu_rate) {
-		mutex_lock(&bus_freq_mutex);
-		if (low_bus_freq_mode || audio_bus_freq_mode) {
-			mutex_unlock(&bus_freq_mutex);
-			set_high_bus_freq(0);
-		} else
-			mutex_unlock(&bus_freq_mutex);
-		if (freq == cpu_op_tbl[0].cpu_rate && !IS_ERR(soc_regulator) && !IS_ERR(pu_regulator)) {
-			ret = regulator_set_voltage(soc_regulator, soc_volt,
-							soc_volt);
-			if (ret < 0) {
-				printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE!!!!\n");
-				return ret;
+		/* Check if the bus freq needs to be increased first */
+		bus_freq_update(cpu_clk, true);
+
+		if (freq == cpu_op_tbl[0].cpu_rate) {
+			if (!IS_ERR(soc_regulator)) {
+				ret = regulator_set_voltage(soc_regulator, soc_volt,
+								soc_volt);
+				if (ret < 0) {
+					printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE!!!!\n");
+					return ret;
+				}
 			}
-			ret = regulator_set_voltage(pu_regulator, pu_volt,
-							pu_volt);
-			if (ret < 0) {
-				printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n");
-				return ret;
+			if (!IS_ERR(pu_regulator)) {
+				ret = regulator_set_voltage(pu_regulator, pu_volt,
+								pu_volt);
+				if (ret < 0) {
+					printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n");
+					return ret;
+				}
 			}
 			soc_regulator_set = 1;
 		}
@@ -137,26 +132,27 @@ int set_cpu_freq(int freq)
 			printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n");
 			return ret;
 		}
-		if (soc_regulator_set && soc_regulator && pu_regulator) {
-			ret = regulator_set_voltage(soc_regulator, soc_volt,
-							soc_volt);
-			if (ret < 0) {
-				printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE BACK!!!!\n");
-				return ret;
+		if (soc_regulator_set) {
+			if (!IS_ERR(soc_regulator)) {
+				ret = regulator_set_voltage(soc_regulator, soc_volt,
+								soc_volt);
+				if (ret < 0) {
+					printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE BACK!!!!\n");
+					return ret;
+				}
 			}
-			ret = regulator_set_voltage(pu_regulator, pu_volt,
-							pu_volt);
-			if (ret < 0) {
-				printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n");
-				return ret;
+			if (!IS_ERR(pu_regulator)) {
+				ret = regulator_set_voltage(pu_regulator, pu_volt,
+								pu_volt);
+				if (ret < 0) {
+					printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n");
+					return ret;
+				}
 			}
 			soc_regulator_set = 0;
 		}
-		mutex_lock(&bus_freq_mutex);
-		if (low_freq_bus_used() &&
-			!(low_bus_freq_mode || audio_bus_freq_mode))
-			set_low_bus_freq();
-		mutex_unlock(&bus_freq_mutex);
+		/* Check if the bus freq can be decreased.*/
+		bus_freq_update(cpu_clk, false);
 	}
 
 	return ret;
@@ -252,8 +248,11 @@ void mxc_cpufreq_suspend(void)
 	pre_suspend_rate = clk_get_rate(cpu_clk);
 	/*set flag and raise up cpu frequency if needed*/
 	cpu_freq_suspend_in = 1;
-	if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000))
+	if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) {
 			set_cpu_freq(imx_freq_table[0].frequency * 1000);
+			loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+				pre_suspend_rate / 1000, imx_freq_table[0].frequency);
+	}
 	cpu_freq_suspend_in = 2;
 	mutex_unlock(&set_cpufreq_lock);
 
@@ -263,8 +262,11 @@ void mxc_cpufreq_resume(void)
 {
 	mutex_lock(&set_cpufreq_lock);
 	cpu_freq_suspend_in = 1;
-	if (clk_get_rate(cpu_clk) != pre_suspend_rate)
+	if (clk_get_rate(cpu_clk) != pre_suspend_rate) {
 		set_cpu_freq(pre_suspend_rate);
+		loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+			imx_freq_table[0].frequency, pre_suspend_rate / 1000);
+	}
 	cpu_freq_suspend_in = 0;
 	mutex_unlock(&set_cpufreq_lock);
 }
@@ -274,16 +276,22 @@ void mxc_cpufreq_resume(void)
 static int mxc_cpufreq_suspend(struct cpufreq_policy *policy)
 {
 	pre_suspend_rate = clk_get_rate(cpu_clk);
-	if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000))
+	if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) {
 		set_cpu_freq(imx_freq_table[0].frequency * 1000);
+		loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+			pre_suspend_rate / 1000, imx_freq_table[0].frequency);
+	}
 
 	return 0;
 }
 
 static int mxc_cpufreq_resume(struct cpufreq_policy *policy)
 {
-	if (clk_get_rate(cpu_clk) != pre_suspend_rate)
+	if (clk_get_rate(cpu_clk) != pre_suspend_rate) {
 		set_cpu_freq(pre_suspend_rate);
+		loops_per_jiffy = cpufreq_scale(loops_per_jiffy,
+			imx_freq_table[0].frequency, pre_suspend_rate / 1000);
+	}
 	return 0;
 }
 #endif
diff --git a/arch/arm/plat-mxc/devices/platform-imx-pxp.c b/arch/arm/plat-mxc/devices/platform-imx-pxp.c
index 3ae3e4880e1d..418489e1c4ea 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-pxp.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-pxp.c
@@ -64,3 +64,8 @@ struct platform_device *__init imx_add_imx_pxp_client()
 		NULL, 0, NULL, 0);
 }
 
+struct platform_device *__init imx_add_imx_pxp_v4l2()
+{
+    return imx_add_platform_device_dmamask("pxp-v4l2", -1,
+		NULL, 0, NULL, 0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
index bdb6b252b356..f2bb01c6a8c9 100755
--- a/arch/arm/plat-mxc/include/mach/arc_otg.h
+++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
@@ -246,6 +246,11 @@ extern void __iomem *imx_otg_base;
 #define PORTSC_PTS_SERIAL		(3 << 30)	/* serial */
 #define PORTSC_STS			(1 << 29)	/* serial xcvr select */
 #define PORTSC_PTW                      (1 << 28)       /* UTMI width */
+#define PORTSC_PORT_SPEED_FULL		(0x0<<26)
+#define PORTSC_PORT_SPEED_LOW		       (0x1<<26)
+#define PORTSC_PORT_SPEED_HIGH		(0x2<<26)
+#define PORTSC_PORT_SPEED_UNDEF		(0x3<<26)
+#define PORTSC_PORT_SPEED_MASK		(0x3<<26)
 #define PORTSC_HSIC_MODE                (1 << 25)       /* Only for HSIC */
 #define PORTSC_PHCD                     (1 << 23)       /* Low Power Suspend */
 #define PORTSC_WKDC			(1 << 21)	/* wakeup on discnt*/
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 4512751cbd11..99ef8abee1e3 100755
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -468,6 +468,7 @@ struct imx_pxp_data {
 struct platform_device *__init imx_add_imx_pxp(
 	const struct imx_pxp_data *data);
 struct platform_device *__init imx_add_imx_pxp_client(void);
+struct platform_device *__init imx_add_imx_pxp_v4l2(void);
 
 #include <linux/fsl_devices.h>
 struct imx_elcdif_data {
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
index 4d0fa922c742..df528bc4f028 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
@@ -73,6 +73,10 @@
 #define MX6DL_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED |	\
 		PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define MX6DL_ADU_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+		PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN |		\
+		PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
 #define MX6DL_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define MX6DL_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
 #define MX6DL_GPMI_PAD_CTRL2 (MX6DL_GPMI_PAD_CTRL0 | MX6DL_GPMI_PAD_CTRL1)
@@ -294,7 +298,7 @@
 #define MX6DL_PAD_CSI0_DAT5__KPP_ROW_5                                         \
 		IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                                   \
-		IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, MX6DL_ADU_PAD_CTRL)
 #define MX6DL_PAD_CSI0_DAT5__GPIO_5_23                                         \
 		IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44                                \
@@ -328,7 +332,7 @@
 #define MX6DL_PAD_CSI0_DAT7__KPP_ROW_6                                         \
 		IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                                   \
-		IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, MX6DL_ADU_PAD_CTRL)
 #define MX6DL_PAD_CSI0_DAT7__GPIO_5_25                                         \
 		IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46                                \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index 7618975d38a3..9226af18f7ee 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -85,6 +85,10 @@
 		PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
 		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW)
 
+#define MX6Q_ADU_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+		PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN |		\
+		PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
 #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1				\
 		IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
 #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0				\
@@ -6177,7 +6181,8 @@
 #define  MX6Q_PAD_CSI0_DAT5__KPP_ROW_5		\
 		(_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		\
-		(_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | \
+					MUX_PAD_CTRL(MX6Q_ADU_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT5__GPIO_5_23		\
 		(_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
 #define  MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44		\
@@ -6211,7 +6216,8 @@
 #define  MX6Q_PAD_CSI0_DAT7__KPP_ROW_6		\
 		(_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		\
-		(_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | \
+					MUX_PAD_CTRL(MX6Q_ADU_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT7__GPIO_5_25		\
 		(_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
 #define  MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46		\
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h
index 52442b5ef561..296df42d3ef7 100755
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h
@@ -74,9 +74,20 @@
 
 #define MX6SL_TSPAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
 				PAD_CTL_PUS_47K_UP)
+#define MX6SL_ADU_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+		PAD_CTL_DSE_40ohm | PAD_CTL_PUS_100K_DOWN |		\
+		PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define MX6SL_PAD_AUD_MCLK		0x02A4
+#define MX6SL_PAD_AUD_RXD		0x02AC
+#define MX6SL_PAD_AUD_TXC		0x02B4
+#define MX6SL_PAD_AUD_TXD		0x02B8
+#define MX6SL_PAD_AUD_TXFS		0x02BC
+#define MX6SL_PAD_HSIC_DAT		0x0444
+#define MX6SL_PAD_HSIC_STROBE		0x0448
 
 #define MX6SL_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT                              \
-		IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
 #define MX6SL_PAD_AUD_MCLK__PWM4_PWMO                                         \
 		IOMUX_PAD(0x02A4, 0x004C, 1, 0x0000, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY                                        \
@@ -112,7 +123,7 @@
 		IOMUX_PAD(0x02A8, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_AUD_RXD__AUDMUX_AUD3_RXD                                    \
-		IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
 #define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI                                        \
 		IOMUX_PAD(0x02AC, 0x0054, 1, 0x06BC, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_AUD_RXD__UART4_TXD                                          \
@@ -150,7 +161,7 @@
 		IOMUX_PAD(0x02B0, 0x0058, 7, 0x07EC, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC                                    \
-		IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
 #define MX6SL_PAD_AUD_TXC__ECSPI3_MISO                                        \
 		IOMUX_PAD(0x02B4, 0x005C, 1, 0x06B8, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_AUD_TXC__UART4_TXD                                          \
@@ -169,7 +180,7 @@
 		IOMUX_PAD(0x02B4, 0x005C, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_AUD_TXD__AUDMUX_AUD3_TXD                                    \
-		IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
 #define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK                                        \
 		IOMUX_PAD(0x02B8, 0x0060, 1, 0x06B0, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_AUD_TXD__UART4_CTS                                          \
@@ -188,7 +199,7 @@
 		IOMUX_PAD(0x02B8, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS                                  \
-		IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, MX6SL_ADU_PAD_CTRL)
 #define MX6SL_PAD_AUD_TXFS__PWM3_PWMO                                         \
 		IOMUX_PAD(0x02BC, 0x0064, 1, 0x0000, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_AUD_TXFS__UART4_CTS                                         \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 1ff80f9fff55..c53028f984d1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -2,6 +2,8 @@
  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
  *			<armlinux@phytec.de>
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -89,6 +91,11 @@ typedef u64 iomux_v3_cfg_t;
 #define NO_PAD_I			0
 #define NO_MUX_I			0
 #ifdef CONFIG_SOC_IMX6Q
+#define PAD_CTL_LVE			(1 << 22)
+#define PAD_CTL_LVE_MASK		(1 << 22)
+#define PAD_CTL_DDR_SEL_LPDDR2		(2 << 18)
+#define PAD_CTL_DDR_SEL_DDR3		(3 << 18)
+#define PAD_CTL_DDR_SEL_MASK		(3 << 18)
 #define PAD_CTL_HYS			(1 << 16)
 
 #define PAD_CTL_PUS_100K_DOWN		(0 << 14)
@@ -173,5 +180,11 @@ void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
  * Set bits for general purpose registers
  */
 void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value);
+
+/*
+ * Set special bits for iomux registers, such as LVE bit, DDR_SEL bits
+ */
+void mxc_iomux_set_specialbits_register(u32 pad_addr, u32 value, u32 mask);
+
 #endif /* __MACH_IOMUX_V3_H__*/
 
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 82457673c5ad..23159090ace8 100755
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -94,6 +94,8 @@ extern unsigned int system_rev;
 	board_is_rev(IMX_BOARD_REV_2))
 #define board_is_mx6q_sabre_auto() (cpu_is_mx6q() && \
 	board_is_rev(IMX_BOARD_REV_3))
+#define board_is_mx6sl_evk() (cpu_is_mx6sl() && \
+	board_is_rev(IMX_BOARD_REV_3))
 
 #define board_is_mx6_unknown() \
 	board_is_rev(IMX_BOARD_REV_1)
@@ -247,6 +249,7 @@ extern unsigned int __mxc_cpu_type;
 struct cpu_op {
 	u32 pll_reg;
 	u32 pll_rate;
+	u32 pll_lpm_rate;
 	u32 cpu_rate;
 	u32 pdr0_reg;
 	u32 pdf;
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index f7bc8718684b..85b7e176981b 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
  *                       <armlinux@phytec.de>
@@ -86,6 +86,15 @@ void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int valu
 	__raw_writel(reg, base + group * 4);
 }
 EXPORT_SYMBOL(mxc_iomux_set_gpr_register);
+void mxc_iomux_set_specialbits_register(u32 pad_addr, u32 value, u32 mask)
+{
+	u32 reg;
+	reg = __raw_readl(base + pad_addr);
+	reg &= ~mask;
+	reg |= value;
+	__raw_writel(reg, base + pad_addr);
+}
+EXPORT_SYMBOL(mxc_iomux_set_specialbits_register);
 
 void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
 {
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
index 97d963a54a54..d85d8d663571 100755
--- a/arch/arm/plat-mxc/usb_common.c
+++ b/arch/arm/plat-mxc/usb_common.c
@@ -53,7 +53,9 @@ typedef void (*driver_vbus_func)(bool);
 
 void __iomem *imx_otg_base;
 static  driver_vbus_func s_driver_vbus;
+static int stop_mode_refcount;
 
+DEFINE_MUTEX(usb_common_mutex);
 EXPORT_SYMBOL(imx_otg_base);
 
 #define MXC_NUMBER_USB_TRANSCEIVER 6
@@ -71,6 +73,41 @@ bool usb_icbug_swfix_need(void)
 }
 EXPORT_SYMBOL(usb_icbug_swfix_need);
 
+/*
+  * The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1 is off.
+  * So we should keep the 1V1 active during the system suspend if any USB host enabled.
+  * Set stop_mode_config when any USB host enabled by default, it will impact on system power.
+  * #define DISABLE_STOP_MODE will disable the feature.
+  */
+#ifndef DISABLE_STOP_MODE
+int usb_stop_mode_refcount(bool enable)
+{
+	if (enable)
+		stop_mode_refcount++;
+	else
+		stop_mode_refcount--;
+	return stop_mode_refcount;
+}
+#else
+int usb_stop_mode_refcount(bool enable)
+{
+	return 0;
+}
+#endif
+EXPORT_SYMBOL(usb_stop_mode_refcount);
+
+void usb_stop_mode_lock(void)
+{
+	mutex_lock(&usb_common_mutex);
+}
+EXPORT_SYMBOL(usb_stop_mode_lock);
+
+void usb_stop_mode_unlock(void)
+{
+	mutex_unlock(&usb_common_mutex);
+}
+EXPORT_SYMBOL(usb_stop_mode_unlock);
+
 void mx6_set_host1_vbus_func(driver_vbus_func driver_vbus)
 {
 	s_driver_vbus = driver_vbus;
diff --git a/arch/arm/plat-mxc/usb_wakeup.c b/arch/arm/plat-mxc/usb_wakeup.c
index e67c2219e52d..5d31d3621205 100755
--- a/arch/arm/plat-mxc/usb_wakeup.c
+++ b/arch/arm/plat-mxc/usb_wakeup.c
@@ -47,6 +47,20 @@ static void wakeup_clk_gate(struct fsl_usb2_wakeup_platform_data *pdata, bool on
 	if (pdata->usb_clock_for_pm)
 		pdata->usb_clock_for_pm(on);
 }
+static bool phy_in_lowpower_mode(struct fsl_usb2_platform_data *pdata)
+{
+	unsigned long flags;
+	bool ret = true;
+
+	spin_lock_irqsave(&pdata->lock, flags);
+
+	if (!pdata->lowpower)
+		ret = false;
+
+	spin_unlock_irqrestore(&pdata->lock, flags);
+
+	return ret;
+}
 
 static bool usb2_is_in_lowpower(struct wakeup_ctrl *ctrl)
 {
@@ -54,8 +68,8 @@ static bool usb2_is_in_lowpower(struct wakeup_ctrl *ctrl)
 	struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata;
 	/* all the usb module related the wakeup is in lowpower mode */
 	for (i = 0; i < 3; i++) {
-		if (pdata->usb_pdata[i]) {
-			if (pdata->usb_pdata[i]->phy_lowpower_suspend && !pdata->usb_pdata[i]->lowpower)
+		if (pdata->usb_pdata[i] && pdata->usb_pdata[i]->phy_lowpower_suspend) {
+			if (!phy_in_lowpower_mode(pdata->usb_pdata[i]))
 				return false;
 		}
 	}
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 5b48a6bdc8f6..88210d976378 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1118,4 +1118,5 @@ mx6q_sabrelite		MACH_MX6Q_SABRELITE	MX6Q_SABRELITE		3769
 mx6q_sabresd		MACH_MX6Q_SABRESD	MX6Q_SABRESD		3980
 mx6q_arm2		MACH_MX6Q_ARM2		MX6Q_ARM2		3837
 mx6sl_arm2		MACH_MX6SL_ARM2		MX6SL_ARM2		4091
+mx6sl_evk		MACH_MX6SL_EVK		MX6SL_EVK		4307
 
diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c
index ceb72edbd39e..87b8f558ae8c 100644
--- a/drivers/dma/pxp/pxp_dma_v2.c
+++ b/drivers/dma/pxp/pxp_dma_v2.c
@@ -339,7 +339,14 @@ static void pxp_set_outbuf(struct pxps *pxp)
 		     BF_PXP_OUT_LRC_Y(out_params->height - 1),
 		     pxp->base + HW_PXP_OUT_LRC);
 
-	__raw_writel(out_params->stride, pxp->base + HW_PXP_OUT_PITCH);
+	if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24)
+		__raw_writel(out_params->stride << 2,
+				pxp->base + HW_PXP_OUT_PITCH);
+	else if (out_params->pixel_fmt == PXP_PIX_FMT_RGB565)
+		__raw_writel(out_params->stride << 1,
+				pxp->base + HW_PXP_OUT_PITCH);
+	else
+		__raw_writel(out_params->stride, pxp->base + HW_PXP_OUT_PITCH);
 }
 
 static void pxp_set_s0colorkey(struct pxps *pxp)
@@ -390,6 +397,13 @@ static void pxp_set_oln(int layer_no, struct pxps *pxp)
 	__raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width) |
 		     BF_PXP_OUT_AS_LRC_Y(olparams_data->height),
 		     pxp->base + HW_PXP_OUT_AS_LRC);
+
+	if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24)
+		__raw_writel(olparams_data->width << 2,
+				pxp->base + HW_PXP_AS_PITCH);
+	else
+		__raw_writel(olparams_data->width << 1,
+				pxp->base + HW_PXP_AS_PITCH);
 }
 
 static void pxp_set_olparam(int layer_no, struct pxps *pxp)
@@ -704,8 +718,9 @@ static void pxp_set_s0buf(struct pxps *pxp)
 		__raw_writel(V, pxp->base + HW_PXP_PS_VBUF);
 	}
 
-	/* TODO: only support RGB565, Y8, Y4 */
-	if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY)
+	/* TODO: only support RGB565, Y8, Y4, YUV420 */
+	if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY ||
+	    s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P)
 		__raw_writel(s0_params->width, pxp->base + HW_PXP_PS_PITCH);
 	else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04)
 		__raw_writel(s0_params->width >> 1, pxp->base + HW_PXP_PS_PITCH);
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index a01553aa0ffc..e0b1633ef218 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -651,7 +651,7 @@ config VIDEO_MXS_PXP
 
 config VIDEO_MXC_PXP_V4L2
         tristate "MXC PxP V4L2 driver"
-        depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MX5
+        depends on VIDEO_DEV && VIDEO_V4L2 && (ARCH_MX5 || SOC_IMX6SL)
         select VIDEOBUF_DMA_CONTIG
         ---help---
           This is a video4linux driver for the Freescale PxP
diff --git a/drivers/media/video/mxc/capture/Makefile b/drivers/media/video/mxc/capture/Makefile
index 04b715352886..bdef5b401485 100644
--- a/drivers/media/video/mxc/capture/Makefile
+++ b/drivers/media/video/mxc/capture/Makefile
@@ -1,7 +1,7 @@
 ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y)
 	obj-$(CONFIG_VIDEO_MXC_CAMERA) += mxc_v4l2_capture.o
 	obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o
-	obj-$(CONFIG_MXC_IPU_DEVICE_QUEUE_SDC) += ipu_fg_overlay_sdc.o ipu_prp_vf_sdc_bg.o
+	obj-$(CONFIG_MXC_IPU_DEVICE_QUEUE_SDC) += ipu_fg_overlay_sdc.o ipu_bg_overlay_sdc.o
 	obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o
 	obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o
 endif
diff --git a/drivers/media/video/mxc/capture/ipu_bg_overlay_sdc.c b/drivers/media/video/mxc/capture/ipu_bg_overlay_sdc.c
new file mode 100644
index 000000000000..1a0229720640
--- /dev/null
+++ b/drivers/media/video/mxc/capture/ipu_bg_overlay_sdc.c
@@ -0,0 +1,551 @@
+
+/*
+ * Copyright 2004-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_bg_overlay_sdc_bg.c
+ *
+ * @brief IPU Use case for PRP-VF back-ground
+ *
+ * @ingroup IPU
+ */
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <linux/ipu.h>
+#include <mach/mipi_csi2.h>
+#include "mxc_v4l2_capture.h"
+#include "ipu_prp_sw.h"
+
+static int csi_buffer_num;
+static u32 bpp, csi_mem_bufsize = 3;
+static u32 out_format;
+static struct ipu_soc *disp_ipu;
+static u32 offset;
+
+static void csi_buf_work_func(struct work_struct *work)
+{
+	int err = 0;
+	cam_data *cam =
+		container_of(work, struct _cam_data, csi_work_struct);
+
+	struct ipu_task	task;
+	memset(&task, 0, sizeof(task));
+
+	if (csi_buffer_num)
+		task.input.paddr = cam->vf_bufs[0];
+	else
+		task.input.paddr = cam->vf_bufs[1];
+	task.input.width = cam->crop_current.width;
+	task.input.height = cam->crop_current.height;
+	task.input.format = IPU_PIX_FMT_UYVY;
+
+	task.output.paddr = offset;
+	task.output.width = cam->overlay_fb->var.xres;
+	task.output.height = cam->overlay_fb->var.yres;
+	task.output.format = out_format;
+	task.output.rotate = cam->rotation;
+	task.output.crop.pos.x = cam->win.w.left;
+	task.output.crop.pos.y = cam->win.w.top;
+	if (cam->win.w.width > 1024 || cam->win.w.height > 1024) {
+		task.output.crop.w = cam->overlay_fb->var.xres;
+		task.output.crop.h = cam->overlay_fb->var.yres;
+	} else {
+		task.output.crop.w = cam->win.w.width;
+		task.output.crop.h = cam->win.w.height;
+	}
+again:
+	err = ipu_check_task(&task);
+	if (err != IPU_CHECK_OK) {
+		if (err > IPU_CHECK_ERR_MIN) {
+			if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
+				task.input.crop.w -= 8;
+				goto again;
+			}
+			if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
+				task.input.crop.h -= 8;
+				goto again;
+			}
+			if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
+					task.output.width -= 8;
+					task.output.crop.w = task.output.width;
+				goto again;
+			}
+			if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
+					task.output.height -= 8;
+					task.output.crop.h = task.output.height;
+				goto again;
+			}
+			printk(KERN_ERR "check ipu taks fail\n");
+			return;
+		}
+		printk(KERN_ERR "check ipu taks fail\n");
+		return;
+	}
+	err = ipu_queue_task(&task);
+	if (err < 0)
+		printk(KERN_ERR "queue ipu task error\n");
+}
+
+static void get_disp_ipu(cam_data *cam)
+{
+	if (cam->output > 2)
+		disp_ipu = ipu_get_soc(1); /* using DISP4 */
+	else
+		disp_ipu = ipu_get_soc(0);
+}
+
+
+/*!
+ * csi ENC callback function.
+ *
+ * @param irq       int irq line
+ * @param dev_id    void * device id
+ *
+ * @return status   IRQ_HANDLED for handled
+ */
+static irqreturn_t csi_enc_callback(int irq, void *dev_id)
+{
+	cam_data *cam = (cam_data *) dev_id;
+
+	ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num);
+	schedule_work(&cam->csi_work_struct);
+	csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0;
+	return IRQ_HANDLED;
+}
+
+static int csi_enc_setup(cam_data *cam)
+{
+	ipu_channel_params_t params;
+	u32 pixel_fmt;
+	int err = 0, sensor_protocol = 0;
+#ifdef CONFIG_MXC_MIPI_CSI2
+	void *mipi_csi2_info;
+	int ipu_id;
+	int csi_id;
+#endif
+
+	if (!cam) {
+		printk(KERN_ERR "cam private is NULL\n");
+		return -ENXIO;
+	}
+
+	memset(&params, 0, sizeof(ipu_channel_params_t));
+	params.csi_mem.csi = cam->csi;
+
+	sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
+	switch (sensor_protocol) {
+	case IPU_CSI_CLK_MODE_GATED_CLK:
+	case IPU_CSI_CLK_MODE_NONGATED_CLK:
+	case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
+	case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
+	case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
+		params.csi_mem.interlaced = false;
+		break;
+	case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
+	case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
+	case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
+		params.csi_mem.interlaced = true;
+		break;
+	default:
+		printk(KERN_ERR "sensor protocol unsupported\n");
+		return -EINVAL;
+	}
+
+	ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_ENC, cam->csi, true, true);
+
+#ifdef CONFIG_MXC_MIPI_CSI2
+	mipi_csi2_info = mipi_csi2_get_info();
+
+	if (mipi_csi2_info) {
+		if (mipi_csi2_get_status(mipi_csi2_info)) {
+			ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
+			csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
+
+			if (cam->ipu == ipu_get_soc(ipu_id)
+				&& cam->csi == csi_id) {
+				params.csi_mem.mipi_en = true;
+				params.csi_mem.mipi_vc =
+				mipi_csi2_get_virtual_channel(mipi_csi2_info);
+				params.csi_mem.mipi_id =
+				mipi_csi2_get_datatype(mipi_csi2_info);
+
+				mipi_csi2_pixelclk_enable(mipi_csi2_info);
+			} else {
+				params.csi_mem.mipi_en = false;
+				params.csi_mem.mipi_vc = 0;
+				params.csi_mem.mipi_id = 0;
+			}
+		} else {
+			params.csi_mem.mipi_en = false;
+			params.csi_mem.mipi_vc = 0;
+			params.csi_mem.mipi_id = 0;
+		}
+	} else {
+		printk(KERN_ERR "Fail to get mipi_csi2_info!\n");
+		return -EPERM;
+	}
+#endif
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0],
+				  (dma_addr_t) cam->vf_bufs[0]);
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1],
+				  (dma_addr_t) cam->vf_bufs[1]);
+	}
+	csi_mem_bufsize = cam->crop_current.width * cam->crop_current.height * 2;
+	cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize);
+	cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
+							   cam->vf_bufs_size[0],
+							   (dma_addr_t *) &
+							   cam->vf_bufs[0],
+							   GFP_DMA |
+							   GFP_KERNEL);
+	if (cam->vf_bufs_vaddr[0] == NULL) {
+		printk(KERN_ERR "Error to allocate vf buffer\n");
+		err = -ENOMEM;
+		goto out_2;
+	}
+	cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize);
+	cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
+							   cam->vf_bufs_size[1],
+							   (dma_addr_t *) &
+							   cam->vf_bufs[1],
+							   GFP_DMA |
+							   GFP_KERNEL);
+	if (cam->vf_bufs_vaddr[1] == NULL) {
+		printk(KERN_ERR "Error to allocate vf buffer\n");
+		err = -ENOMEM;
+		goto out_1;
+	}
+	pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
+
+	err = ipu_init_channel(cam->ipu, CSI_MEM, &params);
+	if (err != 0) {
+		printk(KERN_ERR "ipu_init_channel %d\n", err);
+		goto out_1;
+	}
+
+	pixel_fmt = IPU_PIX_FMT_UYVY;
+	err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
+				      pixel_fmt, cam->crop_current.width,
+				      cam->crop_current.height,
+				      cam->crop_current.width, IPU_ROTATE_NONE,
+				      cam->vf_bufs[0], cam->vf_bufs[1], 0,
+				      cam->offset.u_offset, cam->offset.u_offset);
+	if (err != 0) {
+		printk(KERN_ERR "CSI_MEM output buffer\n");
+		goto out_1;
+	}
+	err = ipu_enable_channel(cam->ipu, CSI_MEM);
+	if (err < 0) {
+		printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
+		goto out_1;
+	}
+
+	csi_buffer_num = 0;
+
+	ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
+	ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1);
+	return err;
+out_1:
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0],
+				  (dma_addr_t) cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1],
+				  (dma_addr_t) cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+out_2:
+	return err;
+}
+
+/*!
+ * Enable encoder task
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int csi_enc_enabling_tasks(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
+	err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
+			      csi_enc_callback, 0, "Mxc Camera", cam);
+	if (err != 0) {
+		printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n");
+		return err;
+	}
+
+	INIT_WORK(&cam->csi_work_struct, csi_buf_work_func);
+
+	err = csi_enc_setup(cam);
+	if (err != 0) {
+		printk(KERN_ERR "csi_enc_setup %d\n", err);
+		goto out1;
+	}
+
+	return err;
+out1:
+	ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
+	return err;
+}
+
+/*!
+ * bg_overlay_start - start the overlay task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int bg_overlay_start(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+	int err = 0;
+
+	if (!cam) {
+		printk(KERN_ERR "private is NULL\n");
+		return -EIO;
+	}
+
+	if (cam->overlay_active == true) {
+		pr_debug("already start.\n");
+		return 0;
+	}
+
+	get_disp_ipu(cam);
+
+	out_format = cam->v4l2_fb.fmt.pixelformat;
+	if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) {
+		bpp = 3, csi_mem_bufsize = 3;
+		pr_info("BGR24\n");
+	} else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) {
+		bpp = 2, csi_mem_bufsize = 2;
+		pr_info("RGB565\n");
+	} else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) {
+		bpp = 4, csi_mem_bufsize = 4;
+		pr_info("BGR32\n");
+	} else {
+		printk(KERN_ERR
+		       "unsupported fix format from the framebuffer.\n");
+		return -EINVAL;
+	}
+
+	offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top +
+	    csi_mem_bufsize * cam->win.w.left;
+
+	if (cam->v4l2_fb.base == 0) {
+		printk(KERN_ERR "invalid frame buffer address.\n");
+	} else {
+		offset += (u32) cam->v4l2_fb.base;
+	}
+
+	csi_mem_bufsize = cam->win.w.width * cam->win.w.height * csi_mem_bufsize;
+
+	err = csi_enc_enabling_tasks(cam);
+	if (err != 0) {
+		printk(KERN_ERR "Error csi enc enable fail\n");
+		return err;
+	}
+
+	cam->overlay_active = true;
+	return err;
+}
+
+/*!
+ * bg_overlay_stop - stop the overlay task
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ */
+static int bg_overlay_stop(void *private)
+{
+	int err = 0;
+	cam_data *cam = (cam_data *) private;
+#ifdef CONFIG_MXC_MIPI_CSI2
+	void *mipi_csi2_info;
+	int ipu_id;
+	int csi_id;
+#endif
+
+	if (cam->overlay_active == false)
+		return 0;
+
+	ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
+
+	err = ipu_disable_channel(cam->ipu, CSI_MEM, true);
+
+	ipu_uninit_channel(cam->ipu, CSI_MEM);
+
+	csi_buffer_num = 0;
+
+#ifdef CONFIG_MXC_MIPI_CSI2
+	mipi_csi2_info = mipi_csi2_get_info();
+
+	if (mipi_csi2_info) {
+		if (mipi_csi2_get_status(mipi_csi2_info)) {
+			ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
+			csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
+
+			if (cam->ipu == ipu_get_soc(ipu_id)
+				&& cam->csi == csi_id)
+				mipi_csi2_pixelclk_disable(mipi_csi2_info);
+		}
+	} else {
+		printk(KERN_ERR "Fail to get mipi_csi2_info!\n");
+		return -EPERM;
+	}
+#endif
+
+	flush_work_sync(&cam->csi_work_struct);
+	cancel_work_sync(&cam->csi_work_struct);
+	ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_VF, cam->csi, false, false);
+
+	if (cam->vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->vf_bufs_size[0],
+				  cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
+		cam->vf_bufs_vaddr[0] = NULL;
+		cam->vf_bufs[0] = 0;
+	}
+	if (cam->vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->vf_bufs_size[1],
+				  cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
+		cam->vf_bufs_vaddr[1] = NULL;
+		cam->vf_bufs[1] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[0]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[0],
+				  cam->rot_vf_bufs_vaddr[0],
+				  cam->rot_vf_bufs[0]);
+		cam->rot_vf_bufs_vaddr[0] = NULL;
+		cam->rot_vf_bufs[0] = 0;
+	}
+	if (cam->rot_vf_bufs_vaddr[1]) {
+		dma_free_coherent(0, cam->rot_vf_buf_size[1],
+				  cam->rot_vf_bufs_vaddr[1],
+				  cam->rot_vf_bufs[1]);
+		cam->rot_vf_bufs_vaddr[1] = NULL;
+		cam->rot_vf_bufs[1] = 0;
+	}
+
+	cam->overlay_active = false;
+	return err;
+}
+
+/*!
+ * Enable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int bg_overlay_enable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_enable_csi(cam->ipu, cam->csi);
+}
+
+/*!
+ * Disable csi
+ * @param private       struct cam_data * mxc capture instance
+ *
+ * @return  status
+ */
+static int bg_overlay_disable_csi(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	return ipu_disable_csi(cam->ipu, cam->csi);
+}
+
+/*!
+ * function to select bg as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int bg_overlay_sdc_select(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->vf_start_sdc = bg_overlay_start;
+		cam->vf_stop_sdc = bg_overlay_stop;
+		cam->vf_enable_csi = bg_overlay_enable_csi;
+		cam->vf_disable_csi = bg_overlay_disable_csi;
+		cam->overlay_active = false;
+	}
+
+	return 0;
+}
+
+/*!
+ * function to de-select bg as the working path
+ *
+ * @param private    cam_data * mxc v4l2 main structure
+ *
+ * @return  status
+ */
+int bg_overlay_sdc_deselect(void *private)
+{
+	cam_data *cam = (cam_data *) private;
+
+	if (cam) {
+		cam->vf_start_sdc = NULL;
+		cam->vf_stop_sdc = NULL;
+		cam->vf_enable_csi = NULL;
+		cam->vf_disable_csi = NULL;
+	}
+	return 0;
+}
+
+/*!
+ * Init background overlay task.
+ *
+ * @return  Error code indicating success or failure
+ */
+__init int bg_overlay_sdc_init(void)
+{
+	return 0;
+}
+
+/*!
+ * Deinit background overlay task.
+ *
+ * @return  Error code indicating success or failure
+ */
+void __exit bg_overlay_sdc_exit(void)
+{
+}
+
+module_init(bg_overlay_sdc_init);
+module_exit(bg_overlay_sdc_exit);
+
+EXPORT_SYMBOL(bg_overlay_sdc_select);
+EXPORT_SYMBOL(bg_overlay_sdc_deselect);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mxc/capture/ipu_fg_overlay_sdc.c b/drivers/media/video/mxc/capture/ipu_fg_overlay_sdc.c
index 05c88c7d409b..312462ac60e0 100644
--- a/drivers/media/video/mxc/capture/ipu_fg_overlay_sdc.c
+++ b/drivers/media/video/mxc/capture/ipu_fg_overlay_sdc.c
@@ -508,6 +508,8 @@ static int foreground_stop(void *private)
 	}
 #endif
 
+	flush_work_sync(&cam->csi_work_struct);
+	cancel_work_sync(&cam->csi_work_struct);
 	ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_VF, cam->csi, false, false);
 
 	if (cam->vf_bufs_vaddr[0]) {
diff --git a/drivers/media/video/mxc/capture/ipu_prp_sw.h b/drivers/media/video/mxc/capture/ipu_prp_sw.h
index 7cdc521711cb..cba47baa4abe 100644
--- a/drivers/media/video/mxc/capture/ipu_prp_sw.h
+++ b/drivers/media/video/mxc/capture/ipu_prp_sw.h
@@ -29,12 +29,14 @@ int prp_enc_deselect(void *private);
 #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
 int prp_vf_sdc_select(void *private);
 int prp_vf_sdc_deselect(void *private);
+int prp_vf_sdc_select_bg(void *private);
+int prp_vf_sdc_deselect_bg(void *private);
 #else
 int foreground_sdc_select(void *private);
 int foreground_sdc_deselect(void *private);
+int bg_overlay_sdc_select(void *private);
+int bg_overlay_sdc_deselect(void *private);
 #endif
-int prp_vf_sdc_select_bg(void *private);
-int prp_vf_sdc_deselect_bg(void *private);
 int prp_still_select(void *private);
 int prp_still_deselect(void *private);
 
diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
index bddfee530274..423575c9d881 100644
--- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
+++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c
@@ -655,7 +655,11 @@ static int start_preview(cam_data *cam)
 		err = foreground_sdc_select(cam);
 	#endif
 	else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
+	#ifdef CONFIG_MXC_IPU_PRP_VF_SDC
 		err = prp_vf_sdc_select_bg(cam);
+	#else
+		err = bg_overlay_sdc_select(cam);
+	#endif
 	if (err != 0)
 		return err;
 
@@ -714,7 +718,11 @@ static int stop_preview(cam_data *cam)
 		err = foreground_sdc_deselect(cam);
 	#endif
 	else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
+	#ifdef CONFIG_MXC_IPU_PRP_VF_SDC
 		err = prp_vf_sdc_deselect_bg(cam);
+	#else
+		err = bg_overlay_sdc_deselect(cam);
+	#endif
 
 	return err;
 }
diff --git a/drivers/media/video/mxc/capture/ov5642.c b/drivers/media/video/mxc/capture/ov5642.c
index 245a92c15ef1..492748c6cac4 100644
--- a/drivers/media/video/mxc/capture/ov5642.c
+++ b/drivers/media/video/mxc/capture/ov5642.c
@@ -3228,6 +3228,7 @@ err:
 static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
        enum ov5642_mode mode)
 {
+	int ret = 0;
 	bool m_60Hz = false;
 	u16 capture_frame_rate = 50;
 	u16 g_preview_frame_rate = 225;
@@ -3255,7 +3256,10 @@ static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
 	gain = 0;
 	ov5642_read_reg(0x350b, &gain);
 
-	ov5642_init_mode(frame_rate, mode);
+	ret = ov5642_init_mode(frame_rate, mode);
+	if (ret < 0)
+		return ret;
+
 	ret_h = ret_m = ret_l = 0;
 	ov5642_read_reg(0x380e, &ret_h);
 	ov5642_read_reg(0x380f, &ret_l);
@@ -3331,7 +3335,7 @@ static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
 	ov5642_write_reg(0x3500, exposure_high);
 	msleep(500);
 
-	return 0;
+	return ret ;
 }
 
 
diff --git a/drivers/media/video/mxc/output/mxc_pxp_v4l2.c b/drivers/media/video/mxc/output/mxc_pxp_v4l2.c
index a26b5d918a26..a3a8294efb8e 100644
--- a/drivers/media/video/mxc/output/mxc_pxp_v4l2.c
+++ b/drivers/media/video/mxc/output/mxc_pxp_v4l2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -254,10 +254,12 @@ static int pxp_set_fbinfo(struct pxps *pxp)
 
 	fb->fmt.width = fbi->var.xres;
 	fb->fmt.height = fbi->var.yres;
+	pxp->pxp_conf.out_param.stride = fbi->var.xres;
 	if (fbi->var.bits_per_pixel == 16)
 		fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565;
 	else
 		fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24;
+
 	fb->base = (void *)fbi->fix.smem_start;
 
 	return 0;
@@ -293,9 +295,9 @@ static int set_fb_blank(int blank)
 	if (err)
 		return err;
 
-	acquire_console_sem();
+	console_lock();
 	fb_blank(fbi, blank);
-	release_console_sem();
+	console_unlock();
 
 	return err;
 }
@@ -679,7 +681,7 @@ static void pxp_buf_free(struct videobuf_queue *q, struct pxp_buffer *buf)
 	 * This waits until this buffer is out of danger, i.e., until it is no
 	 * longer in STATE_QUEUED or STATE_ACTIVE
 	 */
-	videobuf_waiton(vb, 0, 0);
+	videobuf_waiton(q, vb, 0, 0);
 	if (txd)
 		async_tx_ack(txd);
 
@@ -710,7 +712,7 @@ static int pxp_buf_prepare(struct videobuf_queue *q,
 
 	if (vb->state == VIDEOBUF_NEEDS_INIT) {
 		struct pxp_channel *pchan = pxp->pxp_channel[0];
-		struct scatterlist *sg = &buf->sg;
+		struct scatterlist *sg = &buf->sg[0];
 
 		/* This actually (allocates and) maps buffers */
 		ret = videobuf_iolock(q, vb, NULL);
@@ -1055,7 +1057,8 @@ out:
 				V4L2_BUF_TYPE_VIDEO_OUTPUT,
 				V4L2_FIELD_NONE,
 				sizeof(struct pxp_buffer),
-				pxp);
+				pxp,
+				NULL);
 	dev_dbg(&pxp->pdev->dev, "call pxp_open\n");
 
 	return 0;
diff --git a/drivers/media/video/mxc/output/mxc_vout.c b/drivers/media/video/mxc/output/mxc_vout.c
index 4b3617f89b08..366d27a92286 100644
--- a/drivers/media/video/mxc/output/mxc_vout.c
+++ b/drivers/media/video/mxc/output/mxc_vout.c
@@ -244,7 +244,7 @@ static int alloc_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf)
 {
 
 	buf->vaddr = dma_alloc_coherent(vout->vbq.dev, buf->size, &buf->paddr,
-						GFP_KERNEL);
+						GFP_DMA | GFP_KERNEL);
 	if (!buf->vaddr) {
 		v4l2_err(vout->vfd->v4l2_dev,
 			"cannot get dma buf size:0x%x\n", buf->size);
diff --git a/drivers/mfd/mxc-hdmi-core.c b/drivers/mfd/mxc-hdmi-core.c
index 332843661d98..e9322477ff6d 100644
--- a/drivers/mfd/mxc-hdmi-core.c
+++ b/drivers/mfd/mxc-hdmi-core.c
@@ -63,6 +63,104 @@ int mxc_hdmi_disp_id;
 static struct mxc_edid_cfg hdmi_core_edid_cfg;
 static int hdmi_core_init;
 static unsigned int hdmi_dma_running;
+static struct snd_pcm_substream *hdmi_audio_stream_playback;
+static unsigned int hdmi_cable_state;
+static unsigned int hdmi_blank_state;
+static spinlock_t hdmi_audio_lock, hdmi_blank_state_lock, hdmi_cable_state_lock;
+
+
+unsigned int hdmi_set_cable_state(unsigned int state)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&hdmi_cable_state_lock, flags);
+	hdmi_cable_state = state;
+	spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
+
+	return 0;
+}
+
+unsigned int hdmi_set_blank_state(unsigned int state)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&hdmi_blank_state_lock, flags);
+	hdmi_blank_state = state;
+	spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
+
+	return 0;
+}
+
+static void hdmi_audio_abort_stream(struct snd_pcm_substream *substream)
+{
+	unsigned long flags;
+
+	snd_pcm_stream_lock_irqsave(substream, flags);
+
+	if (snd_pcm_running(substream))
+		snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
+
+	snd_pcm_stream_unlock_irqrestore(substream, flags);
+}
+
+int mxc_hdmi_abort_stream(void)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&hdmi_audio_lock, flags);
+	if (hdmi_audio_stream_playback)
+		hdmi_audio_abort_stream(hdmi_audio_stream_playback);
+	spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+
+	return 0;
+}
+
+static int check_hdmi_state(void)
+{
+	unsigned long flags1, flags2;
+	unsigned int ret;
+
+	spin_lock_irqsave(&hdmi_cable_state_lock, flags1);
+	spin_lock_irqsave(&hdmi_blank_state_lock, flags2);
+
+	ret = hdmi_cable_state && hdmi_blank_state;
+
+	spin_unlock_irqrestore(&hdmi_blank_state_lock, flags2);
+	spin_unlock_irqrestore(&hdmi_cable_state_lock, flags1);
+
+	return ret;
+}
+
+int mxc_hdmi_register_audio(struct snd_pcm_substream *substream)
+{
+	unsigned long flags, flags1;
+	int ret = 0;
+
+	snd_pcm_stream_lock_irqsave(substream, flags);
+
+	if (substream && check_hdmi_state()) {
+		spin_lock_irqsave(&hdmi_audio_lock, flags1);
+		if (hdmi_audio_stream_playback) {
+			pr_err("%s unconsist hdmi auido stream!\n", __func__);
+			ret = -EINVAL;
+		}
+		hdmi_audio_stream_playback = substream;
+		spin_unlock_irqrestore(&hdmi_audio_lock, flags1);
+	} else
+		ret = -EINVAL;
+
+	snd_pcm_stream_unlock_irqrestore(substream, flags);
+
+	return ret;
+}
+
+void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&hdmi_audio_lock, flags);
+	hdmi_audio_stream_playback = NULL;
+	spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+}
 
 u8 hdmi_readb(unsigned int reg)
 {
@@ -466,6 +564,7 @@ static int mxc_hdmi_core_probe(struct platform_device *pdev)
 	struct fsl_mxc_hdmi_core_platform_data *pdata = pdev->dev.platform_data;
 	struct mxc_hdmi_data *hdmi_data;
 	struct resource *res;
+	unsigned long flags;
 	int ret = 0;
 
 #ifdef DEBUG
@@ -495,6 +594,23 @@ static int mxc_hdmi_core_probe(struct platform_device *pdev)
 	spin_lock_init(&irq_spinlock);
 	spin_lock_init(&edid_spinlock);
 
+
+	spin_lock_init(&hdmi_cable_state_lock);
+	spin_lock_init(&hdmi_blank_state_lock);
+	spin_lock_init(&hdmi_audio_lock);
+
+	spin_lock_irqsave(&hdmi_cable_state_lock, flags);
+	hdmi_cable_state = 0;
+	spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
+
+	spin_lock_irqsave(&hdmi_blank_state_lock, flags);
+	hdmi_blank_state = 0;
+	spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
+
+	spin_lock_irqsave(&hdmi_audio_lock, flags);
+	hdmi_audio_stream_playback = NULL;
+	spin_unlock_irqrestore(&hdmi_audio_lock, flags);
+
 	isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr_clk");
 	if (IS_ERR(isfr_clk)) {
 		ret = PTR_ERR(isfr_clk);
diff --git a/drivers/mxc/asrc/mxc_asrc.c b/drivers/mxc/asrc/mxc_asrc.c
index cf41f2994226..62d7ceb0e04f 100644
--- a/drivers/mxc/asrc/mxc_asrc.c
+++ b/drivers/mxc/asrc/mxc_asrc.c
@@ -316,22 +316,22 @@ int asrc_req_pair(int chn_num, enum asrc_pair_index *index)
 	spin_lock_irqsave(&data_lock, lock_flags);
 
 	if (chn_num > 2) {
-		pair = &g_asrc->asrc_pair[ASRC_PAIR_C];
+		pair = &g_asrc->asrc_pair[ASRC_PAIR_B];
 		if (pair->active || (chn_num > pair->chn_max))
 			err = -EBUSY;
 		else {
-			*index = ASRC_PAIR_C;
+			*index = ASRC_PAIR_B;
 			pair->chn_num = chn_num;
 			pair->active = 1;
 		}
 	} else {
 		pair = &g_asrc->asrc_pair[ASRC_PAIR_A];
 		if (pair->active || (pair->chn_max == 0)) {
-			pair = &g_asrc->asrc_pair[ASRC_PAIR_B];
+			pair = &g_asrc->asrc_pair[ASRC_PAIR_C];
 			if (pair->active || (pair->chn_max == 0))
 				err = -EBUSY;
 			else {
-				*index = ASRC_PAIR_B;
+				*index = ASRC_PAIR_C;
 				pair->chn_num = 2;
 				pair->active = 1;
 			}
@@ -583,17 +583,23 @@ int asrc_config_pair(struct asrc_config *config)
 		}
 	}
 
-	if ((config->inclk == INCLK_ASRCK1_CLK) &&
+	if ((config->inclk == INCLK_NONE) &&
 			(config->outclk == OUTCLK_ESAI_TX)) {
 		reg = __raw_readl(g_asrc->vaddr + ASRC_ASRCTR_REG);
-		reg |= (1 << (20 + config->pair));
-		reg |= (0x02 << (13 + (config->pair << 1)));
+		reg &= ~(1 << (20 + config->pair));
+		reg |= (0x03 << (13 + (config->pair << 1)));
 		__raw_writel(reg, g_asrc->vaddr + ASRC_ASRCTR_REG);
 		err = asrc_set_clock_ratio(config->pair,
 					   config->input_sample_rate,
 					   config->output_sample_rate);
 		if (err < 0)
 			return err;
+		err = asrc_set_process_configuration(config->pair,
+						     config->input_sample_rate,
+						     config->
+						     output_sample_rate);
+		if (err < 0)
+			return err;
 	}
 
 	/* Config input and output wordwidth */
@@ -667,12 +673,6 @@ void asrc_start_conv(enum asrc_pair_index index)
 		__raw_writel(reg,
 			     g_asrc->vaddr + ASRC_ASRDIA_REG +
 			     (index << 3));
-		__raw_writel(reg,
-			     g_asrc->vaddr + ASRC_ASRDIA_REG +
-			     (index << 3));
-		__raw_writel(reg,
-			     g_asrc->vaddr + ASRC_ASRDIA_REG +
-			     (index << 3));
 	}
 
 	__raw_writel(0x40, g_asrc->vaddr + ASRC_ASRIER_REG);
@@ -813,9 +813,9 @@ static int mxc_init_asrc(void)
 	/* Enable overflow interrupt */
 	__raw_writel(0x00, g_asrc->vaddr + ASRC_ASRIER_REG);
 
-	/* Default 6: 2: 2 channel assignment */
-	__raw_writel((0x06 << g_asrc->mxc_asrc_data->channel_bits *
-		      2) | (0x02 << g_asrc->mxc_asrc_data->channel_bits) | 0x02,
+	/* Default 2: 6: 2 channel assignment */
+	__raw_writel((0x02 << g_asrc->mxc_asrc_data->channel_bits *
+		      2) | (0x06 << g_asrc->mxc_asrc_data->channel_bits) | 0x02,
 		     g_asrc->vaddr + ASRC_ASRCNCR_REG);
 
 	/* Parameter Registers recommended settings */
@@ -1696,8 +1696,8 @@ static int mxc_asrc_probe(struct platform_device *pdev)
 	g_asrc->dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
 	g_asrc->asrc_pair[0].chn_max = 2;
-	g_asrc->asrc_pair[1].chn_max = 2;
-	g_asrc->asrc_pair[2].chn_max = 6;
+	g_asrc->asrc_pair[1].chn_max = 6;
+	g_asrc->asrc_pair[2].chn_max = 2;
 	g_asrc->asrc_pair[0].overload_error = 0;
 	g_asrc->asrc_pair[1].overload_error = 0;
 	g_asrc->asrc_pair[2].overload_error = 0;
diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
index 8cf0509cfd92..e05a143f41c3 100644
--- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
+++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
@@ -30,6 +30,9 @@
 
 #define _GC_OBJ_ZONE            gcvZONE_COMMAND
 
+#if gcdENABLE_FSCALE_VAL_ADJUST
+extern int thermal_hot;
+#endif
 /******************************************************************************\
 ********************************* Support Code *********************************
 \******************************************************************************/
@@ -1080,6 +1083,24 @@ gckCOMMAND_Commit(
     /* Extract the gckHARDWARE and gckEVENT objects. */
     hardware = Command->kernel->hardware;
 
+#if gcdENABLE_FSCALE_VAL_ADJUST
+    if(hardware->core == gcvCORE_MAJOR){
+        static gctUINT orgFscale,minFscale,maxFscale;
+        static gctBOOL bAlreadyTooHot = gcvFALSE;
+        if((thermal_hot > 0) && (!bAlreadyTooHot)) {
+            gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
+            gckHARDWARE_SetFscaleValue(hardware, minFscale);
+            bAlreadyTooHot = gcvTRUE;
+            gckOS_Print("System is too hot. GPU3D will work at %d/64 clock.\n", minFscale);
+        } else if((!(thermal_hot > 0)) && bAlreadyTooHot) {
+            gckHARDWARE_SetFscaleValue(hardware, orgFscale);
+            gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale);
+            bAlreadyTooHot = gcvFALSE;
+        }
+
+    }
+#endif
+
     /* Check wehther we need to copy the structures or not. */
     gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
 
diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c
index c4eac45a6152..029ab5e9dec7 100644
--- a/drivers/mxc/ipu3/ipu_capture.c
+++ b/drivers/mxc/ipu3/ipu_capture.c
@@ -803,7 +803,7 @@ void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel)
 		dev_err(ipu->dev, "CSI irq %d in use\n", irq);
 		return;
 	}
-	ret = wait_for_completion_timeout(&ipu->csi_comp, msecs_to_jiffies(50));
+	ret = wait_for_completion_timeout(&ipu->csi_comp, msecs_to_jiffies(500));
 	ipu_free_irq(ipu, irq, ipu);
 	dev_dbg(ipu->dev, "CSI stop timeout - %d * 10ms\n", 5 - ret);
 }
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 4e3526c81839..5954eb651ad5 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -176,174 +176,6 @@ static int __devinit ipu_clk_setup_enable(struct ipu_soc *ipu,
 	return 0;
 }
 
-#if 0
-static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-	struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
-	const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
-	u32 status;
-	int i, line;
-
-	for (i = 0;; i++) {
-		if (int_reg[i] == 0)
-			break;
-
-		status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
-		status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
-
-		while ((line = ffs(status))) {
-			line--;
-			status &= ~(1UL << line);
-			line += ipu->irq_start + (int_reg[i] - 1) * 32;
-			generic_handle_irq(line);
-		}
-
-	}
-}
-
-static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-	struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
-	const int int_reg[] = { 5, 6, 9, 10, 0 };
-	u32 status;
-	int i, line;
-
-	for (i = 0;; i++) {
-		if (int_reg[i] == 0)
-			break;
-
-		status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
-		status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
-
-		while ((line = ffs(status))) {
-			line--;
-			status &= ~(1UL << line);
-			line += ipu->irq_start + (int_reg[i] - 1) * 32;
-			generic_handle_irq(line);
-		}
-
-	}
-}
-
-static void ipu_ack_irq(struct irq_data *d)
-{
-	struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
-	unsigned int irq = d->irq - ipu->irq_start;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ipu->ipu_lock, flags);
-	ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32 + 1));
-	spin_unlock_irqrestore(&ipu->ipu_lock, flags);
-}
-
-static void ipu_unmask_irq(struct irq_data *d)
-{
-	struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
-	unsigned int irq = d->irq - ipu->irq_start;
-	unsigned long flags;
-	u32 reg;
-
-	spin_lock_irqsave(&ipu->ipu_lock, flags);
-	reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
-	reg |= 1 << (irq % 32);
-	ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
-	spin_unlock_irqrestore(&ipu->ipu_lock, flags);
-}
-
-static void ipu_mask_irq(struct irq_data *d)
-{
-	struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
-	unsigned int irq = d->irq - ipu->irq_start;
-	unsigned long flags;
-	u32 reg;
-
-	spin_lock_irqsave(&ipu->ipu_lock, flags);
-	reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
-	reg &= ~(1 << (irq % 32));
-	ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
-	spin_unlock_irqrestore(&ipu->ipu_lock, flags);
-}
-
-static struct irq_chip ipu_irq_chip = {
-	.name = "IPU",
-	.irq_ack = ipu_ack_irq,
-	.irq_mask = ipu_mask_irq,
-	.irq_unmask = ipu_unmask_irq,
-};
-
-static void __devinit ipu_irq_setup(struct ipu_soc *ipu)
-{
-	int i;
-
-	for (i = ipu->irq_start; i < ipu->irq_start + MX5_IPU_IRQS; i++) {
-		irq_set_chip_and_handler(i, &ipu_irq_chip, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-		irq_set_chip_data(i, ipu);
-	}
-
-	irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
-	irq_set_handler_data(ipu->irq_sync, ipu);
-	irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
-	irq_set_handler_data(ipu->irq_err, ipu);
-}
-
-int ipu_request_irq(struct ipu_soc *ipu, unsigned int irq,
-		irq_handler_t handler, unsigned long flags,
-		const char *name, void *dev)
-{
-	return request_irq(ipu->irq_start + irq, handler, flags, name, dev);
-}
-EXPORT_SYMBOL_GPL(ipu_request_irq);
-
-void ipu_enable_irq(struct ipu_soc *ipu, unsigned int irq)
-{
-	return enable_irq(ipu->irq_start + irq);
-}
-EXPORT_SYMBOL_GPL(ipu_disable_irq);
-
-void ipu_disable_irq(struct ipu_soc *ipu, unsigned int irq)
-{
-	return disable_irq(ipu->irq_start + irq);
-}
-EXPORT_SYMBOL_GPL(ipu_disable_irq);
-
-void ipu_free_irq(struct ipu_soc *ipu, unsigned int irq, void *dev_id)
-{
-	free_irq(ipu->irq_start + irq, dev_id);
-}
-EXPORT_SYMBOL_GPL(ipu_free_irq);
-
-static irqreturn_t ipu_completion_handler(int irq, void *dev)
-{
-	struct completion *completion = dev;
-
-	complete(completion);
-	return IRQ_HANDLED;
-}
-
-int ipu_wait_for_interrupt(struct ipu_soc *ipu, int interrupt, int timeout_ms)
-{
-	DECLARE_COMPLETION_ONSTACK(completion);
-	int ret;
-
-	ret = ipu_request_irq(ipu, interrupt, ipu_completion_handler,
-			0, NULL, &completion);
-	if (ret) {
-		dev_err(ipu->dev,
-			"ipu request irq %d fail\n", interrupt);
-		return ret;
-	}
-
-	ret = wait_for_completion_timeout(&completion,
-			msecs_to_jiffies(timeout_ms));
-
-	ipu_free_irq(ipu, interrupt, &completion);
-
-	return ret > 0 ? 0 : -ETIMEDOUT;
-}
-EXPORT_SYMBOL_GPL(ipu_wait_for_interrupt);
-#endif
-
 struct ipu_soc *ipu_get_soc(int id)
 {
 	if (id >= MXC_IPU_MAX_NUM)
@@ -416,8 +248,8 @@ static int __devinit ipu_probe(struct platform_device *pdev)
 	if (plat_data->init)
 		plat_data->init(pdev->id);
 
-	ipu->irq_sync = platform_get_irq(pdev, 0);
-	ipu->irq_err = platform_get_irq(pdev, 1);
+	ipu->irq_err = platform_get_irq(pdev, 0);
+	ipu->irq_sync = platform_get_irq(pdev, 1);
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
 	if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
@@ -2549,15 +2381,13 @@ static irqreturn_t ipu_irq_handler(int irq, void *desc)
 	uint32_t int_ctrl;
 	const int err_reg[] = { 5, 6, 9, 10, 0 };
 	const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
-	unsigned long lock_flags;
-	uint32_t oneshot;
+
+	spin_lock(&ipu->spin_lock);
 
 	for (i = 0;; i++) {
 		if (err_reg[i] == 0)
 			break;
 
-		spin_lock_irqsave(&ipu->spin_lock, lock_flags);
-
 		int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
 		int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
 		if (int_stat) {
@@ -2570,41 +2400,34 @@ static irqreturn_t ipu_irq_handler(int irq, void *desc)
 			    ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) & ~int_stat;
 			ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
 		}
-
-		spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
 	}
 
 	for (i = 0;; i++) {
 		if (int_reg[i] == 0)
 			break;
-		spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+
 		int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
 		int_ctrl = ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
 		int_stat &= int_ctrl;
 		ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
-		spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
-		oneshot = 0;
 		while ((line = ffs(int_stat)) != 0) {
 			bit = --line;
 			int_stat &= ~(1UL << line);
 			line += (int_reg[i] - 1) * 32;
-			if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT)
-				oneshot |= 1UL << bit;
 			result |=
 			    ipu->irq_list[line].handler(line,
 						       ipu->irq_list[line].
 						       dev_id);
-		}
-		if (oneshot) {
-			spin_lock_irqsave(&ipu->spin_lock, lock_flags);
-			if ((~int_ctrl) & oneshot)
-				BUG();
-			int_ctrl &= ~oneshot;
-			ipu_cm_write(ipu, int_ctrl, IPU_INT_CTRL(int_reg[i]));
-			spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+			if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT) {
+				int_ctrl &= ~(1UL << bit);
+				ipu_cm_write(ipu, int_ctrl,
+						IPU_INT_CTRL(int_reg[i]));
+			}
 		}
 	}
 
+	spin_unlock(&ipu->spin_lock);
+
 	return result;
 }
 
diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c
index 215fc706407f..d12ffdfc7847 100644
--- a/drivers/mxc/ipu3/ipu_device.c
+++ b/drivers/mxc/ipu3/ipu_device.c
@@ -1111,7 +1111,7 @@ static int prepare_task(struct ipu_task_entry *t)
 		if (t->set.task != 0) {
 			dev_err(t->dev, "ERR: vdoa only task:0x%x, [0x%p].\n",
 					t->set.task, t);
-			BUG();
+			return -EINVAL;
 		}
 		t->set.task |= VDOA_ONLY;
 	}
@@ -1173,7 +1173,8 @@ static int _get_vdoa_ipu_res(struct ipu_task_entry *t)
 	for (i = 0; i < max_ipu_no; i++) {
 		ipu = ipu_get_soc(i);
 		if (IS_ERR(ipu))
-			BUG();
+			dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
+				 t->task_no, found_vdoa, i);
 
 		used = &tbl->used[i][IPU_PP_CH_VF];
 		if (t->set.mode & VDI_MODE) {
@@ -1194,7 +1195,8 @@ static int _get_vdoa_ipu_res(struct ipu_task_entry *t)
 				break;
 			}
 		} else
-			BUG();
+			dev_err(t->dev, "no:0x%x,found_vdoa:%d, mode:0x%x\n",
+				 t->task_no, found_vdoa, t->set.mode);
 	}
 	if (found_ipu)
 		goto next;
@@ -1202,7 +1204,8 @@ static int _get_vdoa_ipu_res(struct ipu_task_entry *t)
 	for (i = 0; i < max_ipu_no; i++) {
 		ipu = ipu_get_soc(i);
 		if (IS_ERR(ipu))
-			BUG();
+			dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
+				 t->task_no, found_vdoa, i);
 
 		if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
 			used = &tbl->used[i][IPU_PP_CH_PP];
@@ -1225,7 +1228,9 @@ next:
 		t->ipu_id = i;
 		t->dev = ipu->dev;
 		if (atomic_inc_return(&t->res_get) == 2)
-			BUG();
+			dev_err(t->dev,
+				"ERR no:0x%x,found_vdoa:%d,get ipu twice\n",
+				 t->task_no, found_vdoa);
 	}
 out:
 	dev_dbg(t->dev,
@@ -1246,12 +1251,12 @@ static void put_vdoa_ipu_res(struct ipu_task_entry *tsk, int vdoa_only)
 	int rel_vdoa = 0, rel_ipu = 0;
 	struct ipu_channel_tabel	*tbl = &ipu_ch_tbl;
 
-	if (!tsk)
-		BUG();
 	mutex_lock(&tbl->lock);
 	if (tsk->set.mode & VDOA_MODE) {
 		if (!tbl->vdoa_used && tsk->vdoa_handle)
-			BUG();
+			dev_err(tsk->dev,
+				"ERR no:0x%x,vdoa not used,mode:0x%x\n",
+				 tsk->task_no, tsk->set.mode);
 		if (tbl->vdoa_used && tsk->vdoa_handle) {
 			tbl->vdoa_used = 0;
 			vdoa_put_handle(&tsk->vdoa_handle);
@@ -1263,13 +1268,13 @@ static void put_vdoa_ipu_res(struct ipu_task_entry *tsk, int vdoa_only)
 		}
 	}
 
-	if (tsk) {
-		tbl->used[tsk->ipu_id][tsk->task_id - 1] = 0;
-		rel_ipu = 1;
-		ret = atomic_inc_return(&tsk->res_free);
-		if (ret == 2)
-			BUG();
-	}
+	tbl->used[tsk->ipu_id][tsk->task_id - 1] = 0;
+	rel_ipu = 1;
+	ret = atomic_inc_return(&tsk->res_free);
+	if (ret == 2)
+		dev_err(tsk->dev,
+			"ERR no:0x%x,rel_vdoa:%d,put ipu twice\n",
+			 tsk->task_no, rel_vdoa);
 out:
 	dev_dbg(tsk->dev,
 		"%s:no:0x%x,rel_vdoa:%d, rel_ipu:%d\n",
@@ -1300,12 +1305,16 @@ static int get_vdoa_ipu_res(struct ipu_task_entry *t)
 			goto out;
 		} else {
 			if (!(t->set.task & VDOA_ONLY) && (!t->ipu))
-				BUG();
+				dev_err(t->dev,
+					"ERR[no-0x%x] can not get ipu!\n",
+					t->task_no);
 			ret = atomic_read(&req_cnt);
 			if (ret > 0)
 				ret = atomic_dec_return(&req_cnt);
 			else
-				BUG();
+				dev_err(t->dev,
+					"ERR[no-0x%x] req_cnt:%d mismatch!\n",
+					t->task_no, ret);
 			dev_dbg(t->dev, "no-0x%x,[0x%p],req_cnt:%d, got_res!\n",
 						t->task_no, t, ret);
 			found = 1;
@@ -1827,7 +1836,8 @@ static int init_tiled_ch_bufs(struct ipu_soc *ipu, struct ipu_task_entry *t)
 		CHECK_RETCODE(ret < 0, "init tiled_ch-n", t->state, done, ret);
 	} else {
 		ret = -EINVAL;
-		BUG();
+		dev_err(t->dev, "ERR[no-0x%x] invalid fmt:0x%x!\n",
+			t->task_no, t->input.format);
 	}
 
 done:
@@ -1914,7 +1924,8 @@ static int init_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
 		else if (IPU_DEINTERLACE_FIELD_BOTTOM == t->input.deinterlace.field_fmt)
 			params.mem_prp_vf_mem.field_fmt = V4L2_FIELD_INTERLACED_BT;
 		else
-			BUG();
+			dev_err(t->dev, "ERR[no-0x%x]invalid field fmt:0x%x!\n",
+				t->task_no, t->input.deinterlace.field_fmt);
 		ret = ipu_init_channel(ipu, t->set.vdi_ic_p_chan, &params);
 		if (ret < 0) {
 			t->state = STATE_INIT_CHAN_FAIL;
@@ -2232,8 +2243,10 @@ static void vdi_split_process(struct ipu_soc *ipu, struct ipu_task_entry *t)
 	unsigned char  *base_off;
 	struct ipu_task_entry *parent = t->parent;
 
-	if (!parent)
-		BUG();
+	if (!parent) {
+		dev_err(t->dev, "ERR[0x%x]invalid parent\n", t->task_no);
+		return;
+	}
 	stripe_mode = t->task_no & 0xf;
 	task_no = t->task_no >> 4;
 
@@ -2544,13 +2557,15 @@ static void do_task(struct ipu_task_entry *t)
 		busy = ic_vf_pp_is_busy(ipu, true);
 	else if (t->task_id == IPU_TASK_ID_PP)
 		busy = ic_vf_pp_is_busy(ipu, false);
-	else
-		BUG();
+	else {
+		dev_err(ipu->dev, "ERR[no:0x%x]ipu task_id:%d invalid!\n",
+				t->task_no, t->task_id);
+		return;
+	}
 	if (busy) {
 		dev_err(ipu->dev, "ERR[0x%p-no:0x%x]ipu task_id:%d busy!\n",
 				(void *)t, t->task_no, t->task_id);
 		t->state = STATE_IPU_BUSY;
-		BUG();
 		return;
 	}
 
@@ -2602,7 +2617,7 @@ static void do_task(struct ipu_task_entry *t)
 			ipu->rot_dma[rot_idx].vaddr = dma_alloc_coherent(t->dev,
 						r_size,
 						&ipu->rot_dma[rot_idx].paddr,
-						GFP_KERNEL);
+						GFP_DMA | GFP_KERNEL);
 			CHECK_RETCODE(ipu->rot_dma[rot_idx].vaddr == NULL,
 					"ic_and_rot", STATE_SYS_NO_MEM,
 					chan_setup, -ENOMEM);
@@ -2629,7 +2644,6 @@ static void do_task(struct ipu_task_entry *t)
 	} else {
 		dev_err(t->dev, "ERR [0x%p]do task: should not be here\n", t);
 		t->state = STATE_ERR;
-		BUG();
 		return;
 	}
 
@@ -2832,7 +2846,9 @@ static void get_res_do_task(struct ipu_task_entry *t)
 
 	found = get_vdoa_ipu_res(t);
 	if (!found) {
-		BUG();
+		dev_err(t->dev, "ERR:[0x%p] no-0x%x can not get res\n",
+			t, t->task_no);
+		return;
 	} else {
 		if (t->set.task & VDOA_ONLY)
 			do_task_vdoa_only(t);
@@ -2886,12 +2902,18 @@ static void wait_split_task_complete(struct ipu_task_entry *parent,
 			ret = -ETIMEDOUT;
 			goto out;
 		} else {
-			if (idx < 0)
-				BUG();
+			if (idx < 0) {
+				dev_err(parent->dev,
+				"ERR:[0x%p] no-0x%x, invalid task idx:%d\n",
+				 parent, parent->task_no, idx);
+				continue;
+			}
 			tsk = sp_task[idx].child_task;
 			mutex_lock(lock);
 			if (!tsk->split_done || !tsk->ipu)
-				BUG();
+				dev_err(tsk->dev,
+				"ERR:no-0x%x,split not done:%d/null ipu:0x%p\n",
+				 tsk->task_no, tsk->split_done, tsk->ipu);
 			tsk->split_done = 0;
 			mutex_unlock(lock);
 
@@ -2911,7 +2933,8 @@ out:
 		for (k = 0; k < max_ipu_no; k++) {
 			ipu = ipu_get_soc(k);
 			if (IS_ERR(ipu)) {
-				BUG();
+				dev_err(parent->dev, "no:0x%x, null ipu:%d\n",
+				 parent->task_no, k);
 			} else {
 				busy_vf = ic_vf_pp_is_busy(ipu, true);
 				busy_pp = ic_vf_pp_is_busy(ipu, false);
@@ -2948,10 +2971,6 @@ out:
 		spin_unlock_irqrestore(&ipu_task_list_lock, flags);
 		if (!tsk->ipu)
 			continue;
-		if (STATE_IN_PROGRESS == tsk->state) {
-			do_task_release(tsk, 1);
-			put_vdoa_ipu_res(tsk, 0);
-		}
 		if (tsk->state != STATE_OK) {
 			dev_err(tsk->dev,
 				"ERR:[0x%p] no-0x%x,id:%d, sp_tsk state: %s\n",
@@ -2992,7 +3011,9 @@ static inline int find_task(struct ipu_task_entry **t, int thread_id)
 			"thread_id:%d,[0x%p] task_no:0x%x,mode:0x%x list_del\n",
 			thread_id, tsk, tsk->task_no, tsk->set.mode);
 		} else
-			BUG();
+			dev_err(tsk->dev,
+			"thread_id:%d,task_no:0x%x,mode:0x%x not on list_del\n",
+			thread_id, tsk->task_no, tsk->set.mode);
 	}
 	spin_unlock_irqrestore(&ipu_task_list_lock, flags);
 
@@ -3027,7 +3048,6 @@ static int ipu_task_thread(void *argv)
 			&cpu_mask);
 		if (ret < 0) {
 			pr_err("%s: sched_setaffinity fail:%d.\n", __func__, ret);
-			BUG();
 		}
 		pr_debug("%s: sched_setaffinity cpu:%d.\n", __func__, cpu);
 	}
@@ -3039,8 +3059,11 @@ static int ipu_task_thread(void *argv)
 
 		wait_event(thread_waitq, find_task(&tsk, curr_thread_id));
 
-		if (!tsk)
-			BUG();
+		if (!tsk) {
+			pr_err("thread:%d can not find task.\n",
+				curr_thread_id);
+			continue;
+		}
 
 		/* note: other threads run split child task */
 		split_parent = need_split(tsk) && !tsk->parent;
@@ -3083,7 +3106,9 @@ static int ipu_task_thread(void *argv)
 				/* FIXME: ensure the correct sequence for split
 					4size: 5/6->9/a*/
 				if (!sp_tsk0)
-					BUG();
+					dev_err(tsk->dev,
+					"ERR: no-0x%x,can not get split_tsk0\n",
+					tsk->task_no);
 				wake_up(&thread_waitq);
 				get_res_do_task(sp_tsk0);
 				dev_dbg(sp_tsk0->dev,
@@ -3127,8 +3152,7 @@ static int ipu_task_thread(void *argv)
 		kref_put(&tsk->refcount, task_mem_free);
 	}
 
-	pr_info("%s exit.\n", __func__);
-	BUG();
+	pr_info("ERR %s exit.\n", __func__);
 	return 0;
 }
 
@@ -3301,7 +3325,7 @@ static long mxc_ipu_ioctl(struct file *file,
 
 			mem->cpu_addr = dma_alloc_coherent(ipu_dev, size,
 							   &mem->phy_addr,
-							   GFP_KERNEL);
+							   GFP_DMA | GFP_KERNEL);
 			if (mem->cpu_addr == NULL) {
 				kfree(mem);
 				return -ENOMEM;
diff --git a/drivers/mxc/thermal/cooling.c b/drivers/mxc/thermal/cooling.c
index 772f771c8149..7019d9949c8a 100644
--- a/drivers/mxc/thermal/cooling.c
+++ b/drivers/mxc/thermal/cooling.c
@@ -57,6 +57,7 @@ cpufreq, it minor 1, and when we promote cpufreq, it add 1, so
 if it is 0, mean we didn't change the cpufreq */
 static int cpufreq_change_count;
 
+extern int thermal_hot;
 int anatop_thermal_get_cpufreq_cur(void)
 {
 	int ret = -EINVAL;
@@ -177,6 +178,7 @@ int anatop_thermal_cpu_hotplug(bool cpu_on)
 					sys_write(fd, (char *)"1", MAX_CPU_ONLINE_LEN);
 					cpu_mask &= ~(0x1 << cpu);
 					ret = 0;
+					sys_close(fd);
 					break;
 				}
 				sys_close(fd);
@@ -198,6 +200,7 @@ int anatop_thermal_cpu_hotplug(bool cpu_on)
 					sys_write(fd, (char *)"0", MAX_CPU_ONLINE_LEN);
 					cpu_mask |= 0x1 << cpu;
 					ret = 0;
+					sys_close(fd);
 					break;
 				}
 				sys_close(fd);
@@ -235,6 +238,7 @@ imx_processor_set_cur_state(struct thermal_cooling_device *cdev,
 	secondary CPUs that detached by thermal driver */
 	if (cooling_cpuhotplug) {
 		if (!state) {
+			thermal_hot = 0;
 			for (i = 1; i < 4; i++) {
 				if (cpu_mask && (0x1 << i)) {
 					anatop_thermal_cpu_hotplug(true);
@@ -245,6 +249,7 @@ imx_processor_set_cur_state(struct thermal_cooling_device *cdev,
 		}
 	} else {
 		if (!state) {
+			thermal_hot = 0;
 			if (cpufreq_change_count < 0)
 				anatop_thermal_cpufreq_up();
 			else if (cpufreq_change_count > 0)
diff --git a/drivers/mxc/thermal/thermal.c b/drivers/mxc/thermal/thermal.c
index 0f4cfb8304ce..6f3c7a912170 100644
--- a/drivers/mxc/thermal/thermal.c
+++ b/drivers/mxc/thermal/thermal.c
@@ -152,6 +152,8 @@ static const struct anatop_device_id thermal_device_ids[] = {
 	{ANATOP_THERMAL_HID},
 	{""},
 };
+int thermal_hot;
+EXPORT_SYMBOL(thermal_hot);
 
 enum {
 	DEBUG_USER_STATE = 1U << 0,
@@ -584,6 +586,7 @@ static int anatop_thermal_notify(struct thermal_zone_device *thermal, int trip,
 		printk(KERN_WARNING "thermal_notify: trip_critical reached!\n");
 		arch_reset(mode, cmd);
 	} else if (trip_type == THERMAL_TRIP_HOT) {
+		thermal_hot = 1;
 		printk(KERN_DEBUG "thermal_notify: trip_hot reached!\n");
 		type = ANATOP_THERMAL_NOTIFY_HOT;
 		/* if temperature increase, continue to detach secondary CPUs*/
@@ -598,6 +601,7 @@ static int anatop_thermal_notify(struct thermal_zone_device *thermal, int trip,
 			printk(KERN_INFO "No secondary CPUs detached!\n");
 		full_run = false;
 	} else {
+		thermal_hot = 0;
 		if (!full_run) {
 			temperature_cooling = 0;
 			if (cooling_cpuhotplug)
diff --git a/drivers/mxc/vpu/Kconfig b/drivers/mxc/vpu/Kconfig
index dada2040e2ad..6562697f25f5 100644
--- a/drivers/mxc/vpu/Kconfig
+++ b/drivers/mxc/vpu/Kconfig
@@ -19,4 +19,13 @@ config MXC_VPU_DEBUG
 	  This is an option for the developers; most people should
 	  say N here.  This enables MXC VPU driver debugging.
 
+config MX6_VPU_352M
+	bool "MX6 VPU 352M"
+	depends on MXC_VPU
+	default n
+	help
+	 Increase VPU frequncy to 352M, the config will disable bus frequency
+	 adjust dynamic, and CPU lowest setpoint will be 352Mhz.
+	 This config is used for special VPU use case.
+
 endmenu
diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c
index 048776bfdc57..c3a48307c918 100755
--- a/drivers/usb/gadget/arcotg_udc.c
+++ b/drivers/usb/gadget/arcotg_udc.c
@@ -68,7 +68,6 @@
 #define cpu_to_hc32(x)	cpu_to_le32((x))
 #define hc32_to_cpu(x)	le32_to_cpu((x))
 #endif
-
 #define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
 DEFINE_MUTEX(udc_resume_mutex);
 extern void usb_debounce_id_vbus(void);
@@ -340,7 +339,7 @@ static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable)
 	struct fsl_usb2_platform_data *pdata = udc->pdata;
 	u32 portsc;
 	unsigned long flags;
-	spin_lock_irqsave(&udc->lock, flags);
+	spin_lock_irqsave(&pdata->lock, flags);
 
 	if (pdata && pdata->phy_lowpower_suspend) {
 		pdata->phy_lowpower_suspend(pdata, enable);
@@ -356,7 +355,7 @@ static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable)
 		}
 	}
 	pdata->lowpower = enable;
-	spin_unlock_irqrestore(&udc->lock, flags);
+	spin_unlock_irqrestore(&pdata->lock, flags);
 }
 
 static int dr_controller_setup(struct fsl_udc *udc)
@@ -473,6 +472,9 @@ static void dr_controller_run(struct fsl_udc *udc)
 {
 	u32 temp;
 
+	udc_controller->usb_state = USB_STATE_ATTACHED;
+	udc_controller->ep0_dir = 0;
+
 	fsl_platform_pullup_enable(udc->pdata);
 
 	/* Enable DR irq reg */
@@ -2206,9 +2208,9 @@ static void fsl_gadget_disconnect_event(struct work_struct *work)
 		fsl_writel(tmp | (OTGSC_B_SESSION_VALID_IRQ_EN),
 				&dr_regs->otgsc);
 	udc->stopped = 1;
+	spin_unlock_irqrestore(&udc->lock, flags);
 	/* enable wake up */
 	dr_wake_up_enable(udc, true);
-	spin_unlock_irqrestore(&udc->lock, flags);
 	/* close USB PHY clock */
 	dr_phy_low_power_mode(udc, true);
 	/* close dr controller clock */
@@ -2445,8 +2447,6 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
 		dr_controller_run(udc_controller);
 		if (udc_controller->stopped)
 			dr_clk_gate(false);
-		udc_controller->usb_state = USB_STATE_ATTACHED;
-		udc_controller->ep0_dir = 0;
 	}
 	printk(KERN_INFO "%s: bind to driver %s \n",
 			udc_controller->gadget.name, driver->driver.name);
@@ -3210,6 +3210,7 @@ static int __devinit fsl_udc_probe(struct platform_device *pdev)
 	udc_controller->charger.enable = false;
 #endif
 
+	spin_lock_init(&pdata->lock);
 	return 0;
 
 err4:
@@ -3464,6 +3465,7 @@ static int fsl_udc_resume(struct platform_device *pdev)
 	 */
 	if (udc_controller->suspended && !udc_controller->stopped) {
 		dr_clk_gate(true);
+		dr_wake_up_enable(udc_controller, false);
 		dr_phy_low_power_mode(udc_controller, false);
 	}
 	/* Enable DR irq reg and set controller Run */
@@ -3483,9 +3485,6 @@ static int fsl_udc_resume(struct platform_device *pdev)
 		dr_controller_setup(udc_controller);
 		dr_controller_run(udc_controller);
 	}
-	udc_controller->usb_state = USB_STATE_ATTACHED;
-	udc_controller->ep0_dir = 0;
-
 end:
 	/* if udc is resume by otg id change and no device
 	 * connecting to the otg, otg will enter low power mode*/
diff --git a/drivers/usb/host/ehci-arc.c b/drivers/usb/host/ehci-arc.c
index 787374ab138d..b872d94b3fc3 100755
--- a/drivers/usb/host/ehci-arc.c
+++ b/drivers/usb/host/ehci-arc.c
@@ -31,6 +31,9 @@
 extern void usb_host_set_wakeup(struct device *wkup_dev, bool para);
 static void fsl_usb_lowpower_mode(struct fsl_usb2_platform_data *pdata, bool enable)
 {
+	unsigned long flags;
+
+	spin_lock_irqsave(&pdata->lock, flags);
 	if (enable) {
 		if (pdata->phy_lowpower_suspend)
 			pdata->phy_lowpower_suspend(pdata, true);
@@ -39,6 +42,7 @@ static void fsl_usb_lowpower_mode(struct fsl_usb2_platform_data *pdata, bool ena
 			pdata->phy_lowpower_suspend(pdata, false);
 	}
 	pdata->lowpower = enable;
+	spin_unlock_irqrestore(&pdata->lock, flags);
 }
 
 static void fsl_usb_clk_gate(struct fsl_usb2_platform_data *pdata, bool enable)
@@ -304,6 +308,7 @@ int usb_hcd_fsl_probe(const struct hc_driver *driver,
 
 	ehci = hcd_to_ehci(hcd);
 	pdata->pm_command = ehci->command;
+	spin_lock_init(&pdata->lock);
 	return retval;
 err6:
 	free_irq(irq, (void *)pdev);
@@ -337,7 +342,6 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
 	u32 tmp;
-	unsigned long flags;
 
 	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
 		/* Need open clock for register access */
@@ -366,9 +370,7 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
 	}
 	/*disable the host wakeup and put phy to low power mode */
 	usb_host_set_wakeup(hcd->self.controller, false);
-	spin_lock_irqsave(&ehci->lock, flags);
 	fsl_usb_lowpower_mode(pdata, true);
-	spin_unlock_irqrestore(&ehci->lock, flags);
 	/*free the ehci_fsl_pre_irq  */
 	free_irq(hcd->irq, (void *)pdev);
 	usb_remove_hcd(hcd);
@@ -430,7 +432,6 @@ static int ehci_fsl_bus_suspend(struct usb_hcd *hcd)
 	struct fsl_usb2_platform_data *pdata;
 	u32 tmp, portsc, cmd;
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-	unsigned long flags;
 
 	pdata = hcd->self.controller->platform_data;
 	printk(KERN_DEBUG "%s begins, %s\n", __func__, pdata->name);
@@ -458,9 +459,7 @@ static int ehci_fsl_bus_suspend(struct usb_hcd *hcd)
 	if (pdata->platform_suspend)
 		pdata->platform_suspend(pdata);
 	usb_host_set_wakeup(hcd->self.controller, true);
-	spin_lock_irqsave(&ehci->lock, flags);
 	fsl_usb_lowpower_mode(pdata, true);
-	spin_unlock_irqrestore(&ehci->lock, flags);
 	fsl_usb_clk_gate(hcd->self.controller->platform_data, false);
 	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 	printk(KERN_DEBUG "%s ends, %s\n", __func__, pdata->name);
@@ -472,8 +471,6 @@ static int ehci_fsl_bus_resume(struct usb_hcd *hcd)
 {
 	int ret = 0;
 	struct fsl_usb2_platform_data *pdata;
-	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-	unsigned long flags;
 
 	pdata = hcd->self.controller->platform_data;
 	printk(KERN_DEBUG "%s begins, %s\n", __func__, pdata->name);
@@ -490,9 +487,7 @@ static int ehci_fsl_bus_resume(struct usb_hcd *hcd)
 		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 		fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
 		usb_host_set_wakeup(hcd->self.controller, false);
-		spin_lock_irqsave(&ehci->lock, flags);
 		fsl_usb_lowpower_mode(pdata, false);
-		spin_unlock_irqrestore(&ehci->lock, flags);
 	}
 
 	if (pdata->platform_resume)
@@ -669,7 +664,6 @@ static int ehci_fsl_drv_suspend(struct platform_device *pdev,
 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 	struct usb_device *roothub = hcd->self.root_hub;
-	unsigned long flags;
 	u32 port_status;
 	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
 
@@ -745,9 +739,7 @@ static int ehci_fsl_drv_suspend(struct platform_device *pdev,
 	pdata->pm_portsc &= ~PORT_PTS_PHCD;
 
 	usb_host_set_wakeup(hcd->self.controller, true);
-	spin_lock_irqsave(&ehci->lock, flags);
 	fsl_usb_lowpower_mode(pdata, true);
-	spin_unlock_irqrestore(&ehci->lock, flags);
 
 	if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
 		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
@@ -801,9 +793,7 @@ static int ehci_fsl_drv_resume(struct platform_device *pdev)
 		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 		fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
 		usb_host_set_wakeup(hcd->self.controller, false);
-		spin_lock_irqsave(&ehci->lock, flags);
 		fsl_usb_lowpower_mode(pdata, false);
-		spin_unlock_irqrestore(&ehci->lock, flags);
 	}
 
 	spin_lock_irqsave(&ehci->lock, flags);
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
index 8b84498fd285..426b139b14b8 100644
--- a/drivers/video/mxc/ldb.c
+++ b/drivers/video/mxc/ldb.c
@@ -316,7 +316,14 @@ int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
 				writel(data, ldb->control_reg);
 			}
 		}
+		break;
 	}
+	case FB_EVENT_SUSPEND:
+		if (ldb->setting[index].clk_en) {
+			clk_disable(ldb->setting[index].ldb_di_clk);
+			ldb->setting[index].clk_en = false;
+		}
+		break;
 	default:
 		break;
 	}
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
index a2ccbaa81a8d..8a052e0433d3 100644
--- a/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -436,13 +436,13 @@ static int mxcfb_set_par(struct fb_info *fbi)
 					dma_alloc_coherent(fbi->device,
 						  alpha_mem_len,
 						  &mxc_fbi->alpha_phy_addr0,
-						  GFP_KERNEL);
+						  GFP_DMA | GFP_KERNEL);
 
 			mxc_fbi->alpha_virt_addr1 =
 					dma_alloc_coherent(fbi->device,
 						  alpha_mem_len,
 						  &mxc_fbi->alpha_phy_addr1,
-						  GFP_KERNEL);
+						  GFP_DMA | GFP_KERNEL);
 			if (mxc_fbi->alpha_virt_addr0 == NULL ||
 			    mxc_fbi->alpha_virt_addr1 == NULL) {
 				dev_err(fbi->device, "mxcfb: dma alloc for"
@@ -1782,7 +1782,7 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 	fbi->screen_base = dma_alloc_writecombine(fbi->device,
 				fbi->fix.smem_len,
 				(dma_addr_t *)&fbi->fix.smem_start,
-				GFP_KERNEL);
+				GFP_DMA | GFP_KERNEL);
 	if (fbi->screen_base == 0) {
 		dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
 		fbi->fix.smem_len = 0;
diff --git a/drivers/video/mxc_hdmi.c b/drivers/video/mxc_hdmi.c
index 999e3b157211..9e23bdea331f 100644
--- a/drivers/video/mxc_hdmi.c
+++ b/drivers/video/mxc_hdmi.c
@@ -1543,6 +1543,7 @@ static void mxc_hdmi_notify_fb(struct mxc_hdmi *hdmi)
 static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
 {
 	int i;
+	struct fb_videomode *mode;
 
 	dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
 
@@ -1554,10 +1555,14 @@ static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
 	for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
 		/*
 		 * We might check here if mode is supported by HDMI.
-		 * We do not currently support interlaced modes
+		 * We do not currently support interlaced modes.
+		 * And add CEA modes in the modelist.
 		 */
-		if (!(hdmi->fbi->monspecs.modedb[i].vmode &
-				FB_VMODE_INTERLACED)) {
+		mode = &hdmi->fbi->monspecs.modedb[i];
+
+		if (!(mode->vmode & FB_VMODE_INTERLACED) &&
+				(mxc_edid_mode_to_vic(mode) != 0)) {
+
 			dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i);
 			dev_dbg(&hdmi->pdev->dev,
 				"xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
@@ -1567,8 +1572,7 @@ static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
 				hdmi->fbi->monspecs.modedb[i].vmode,
 				hdmi->fbi->monspecs.modedb[i].flag);
 
-			fb_add_videomode(&hdmi->fbi->monspecs.modedb[i],
-					 &hdmi->fbi->modelist);
+			fb_add_videomode(mode, &hdmi->fbi->modelist);
 		}
 	}
 
@@ -1651,6 +1655,8 @@ static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi)
 	if (fb_mode_is_equal(&hdmi->previous_non_vga_mode, mode)) {
 		dev_dbg(&hdmi->pdev->dev,
 				"%s: Video mode same as previous\n", __func__);
+		/* update fbi mode in case modelist is updated */
+		hdmi->fbi->mode = mode;
 		mxc_hdmi_phy_init(hdmi);
 	} else {
 		dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
@@ -1674,6 +1680,13 @@ static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
 	/* HDMI Initialization Step C */
 	edid_status = mxc_hdmi_read_edid(hdmi);
 
+	/* Read EDID again if first EDID read failed */
+	if (edid_status == HDMI_EDID_NO_MODES ||
+			edid_status == HDMI_EDID_FAIL) {
+		dev_info(&hdmi->pdev->dev, "Read EDID again\n");
+		edid_status = mxc_hdmi_read_edid(hdmi);
+	}
+
 	/* HDMI Initialization Steps D, E, F */
 	switch (edid_status) {
 	case HDMI_EDID_SUCCESS:
@@ -1756,10 +1769,13 @@ static void hotplug_worker(struct work_struct *work)
 #ifdef CONFIG_MXC_HDMI_CEC
 			mxc_hdmi_cec_handle(0x80);
 #endif
+			hdmi_set_cable_state(1);
 
 		} else if (!(phy_int_pol & HDMI_PHY_HPD)) {
 			/* Plugout event */
 			dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
+			hdmi_set_cable_state(0);
+			mxc_hdmi_abort_stream();
 			mxc_hdmi_cable_disconnected(hdmi);
 
 			/* Make HPD intr active high to capture plugin event */
@@ -2048,10 +2064,13 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb,
 
 			if (hdmi->fb_reg && hdmi->cable_plugin)
 				mxc_hdmi_setup(hdmi, val);
+			hdmi_set_blank_state(1);
 
 		} else if (*((int *)event->data) != hdmi->blank) {
 			dev_dbg(&hdmi->pdev->dev,
 				"event=FB_EVENT_BLANK - BLANK\n");
+			hdmi_set_blank_state(0);
+			mxc_hdmi_abort_stream();
 
 			mxc_hdmi_phy_disable(hdmi);
 
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 8c41b237fc83..2a9557307643 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -144,6 +144,7 @@ struct fsl_usb2_platform_data {
 	unsigned	irq_delay:1;
 	enum usb_wakeup_event	wakeup_event;
 	u32		pmflags;	/* PM from otg or system */
+	spinlock_t lock;
 
 	void __iomem *charger_base_addr; /* used for i.mx6 usb charger detect */
 
diff --git a/include/linux/mfd/mxc-hdmi-core.h b/include/linux/mfd/mxc-hdmi-core.h
index 8ddea5a040cc..f16b11cb5cf4 100644
--- a/include/linux/mfd/mxc-hdmi-core.h
+++ b/include/linux/mfd/mxc-hdmi-core.h
@@ -21,6 +21,11 @@
 
 #include <mach/mxc_edid.h>
 
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
 #define IRQ_DISABLE_SUCCEED	0
 #define IRQ_DISABLE_FAIL	1
 
@@ -50,5 +55,10 @@ extern int mxc_hdmi_disp_id;
 void hdmi_set_registered(int registered);
 int hdmi_get_registered(void);
 unsigned int hdmi_SDMA_check(void);
+int mxc_hdmi_abort_stream(void);
+int mxc_hdmi_register_audio(struct snd_pcm_substream *substream);
+void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream);
+unsigned int hdmi_set_cable_state(unsigned int state);
+unsigned int hdmi_set_blank_state(unsigned int state);
 
 #endif
diff --git a/sound/soc/codecs/cs42888.c b/sound/soc/codecs/cs42888.c
index 73571dafa9a4..ce240834b2e1 100644
--- a/sound/soc/codecs/cs42888.c
+++ b/sound/soc/codecs/cs42888.c
@@ -758,11 +758,33 @@ static void cs42888_shutdown(struct snd_pcm_substream *substream,
 
 }
 
+static int cs42888_prepare(struct snd_pcm_substream *substream,
+				  struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_card *card = rtd->card;
+	struct snd_soc_dai *tmp_codec_dai;
+	struct snd_soc_pcm_runtime *tmp_rtd;
+	u32 i;
+
+	for (i = 0; i < card->num_rtd; i++) {
+		tmp_codec_dai = card->rtd[i].codec_dai;
+		tmp_rtd = (struct snd_soc_pcm_runtime *)(card->rtd + i);
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
+			tmp_codec_dai->pop_wait) {
+			tmp_codec_dai->pop_wait = 0;
+			cancel_delayed_work(&tmp_rtd->delayed_work);
+		}
+	}
+	return 0;
+}
+
 static struct snd_soc_dai_ops cs42888_dai_ops = {
 	.set_fmt	= cs42888_set_dai_fmt,
 	.set_sysclk	= cs42888_set_dai_sysclk,
 	.hw_params	= cs42888_hw_params,
 	.shutdown	= cs42888_shutdown,
+	.prepare	= cs42888_prepare,
 };
 
 
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index 8558be580ee3..b14531157067 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -5,6 +5,7 @@
  *
  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -4019,7 +4020,7 @@ static int wm8962_probe(struct snd_soc_codec *codec)
 		dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 		goto err_get;
 	}
-
+	msleep(100);
 	ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to read ID register\n");
diff --git a/sound/soc/imx/imx-cs42888.c b/sound/soc/imx/imx-cs42888.c
index e06b1a7fc314..acec900618b1 100644
--- a/sound/soc/imx/imx-cs42888.c
+++ b/sound/soc/imx/imx-cs42888.c
@@ -85,8 +85,6 @@ static int config_asrc(struct snd_pcm_substream *substream,
 	ret = asrc_req_pair(channel, &iprtd->asrc_index);
 	if (ret < 0) {
 		pr_err("Fail to request asrc pair\n");
-		asrc_release_pair(iprtd->asrc_index);
-		asrc_finish_conv(iprtd->asrc_index);
 		return -EINVAL;
 	}
 
@@ -96,14 +94,12 @@ static int config_asrc(struct snd_pcm_substream *substream,
 	config.channel_num = channel;
 	config.input_sample_rate = rate;
 	config.output_sample_rate = iprtd->p2p->p2p_rate;
-	config.inclk = INCLK_ASRCK1_CLK;
+	config.inclk = INCLK_NONE;
 	config.outclk = OUTCLK_ESAI_TX;
 
 	ret = asrc_config_pair(&config);
 	if (ret < 0) {
 		pr_err("Fail to config asrc\n");
-		asrc_release_pair(iprtd->asrc_index);
-		asrc_finish_conv(iprtd->asrc_index);
 		return ret;
 	}
 
@@ -135,6 +131,13 @@ static void imx_3stack_shutdown(struct snd_pcm_substream *substream)
 {
 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+
+	if (!cpu_dai->active)
+		hw_state.hw = 0;
+}
+
+static int imx_3stack_surround_hw_free(struct snd_pcm_substream *substream)
+{
 	struct imx_pcm_runtime_data *iprtd = substream->runtime->private_data;
 
 	if (iprtd->asrc_enable) {
@@ -145,10 +148,8 @@ static void imx_3stack_shutdown(struct snd_pcm_substream *substream)
 		iprtd->asrc_index = -1;
 	}
 
-	if (!cpu_dai->active)
-		hw_state.hw = 0;
+	return 0;
 }
-
 static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream,
 					 struct snd_pcm_hw_params *params)
 {
@@ -161,16 +162,17 @@ static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream,
 	unsigned int lrclk_ratio = 0;
 	int err = 0;
 
-	if (hw_state.hw)
-		return 0;
-	hw_state.hw = 1;
-
 	if (iprtd->asrc_enable) {
 		err = config_asrc(substream, params);
 		if (err < 0)
 			return err;
 		rate = iprtd->p2p->p2p_rate;
 	}
+
+	if (hw_state.hw)
+		return 0;
+	hw_state.hw = 1;
+
 	if (cpu_is_mx53() || machine_is_mx6q_sabreauto()) {
 		switch (rate) {
 		case 32000:
@@ -280,6 +282,7 @@ static struct snd_soc_ops imx_3stack_surround_ops = {
 	.startup = imx_3stack_startup,
 	.shutdown = imx_3stack_shutdown,
 	.hw_params = imx_3stack_surround_hw_params,
+	.hw_free = imx_3stack_surround_hw_free,
 };
 
 static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = {
diff --git a/sound/soc/imx/imx-esai.c b/sound/soc/imx/imx-esai.c
index b3cba9ea53c4..359cb2a4aea0 100644
--- a/sound/soc/imx/imx-esai.c
+++ b/sound/soc/imx/imx-esai.c
@@ -278,6 +278,12 @@ static int imx_esai_startup(struct snd_pcm_substream *substream,
 {
 	struct imx_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
 
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
+			(local_esai->imx_esai_txrx_state & IMX_DAI_ESAI_TX)) {
+		pr_err("error: too much esai playback!\n");
+		return -EINVAL;
+	}
+
 	if (!(local_esai->imx_esai_txrx_state & IMX_DAI_ESAI_TXRX)) {
 		clk_enable(esai->clk);
 
@@ -468,6 +474,7 @@ static int imx_esai_trigger(struct snd_pcm_substream *substream, int cmd,
 {
 	struct imx_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
 	u32 reg, tfcr = 0, rfcr = 0;
+	int i;
 
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		tfcr = readl(esai->base + ESAI_TFCR);
@@ -483,6 +490,9 @@ static int imx_esai_trigger(struct snd_pcm_substream *substream, int cmd,
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 			tfcr |= ESAI_TFCR_TFEN;
 			writel(tfcr, esai->base + ESAI_TFCR);
+			/* write initial words to ETDR register */
+			for (i = 0; i < substream->runtime->channels; i++)
+				writel(0x0, esai->base + ESAI_ETDR);
 			reg |= ESAI_TCR_TE(substream->runtime->channels);
 			writel(reg, esai->base + ESAI_TCR);
 		} else {
diff --git a/sound/soc/imx/imx-hdmi-dma.c b/sound/soc/imx/imx-hdmi-dma.c
index 18e3a016cca8..70c8cb13d3de 100644
--- a/sound/soc/imx/imx-hdmi-dma.c
+++ b/sound/soc/imx/imx-hdmi-dma.c
@@ -1195,6 +1195,12 @@ static int hdmi_dma_open(struct snd_pcm_substream *substream)
 		(int)clk_get_rate(hdmi_dma_priv->isfr_clk),
 		(int)clk_get_rate(hdmi_dma_priv->iahb_clk));
 
+	ret = mxc_hdmi_register_audio(substream);
+	if (ret < 0) {
+		pr_err("ERROR: HDMI is not ready!\n");
+		return ret;
+	}
+
 	hdmi_fifo_reset();
 
 	ret = snd_pcm_hw_constraint_integer(substream->runtime,
@@ -1215,6 +1221,7 @@ static int hdmi_dma_close(struct snd_pcm_substream *substream)
 	struct imx_hdmi_dma_runtime_data *rtd = runtime->private_data;
 
 	hdmi_dma_irq_disable(rtd);
+	mxc_hdmi_unregister_audio(substream);
 
 	clk_disable(rtd->iahb_clk);
 	clk_disable(rtd->isfr_clk);
@@ -1337,7 +1344,7 @@ static int __devinit imx_soc_platform_probe(struct platform_device *pdev)
 	if (hdmi_SDMA_check()) {
 		/*To alloc a buffer non cacheable for hdmi script use*/
 		hdmi_dma_priv->hdmi_sdma_t =
-			dma_alloc_coherent(NULL,
+			dma_alloc_noncacheable(NULL,
 				sizeof(struct hdmi_sdma_script_data),
 				&hdmi_dma_priv->phy_hdmi_sdma_t,
 				GFP_KERNEL);
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
index b36b28108049..ad8d5a3329c7 100644
--- a/sound/soc/imx/imx-pcm-dma-mx2.c
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -359,6 +359,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 			dmaengine_submit(iprtd->asrc_p2p_desc);
 			dmaengine_submit(iprtd->asrc_desc);
 			asrc_start_conv(iprtd->asrc_index);
+			mdelay(1);
 		} else {
 			dmaengine_submit(iprtd->desc);
 		}
diff --git a/sound/soc/imx/imx-si4763.c b/sound/soc/imx/imx-si4763.c
index 3bf7f0340ea9..1dd50e769235 100644
--- a/sound/soc/imx/imx-si4763.c
+++ b/sound/soc/imx/imx-si4763.c
@@ -94,7 +94,7 @@ static int imx_3stack_si4763_hw_params(struct snd_pcm_substream *substream,
 	/* set the SSI system clock as input (unused) */
 	snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN);
 
-	snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 9);
+	snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 4);
 	snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 1);
 	snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);
 	return 0;
diff --git a/sound/soc/imx/imx-wm8962.c b/sound/soc/imx/imx-wm8962.c
index de0dcd60a594..8da589f2fa69 100644
--- a/sound/soc/imx/imx-wm8962.c
+++ b/sound/soc/imx/imx-wm8962.c
@@ -474,7 +474,7 @@ static int __init imx_asoc_init(void)
 
 	if (machine_is_mx6q_sabresd())
 		imx_dai[0].codec_name = "wm8962.0-001a";
-	else if (machine_is_mx6sl_arm2())
+	else if (machine_is_mx6sl_arm2() | machine_is_mx6sl_evk())
 		imx_dai[0].codec_name = "wm8962.1-001a";
 
 	imx_snd_device = platform_device_alloc("soc-audio", 5);
author	Jack Lee <jacklee@freescale.com>	2012-09-05 10:21:49 +0800
committer	Jack Lee <jacklee@freescale.com>	2012-09-05 10:21:49 +0800
commit	a0619e1d6c1c51a367b8d0bf74bb9058df919545 (patch)
tree	d40e30c91892ea35c82d22a8364b9b9548e42b7a
parent	65745dd4b7f80711d03dce5529fc501162428c53 (diff)
parent	85a6685fb327f1eebaeea5dfc04a6750573472ef (diff)