diff options
| author | Allen Xu <allen.xu@freescale.com> | 2012-04-18 10:15:27 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2012-04-19 17:39:43 +0800 |
| commit | 3826b1a6961fd7bf626280cba95beb368a9cd696 (patch) | |
| tree | dc88cd5f3f62b5e4fcf3151c00c6fc6528c9aa45 | |
| parent | c31803a30d4ed3b607ef311f340be31138ee0f91 (diff) | |
ENGR00180096 change NAND clock source to pll2_pfd_400M
change clock source explicitly by calling set_parent() function
Signed-off-by: Allen Xu <allen.xu@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 7131578a2bdb..ce6de1e275f7 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -3874,7 +3874,7 @@ static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate) static struct clk enfc_clk = { __INIT_CLK_DEBUG(enfc_clk) .id = 0, - .parent = &pll2_pfd_400M, + .parent = &pll2_pfd_352M, .enable_reg = MXC_CCM_CCGR2, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, .enable = _clk_enable, @@ -5235,6 +5235,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_set_rate(&asrc_clk[1], 7500000); /* set the GPMI clock to default frequency : 20MHz */ + clk_set_parent(&enfc_clk, &pll2_pfd_400M); clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 20000000)); mx6_cpu_op_init(); |