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authorPeter Chen <peter.chen@freescale.com>2013-03-01 16:37:42 +0800
committerPeter Chen <peter.chen@freescale.com>2013-03-06 09:09:28 +0800
commit59fc3c58c471a125e5882ae3823545f24843eb75 (patch)
treea0ebd1cfed6fda9cb78e6c555233c32e7b25130e
parent456627186832cb315805b16a9e3a44034cc7a2b2 (diff)
ENGR00251209-2 usb: otg: fix the dp/dm will be floating when phy is no 3v3
For the design which the phy is no power (no 5v for VBUS), the PHY can't get dp/dm correctly, so it the port change interrpt is enabled or the host enters low power mode, the unexpected interrupt will occur. This commit will make the dp/dm as zero at otg configuration. For gadget-only, the same function is existed at probe. For host-only, the vbus will be on before port change interrupt is enabled. Signed-off-by: Peter Chen <peter.chen@freescale.com>
-rwxr-xr-xdrivers/usb/otg/fsl_otg.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c
index 292c2e930b5d..9fd3c87babfb 100755
--- a/drivers/usb/otg/fsl_otg.c
+++ b/drivers/usb/otg/fsl_otg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Author: Li Yang <LeoLi@freescale.com>
* Jerry Huang <Chang-Ming.Huang@freescale.com>
@@ -631,6 +631,11 @@ static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
if (otg_dev->fsm.id) {
otg_dev->host_first_call = true;
+ /* The discharge will be false when the controller
+ * is ready to use.
+ */
+ if (pdata->dr_discharge_line)
+ pdata->dr_discharge_line(true);
schedule_otg_work(&otg_dev->otg_event, 100);
}
else {