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authortkasivajhula <tkasivajhula@nvidia.com>2010-05-04 21:44:39 -0700
committerGary King <gking@nvidia.com>2010-05-06 00:03:47 -0700
commit2fcda6686031abe10d5fd2127b8a62d65eebbd77 (patch)
treef58aa41bc0baf403fcaadde7caf25302d28ddfe4
parent3426549ad7bd20c115a4a354ab5d7866638a80f7 (diff)
tegra power: Fix gart suspend/resume operations
Apply proper barriers to suspend/resume operations. The dmb() in suspend is required to prevent a race between the next ENTRY_ADDR write and the previous ENTRY_DATA read. The dsb+outer_sync() in resume() is needed to ensure that the writes and reads occur as expected. Change-Id: I2e66ecce6ceb4f4647bde82cb706b739affeb858 Reviewed-on: http://git-master/r/1291 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/iovmm-gart.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/iovmm-gart.c b/arch/arm/mach-tegra/iovmm-gart.c
index e11b7d8b821b..c1d3a1a88a6f 100644
--- a/arch/arm/mach-tegra/iovmm-gart.c
+++ b/arch/arm/mach-tegra/iovmm-gart.c
@@ -108,6 +108,7 @@ static int gart_suspend(struct platform_device *pdev, pm_message_t state)
GART_ENTRY_ADDR_TABLE_ADDR, gpfn_to_gart(gart,i));
writel(reg, gart->regs + MC_GART_ENTRY_ADDR_0);
gart->savedata[i] = readl(gart->regs + MC_GART_ENTRY_DATA_0);
+ dmb();
}
spin_unlock(&gart->pte_lock);
return 0;
@@ -131,7 +132,10 @@ static int gart_resume(struct platform_device *pdev)
GART_ENTRY_ADDR_TABLE_ADDR, gpfn_to_gart(gart, i));
writel(reg, gart->regs + MC_GART_ENTRY_ADDR_0);
writel(gart->savedata[i], gart->regs + MC_GART_ENTRY_DATA_0);
+ dsb();
+ outer_sync();
}
+
reg = NV_DRF_DEF(MC, GART_CONFIG, GART_ENABLE, ENABLE);
writel(reg, gart->regs + MC_GART_CONFIG_0);
spin_unlock(&gart->pte_lock);