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author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-10-31 12:38:07 +0100 |
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committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-10-31 12:38:07 +0100 |
commit | 73e0d2dcb1326fb64ddb7cadb5ca211b058f39ba (patch) | |
tree | b549cb9f0ba8759877cc5d3c6bcf0f100c258dcf | |
parent | 4b2d05c05c9e775abf7218ad7a4b52c2d220dd14 (diff) |
apalis-imx8qm: enable sata
Add external clock nodes to model the on-module SATA reference
clock generator. Assign it to the SATA instance so it can be
disabled if required.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 75c39e765472..ddae611dd2b8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -953,6 +953,20 @@ status = "okay"; }; +&sata { + ext_osc = <1>; + clocks = <&clk IMX8QM_HSIO_SATA_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&pcie_sata_refclk_gate>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "phy_pclk0", "phy_pclk1", "sata_ext"; + status = "okay"; +}; + &ldb2_phy { status = "okay"; }; |