diff options
| author | Liu Ying <victor.liu@nxp.com> | 2017-12-15 16:51:39 +0800 |
|---|---|---|
| committer | Liu Ying <victor.liu@nxp.com> | 2017-12-15 17:56:55 +0800 |
| commit | 75255ca3f1db172976b77cccd36d43f9e5c7059c (patch) | |
| tree | b95d2d004b6f6a47bc316607775deba9ad4e04cb | |
| parent | 09ef105d5feff344e54a0826503d96629ca2b60f (diff) | |
MLK-17225 gpu: imx: imx8_dprc: Directly map color component for 32bit RGB pixels
The DPR prefetch engine has the A/R/G/B_COMP_SEL fields in the
MODE_CTRL0 register to control the color component position
mapping from input to output. We may choose to use direct mapping
and leave the pixel format to be handled by the display controllers.
Fixes: a0a3a82f90e9 ("MLK-15110-3 gpu: imx: Add i.MX8 DPR(Display Prefetch Resolve) support")
Reported-by: Richard Liu <xuegang.liu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 7cd2b87805f08923e01a32445396388e89928aaf)
| -rw-r--r-- | drivers/gpu/imx/imx8_dprc.c | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/drivers/gpu/imx/imx8_dprc.c b/drivers/gpu/imx/imx8_dprc.c index 53d48ec6cd09..1aedc8f0169d 100644 --- a/drivers/gpu/imx/imx8_dprc.c +++ b/drivers/gpu/imx/imx8_dprc.c @@ -411,23 +411,18 @@ void dprc_configure(struct dprc *dprc, unsigned int stream_id, val &= ~(PIX_COMP_SEL_MASK | PIX_SIZE); switch (format) { case DRM_FORMAT_XRGB8888: - val |= A_COMP_SEL(3) | R_COMP_SEL(2) | - G_COMP_SEL(1) | B_COMP_SEL(0); - val |= PIX_SIZE_32BIT; - break; case DRM_FORMAT_XBGR8888: - val |= A_COMP_SEL(3) | R_COMP_SEL(0) | - G_COMP_SEL(1) | B_COMP_SEL(2); - val |= PIX_SIZE_32BIT; - break; case DRM_FORMAT_RGBX8888: - val |= A_COMP_SEL(0) | R_COMP_SEL(3) | - G_COMP_SEL(2) | B_COMP_SEL(1); - val |= PIX_SIZE_32BIT; - break; case DRM_FORMAT_BGRX8888: - val |= A_COMP_SEL(0) | R_COMP_SEL(1) | - G_COMP_SEL(2) | B_COMP_SEL(3); + /* + * It turns out pixel components are mapped directly + * without position change via DPR processing with + * the following color component configurations. + * Leave the pixel format to be handled by the + * display controllers. + */ + val |= A_COMP_SEL(3) | R_COMP_SEL(2) | + G_COMP_SEL(1) | B_COMP_SEL(0); val |= PIX_SIZE_32BIT; break; case DRM_FORMAT_YUYV: |