diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2017-03-03 19:34:53 -0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-09 22:45:33 +0100 |
| commit | 780ce521ba8db2a51ebc55e31fcdb2a84a9611cb (patch) | |
| tree | 7fcca16817e7b54683e66e59a442600a3d8445d0 | |
| parent | 93a9cdfe65f512cb243f2f8794465ca47899211a (diff) | |
ARM: imx: clk: do not force clock frequency of M4
Let the M4 handle the clock frequency by itself. We also don't need
to take care to make sure clocks stay on, the per domain CCM clock
gate control registers can be used to let the CCM know that the M4
runs on that PLL:
CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
(cherry picked from commit 98adbbaef78b8a401350a0bf27c3ddc1881ec34d)
| -rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 89072718c10b..914d9a4ecff8 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -891,11 +891,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); - if (imx_src_is_m4_enabled()) { - imx_clk_set_parent(clks[IMX7D_ARM_M4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_prepare_enable(clks[IMX7D_ARM_M4_ROOT_CLK]); - } - imx_clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); imx_clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); imx_clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); |