diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2016-10-18 22:51:42 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2016-11-08 15:40:33 -0600 |
| commit | e8f0ff58330b76342359986a0321520106e80ad3 (patch) | |
| tree | 5c895f4ecba92ab4a4ff27d86100d7e1b6ee1de2 /arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | |
| parent | d1da66351749d82e4c82ef2251e95f6294847a85 (diff) | |
ARM: dts: socfpga: enable qspi on the Cyclone5 devkit
Enable the qspi controller on the devkit and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_cyclone5_socdk.dts')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 7a5f42dba12e..6306d008f01b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -87,6 +87,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; |