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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-10-18 13:31:55 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-10-18 13:31:55 +0200 |
| commit | 3624f8bc84b3ac16c314c231bed36d0eab162d7b (patch) | |
| tree | 928836bcb33d5357e55290efa94b22dbbe309374 /arch/arm/mach-tegra/board-colibri_t20.c | |
| parent | 3bb417fa73d3576ed83ca49c6a28806b05409c83 (diff) | |
colibri_t20: clean-up ADC platform data
Clean-up ADC platform data.
While at it fix some white space in the clock initialisation table and
add some comment concerning missing AC97 clock mux availability.
Diffstat (limited to 'arch/arm/mach-tegra/board-colibri_t20.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-colibri_t20.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20.c b/arch/arm/mach-tegra/board-colibri_t20.c index 98c15b8f96ab..db5946abf235 100644 --- a/arch/arm/mach-tegra/board-colibri_t20.c +++ b/arch/arm/mach-tegra/board-colibri_t20.c @@ -67,14 +67,14 @@ /* ADC */ static struct wm97xx_batt_pdata colibri_t20_adc_pdata = { - .batt_aux = WM97XX_AUX_ID1, /* AD0 - ANALOG_IN0 */ - .temp_aux = WM97XX_AUX_ID2, /* AD1 - ANALOG_IN1 */ - .charge_gpio = -1, - .batt_div = 1, - .batt_mult = 1, - .temp_div = 1, - .temp_mult = 1, - .batt_name = "colibri_t20-analog_inputs", + .batt_aux = WM97XX_AUX_ID1, /* AD0 - ANALOG_IN0 */ + .temp_aux = WM97XX_AUX_ID2, /* AD1 - ANALOG_IN1 */ + .charge_gpio = -1, + .batt_div = 1, + .batt_mult = 1, + .temp_div = 1, + .temp_mult = 1, + .batt_name = "colibri_t20-analog_inputs", }; static struct wm97xx_pdata colibri_t20_wm97xx_pdata = { @@ -86,9 +86,6 @@ static struct wm97xx_pdata colibri_t20_wm97xx_pdata = { static struct platform_device colibri_t20_audio_device = { .name = "colibri_t20-snd-wm9715l", .id = 0, -// .dev = { -// .platform_data = &colibri_t20_audio_pdata, -// }, }; #ifdef CAMERA_INTERFACE @@ -112,9 +109,9 @@ static __initdata struct tegra_clk_init_table colibri_t20_clk_init_table[] = { {"uarta", "pll_p", 216000000, true}, //required otherwise uses pll_p_out4 as parent and changing its rate to 72 MHz - {"sclk", "pll_p_out3", 108000000, true }, + {"sclk", "pll_p_out3", 108000000, true}, - /* AC97 incl. touch */ + /* AC97 incl. touch (note: unfortunately no clk source mux exists) */ {"ac97", "pll_a_out0", 24576000, true}, /* WM9715L XTL_IN 24.576 MHz */ |