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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-10-03 14:44:39 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-10-03 14:44:39 +0200 |
| commit | 49f91ff5b1083b8350ea0bd8fc1a37d7436b7e5b (patch) | |
| tree | 6f151e2928da6e3c1f3de78afd609dfd049b1b0c /arch/arm/mach-tegra/board-colibri_t20.c | |
| parent | dfb47833b7ee0248430bfd22460b3902527466cc (diff) | |
tegra: colibri_t20: clock clean-up
Clean-up some of the early clock initialisation hacks.
Diffstat (limited to 'arch/arm/mach-tegra/board-colibri_t20.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-colibri_t20.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20.c b/arch/arm/mach-tegra/board-colibri_t20.c index abc419226d13..98c15b8f96ab 100644 --- a/arch/arm/mach-tegra/board-colibri_t20.c +++ b/arch/arm/mach-tegra/board-colibri_t20.c @@ -106,8 +106,6 @@ static __initdata struct tegra_clk_init_table colibri_t20_clk_init_table[] = { /* SMSC3340 REFCLK 24 MHz */ {"pll_p_out4", "pll_p", 24000000, true}, {"pwm", "clk_32k", 32768, false}, - {"i2s1", "pll_a_out0", 0, false}, - {"i2s2", "pll_a_out0", 0, false}, {"spdif_out", "pll_a_out0", 0, false}, //required otherwise getting disabled by "Disabling clocks left on by bootloader" stage @@ -116,17 +114,16 @@ static __initdata struct tegra_clk_init_table colibri_t20_clk_init_table[] = { //required otherwise uses pll_p_out4 as parent and changing its rate to 72 MHz {"sclk", "pll_p_out3", 108000000, true }, + /* AC97 incl. touch */ {"ac97", "pll_a_out0", 24576000, true}, + /* WM9715L XTL_IN 24.576 MHz */ //[ 0.372722] Unable to set parent pll_a_out0 of clock cdev1: -38 // {"cdev1", "pll_a_out0", 24576000, true}, // {"pll_a_out0", "pll_a", 24576000, true}, {"vde", "pll_c", 240000000, false}, -//dynamic -// {"avp.sclk", "virt_sclk", 250000000, false}, -//dynamic - {"apbdma", "pclk", 36000000, false}, + {"ndflash", "pll_p", 108000000, false}, //[ 2.284308] kernel BUG at drivers/spi/spi-tegra.c:254! |