diff options
| author | ScottPeterson <speterson@nvidia.com> | 2011-12-28 13:40:20 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-01-06 17:08:38 +0530 |
| commit | fde0dd459ac5048614a4f4bf4cf86224480c846d (patch) | |
| tree | dfceca21b0a8f1a892bc27881d5f529f9e27270c /arch/arm/mach-tegra/common.c | |
| parent | 494a7b66ad5fc814b1344dd105d9f2dfad20a191 (diff) | |
arm: tegra: Disable pll_p_out clocks by default
Disable unused pll_p_out clocks until they are
needed to reduce power.
Change-Id: I60c2a7ca50a957f23ca20ec559dbbb1aa26ca797
Reviewed-on: http://git-master/r/72464
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index dd281d8d4f69..103634a9cec4 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -149,24 +149,24 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "3d", "pll_c", 0, false }, #else { "pll_p", NULL, 408000000, true }, - { "pll_p_out1", "pll_p", 9600000, true }, - { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out1", "pll_p", 9600000, false }, + { "pll_p_out2", "pll_p", 48000000, false }, { "pll_p_out3", "pll_p", 102000000, true }, { "pll_m_out1", "pll_m", 275000000, false }, - { "pll_p_out4", "pll_p", 102000000, true }, + { "pll_p_out4", "pll_p", 102000000, false }, { "sclk", "pll_p_out4", 102000000, true }, { "hclk", "sclk", 102000000, true }, { "pclk", "hclk", 51000000, true }, #endif #else { "pll_p", NULL, 216000000, true }, - { "pll_p_out1", "pll_p", 28800000, true }, - { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out1", "pll_p", 28800000, false }, + { "pll_p_out2", "pll_p", 48000000, false }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_m_out1", "pll_m", 275000000, true }, { "pll_c", NULL, ULONG_MAX, false }, { "pll_c_out1", "pll_c", 208000000, false }, - { "pll_p_out4", "pll_p", 108000000, true }, + { "pll_p_out4", "pll_p", 108000000, false }, { "sclk", "pll_p_out4", 108000000, true }, { "hclk", "sclk", 108000000, true }, { "pclk", "hclk", 54000000, true }, |