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authorVarun Wadekar <vwadekar@nvidia.com>2012-03-27 16:17:20 +0530
committerSimone Willett <swillett@nvidia.com>2012-04-05 18:13:10 -0700
commit743c03fbeb5908faf4aef6bee7702a2ad4caac22 (patch)
tree17bebff5bed35b544f559db0239297ff8fc9ec21 /arch/arm/mach-tegra/sleep-t3.S
parentf31ca2d9e0580b58dc51fde31fc8ace190dd253b (diff)
ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU
Change-Id: Ib16ee5efdf8686d750a5263baa8fff4d258e68cd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/92542 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
-rw-r--r--arch/arm/mach-tegra/sleep-t3.S12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S
index 6d58585a4903..caabeb751390 100644
--- a/arch/arm/mach-tegra/sleep-t3.S
+++ b/arch/arm/mach-tegra/sleep-t3.S
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/include/mach/sleep-t3.S
*
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -235,6 +235,16 @@ ENDPROC(tegra3_sleep_core_finish)
*/
ENTRY(tegra3_sleep_cpu_secondary_finish)
mov r6, lr
+
+ dsb
+#ifdef MULTI_CACHE
+ mov32 r10, cpu_cache
+ mov lr, pc
+ ldr pc, [r10, #CACHE_FLUSH_KERN_ALL]
+#else
+ bl __cpuc_flush_kern_all
+#endif
+
bl tegra_cpu_exit_coherency
/* Powergate this CPU. */