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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-01-16 03:15:03 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-01-16 10:42:08 +0100 |
| commit | 4e87f2dd9bc258c85b2f3bb1a100b49927fbe6f3 (patch) | |
| tree | 96c82edf20e2c28e8fc4d97438d00e3b18b8afe9 /arch/arm/mach-tegra/tegra3_clocks.c | |
| parent | fe4c58c4b96a24aba8e27956e8158b3002723b17 (diff) | |
| parent | c7460e0d6afd754ebf5555477129579bc83c47b9 (diff) | |
Merge remote-tracking branch 'remotes/nvidia/l4t/l4t-r16-r2' into tegra-next
(tegra-l4t-r16-16.5)
Conflicts:
drivers/media/video/tegra_v4l2_camera.c
drivers/mmc/host/sdhci.c
drivers/watchdog/tegra_wdt.c
include/media/tegra_v4l2_camera.h
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index fafa5a22157a..eaacad3d3396 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4372,7 +4372,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), - PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 470000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), + PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71, &tegra_vi_clk_ops), PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), |