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authorAlex Frid <afrid@nvidia.com>2011-08-11 20:54:33 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:49:37 -0800
commit84cadce9be76a334bd3c6bf0c6f8e04d00657297 (patch)
tree6ae8bfeea920bba7007ad7fd071c9201008e2cd4 /arch/arm/mach-tegra/tegra3_clocks.c
parent2f8be47bd7c24f246b3573ee43dfcede03df1fe7 (diff)
ARM: tegra: power: Add Tegra3 balanced throttling
Balanced CPU and core domains thermal throttling on Tegra3. When throttling is enabled the new algorithm caps core bus frequencies (EMC, cbus and sbus) along with CPU rate. The throttling steps, and time spent on each step are pre-defined based on characterization results. (cherry picked from commit 0fa05e9904f369e201cad0c9be2b15e141d3624e) (cherry picked from commit 977e6bf94297347d8979b19877cf228325377d8f) Change-Id: I62bfcda7b5d6ba7b621e813f5d20ded7334a080f Reviewed-on: http://git-master/r/61024 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R0e65df5536ed7153a4a11dd299c5cd383b51c190
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_clocks.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index 5d9575e75a08..2308f1d6a746 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -4195,9 +4195,9 @@ static struct cpufreq_frequency_table freq_table_1p4GHz[] = {
static struct tegra_cpufreq_table_data cpufreq_tables[] = {
{ freq_table_300MHz, 0, 1 },
- { freq_table_1p0GHz, 2, 7, 2},
- { freq_table_1p3GHz, 2, 9, 2},
- { freq_table_1p4GHz, 2, 10, 2},
+ { freq_table_1p0GHz, 1, 7, 2},
+ { freq_table_1p3GHz, 1, 9, 2},
+ { freq_table_1p4GHz, 1, 10, 2},
};
static int clip_cpu_rate_limits(