diff options
| author | Heechul Yun <hyun@nvidia.com> | 2011-06-30 15:40:43 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:41 -0800 |
| commit | 16cf91484364b27fe463c81e8eaeb7668c6de954 (patch) | |
| tree | 68a0869a71f5ed80f52f6120b30fb647dc9392c1 /arch/arm/mm | |
| parent | c0904bc1866ed5c97b193f0b787dbd1d670fa333 (diff) | |
arm: mm: Remove unnecessary cache flush on page table modification
Since MMU of Cortex-A9 read from L1-D not from memory, there's no
need to flush the cache line of the modified page table entry.
Original-Change-Id: Ie5e6a027f633ed6060b8d2a9fdcd6a5399736d55
Reviewed-on: http://git-master/r/39697
Reviewed-by: Heechul Yun <hyun@nvidia.com>
Tested-by: Heechul Yun <hyun@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rb8fd18147f8eb30b7969a6eac490efe03b646f16
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 26ee164fc803..8c165d905461 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -176,7 +176,9 @@ ENTRY(cpu_v7_set_pte_ext) ARM( str r3, [r0, #2048]! ) THUMB( add r0, r0, #2048 ) THUMB( str r3, [r0] ) - mcr p15, 0, r0, c7, c10, 1 @ flush_pte + mrc p15, 0, r3, c0, c1, 7 @ read ID_MMFR3 + tst r3, #0xf << 20 @ check the coherent walk bits + mcreq p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext) |