diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2012-03-01 11:05:50 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-03-02 18:08:03 -0800 |
| commit | 9705ceab5813d5e8e544a7195d8991cdcd96817a (patch) | |
| tree | 07bacf94435867ee73d3d4576696c865cb119cf5 /arch/arm/mm | |
| parent | abf888f5810713adb049b5aa79bf6ac58398435f (diff) | |
arm: cache: fix v7 boot with lockdep enabled
Bootup with lockdep enabled has been broken on v7 since b46c0f74657d
("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").
This is because v7_setup (which is called very early during boot) calls
v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
ends up attempting to call into lockdep C code (trace_hardirqs_off())
when we are in no position to execute it (no stack, MMU off).
Fix this by using a notrace variant of save_and_disable_irqs. The code
already uses the notrace variant of restore_irqs.
Change-Id: I1110a7e07fa3f96022b2e198488fa698c91e2642
Reviewed-by: Nicolas Pitre <(address hidden)>
Acked-by: Stephen Boyd <(address hidden)>
Cc: Catalin Marinas <(address hidden)>
Cc: stable@vger.kernel.org
Signed-off-by: Rabin Vincent <(address hidden)>
Reviewed-on: http://git-master/r/86779
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 66bf91bd75a3..ac0925bc4fa7 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -56,7 +56,7 @@ ENDPROC(v7_flush_icache_all) cmp r1, #2 @ see what cache we have at this level blt 1004f @ skip if no cache, or just i-cache #ifdef CONFIG_PREEMPT - save_and_disable_irqs r9 @ make cssr&csidr read atomic + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr |