diff options
| author | Nitin Garg <nitin.garg@nxp.com> | 2019-12-11 10:47:16 -0600 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2019-12-12 09:52:35 -0600 |
| commit | 898814df9b4f63524d7c09ccc218f1dcdb22a106 (patch) | |
| tree | 19dc3b12a66abaa14cff95dc2100cbfc489595e8 /arch/arm64/kvm | |
| parent | 8742e3e58e3ffbd402eb546d7b77586e1aced922 (diff) | |
MLK-23112 arm64: Update the SW workaround for i.MX8QM B0 ERR050104
The upper bits, above bit-35, of ARADDR and ACADDR buses within
in Arm A53 sub-system have been incorrectly connected. Therefore
ARADDR and ACADDR address bits above bit-35 should not be used.
Hence downgrade instructions using higher address bits.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 1894c0ed972d04d790a742c67b330d8a5d57e54c)
Diffstat (limited to 'arch/arm64/kvm')
| -rw-r--r-- | arch/arm64/kvm/hyp/tlb.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 73464a96c365..2e93b4d86826 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -18,6 +18,8 @@ #include <asm/kvm_hyp.h> #include <asm/tlbflush.h> +extern bool TKT340553_SW_WORKAROUND; + static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm) { u64 val; @@ -80,8 +82,12 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... */ - ipa >>= 12; - __tlbi(ipas2e1is, ipa); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalls12e1is); + } else { + ipa >>= 12; + __tlbi(ipas2e1is, ipa); + } /* * We have to ensure completion of the invalidation at Stage-2, |