diff options
Diffstat (limited to 'arch/arm/mach-mx28/include')
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/dma.h | 59 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/lcdif.h | 276 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/mx28.h | 245 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-apbh.h | 535 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-i2c.h | 498 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-icoll.h | 293 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-lcdif.h | 680 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-lradc.h | 772 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-ocotp.h | 239 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-power.h | 683 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-pwm.h | 147 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-pxp.h | 518 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-rtc.h | 226 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-ssp.h | 474 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regs-timrot.h | 293 | ||||
| -rw-r--r-- | arch/arm/mach-mx28/include/mach/regulator.h | 30 |
16 files changed, 5968 insertions, 0 deletions
diff --git a/arch/arm/mach-mx28/include/mach/dma.h b/arch/arm/mach-mx28/include/mach/dma.h new file mode 100644 index 000000000000..ad8076c5d8f3 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_14, + MXS_DMA_CHANNEL_AHB_APBH_15, + MXS_DMA_CHANNEL_AHB_APBX = 16, + MXS_DMA_CHANNEL_AHB_APBX_UART4_RX = MXS_DMA_CHANNEL_AHB_APBX, + MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + MXS_DMA_CHANNEL_AHB_APBX_03, + MXS_DMA_CHANNEL_AHB_APBX_SAIF0, + MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + MXS_DMA_CHANNEL_AHB_APBX_I2C0, + MXS_DMA_CHANNEL_AHB_APBX_I2C1, + MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + MAX_DMA_CHANNELS, +}; +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/lcdif.h b/arch/arm/mach-mx28/include/mach/lcdif.h new file mode 100644 index 000000000000..23fff95968ba --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/lcdif.h @@ -0,0 +1,276 @@ +/* + * Freescale MXS LCDIF interfaces + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _ARCH_ARM_LCDIF_H +#define _ARCH_ARM_LCDIF_H + +#include <linux/types.h> +#include <linux/fb.h> +#include <linux/list.h> +#include <linux/backlight.h> +#include <linux/dma-mapping.h> +#include <linux/regulator/consumer.h> +#include <linux/platform_device.h> + +#include <mach/device.h> + +#include "regs-lcdif.h" + +#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR) + +enum { + SPI_MOSI = 0, + SPI_SCLK, + SPI_CS, +}; + +struct mxs_lcd_dma_chain_info { + dma_addr_t *dma_addr_p; + unsigned offset; +}; + +enum { + MXS_LCD_PANEL_SYSTEM = 0, + MXS_LCD_PANEL_VSYNC, + MXS_LCD_PANEL_DOTCLK, + MXS_LCD_PANEL_DVI, +}; + +struct mxs_platform_bl_data; +struct mxs_platform_fb_entry { + char name[16]; + u16 x_res; + u16 y_res; + u16 bpp; + u32 cycle_time_ns; + int lcd_type; + int (*init_panel) (struct device *, dma_addr_t, int, + struct mxs_platform_fb_entry *); + void (*release_panel) (struct device *, struct mxs_platform_fb_entry *); + int (*blank_panel) (int); + void (*run_panel) (void); + void (*stop_panel) (void); + int (*pan_display) (dma_addr_t); + int (*update_panel) (void *, struct mxs_platform_fb_entry *); + struct list_head link; + struct mxs_platform_bl_data *bl_data; +}; + +struct mxs_platform_fb_data { + struct list_head list; + struct mxs_platform_fb_entry *cur; + struct mxs_platform_fb_entry *next; +}; + +#define MXS_LCDIF_PANEL_INIT 1 +#define MXS_LCDIF_PANEL_RELEASE 2 + +struct mxs_platform_bl_data { + struct list_head list; + struct regulator *regulator; + int bl_gpio; + int bl_max_intensity; + int bl_cons_intensity; + int bl_default_intensity; + int (*init_bl) (struct mxs_platform_bl_data *); + int (*set_bl_intensity) (struct mxs_platform_bl_data *, + struct backlight_device *, int); + void (*free_bl) (struct mxs_platform_bl_data *); +}; + +static inline void mxs_lcd_register_entry(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_add_tail(&pentry->link, &pdata->list); + if (!pdata->cur) + pdata->cur = pentry; +} + +static inline void mxs_lcd_move_pentry_up(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_move(&pentry->link, &pdata->list); +} + +static inline int mxs_lcd_iterate_pdata(struct mxs_platform_fb_data + *pdata, + int (*func) (struct + mxs_platform_fb_entry + * pentry, void *data, + int ret_prev), void *data) +{ + struct mxs_platform_fb_entry *pentry; + int ret = 0; + list_for_each_entry(pentry, &pdata->list, link) { + ret = func(pentry, data, ret); + } + return ret; +} + +static inline void mxs_lcd_set_bl_pdata(struct mxs_platform_bl_data + *pdata) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-bl", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->dev.platform_data = pdata; +} + +void mxs_init_lcdif(void); +int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize); +void mxs_lcdif_dma_release(void); +void mxs_lcdif_run(void); +void mxs_lcdif_stop(void); +int mxs_lcdif_pan_display(dma_addr_t addr); + +int mxs_lcdif_register_client(struct notifier_block *nb); +void mxs_lcdif_unregister_client(struct notifier_block *nb); +void mxs_lcdif_notify_clients(unsigned long event, + struct mxs_platform_fb_entry *pentry); + +#ifndef FBIO_WAITFORVSYNC +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#endif + +static inline void setup_dotclk_panel(u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, int enable_present) +{ + u32 val; + + __raw_writel(BM_LCDIF_CTRL_DATA_SHIFT_DIR, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_SHIFT_NUM_BITS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /* 24 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL | + BM_LCDIF_VDCTRL0_HSYNC_POL | + BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL); + val |= BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); /* vsync is output */ + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR); + __raw_writel(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET); + + __raw_writel(BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + + __raw_writel(BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | + BF_LCDIF_VDCTRL2_HSYNC_PERIOD(h_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | + BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); +} + +static inline void release_dotclk_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); +} + +#endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-mx28/include/mach/mx28.h b/arch/arm/mach-mx28/include/mach/mx28.h new file mode 100644 index 000000000000..097253266709 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/mx28.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_MX28_H__ +#define __ASM_ARCH_MACH_MX28_H__ + +#include <asm/sizes.h> + +#define MX28_SOC_IO_PHYS_BASE 0x80000000 +#define MX28_SOC_IO_VIRT_BASE 0xF0000000 +#define MX28_SOC_IO_AREA_SIZE SZ_1M + +/* Virtual address where OCRAM is mapped */ +#define MX28_OCRAM_PHBASE 0x00000000 +#ifdef __ASSEMBLER__ +#define MX28_OCRAM_BASE 0xf1000000 +#else +#define MX28_OCRAM_BASE (void __iomem *)0xf1000000 +#endif +#define MX28_OCRAM_SIZE (128 * SZ_1K) + + +#define ICOLL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x000000) +#define HSADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x002000) +#define APBH_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x004000) +#define PERFMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x006000) +#define BCH_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00A000) +#define GPMI_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00C000) +#define SSP0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x010000) +#define SSP1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x012000) +#define SSP2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x014000) +#define SSP3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x016000) +#define PINCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x018000) +#define DIGCTL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x01C000) +#define ETM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x022000) +#define APBX_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x024000) +#define DCP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x028000) +#define PXP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02A000) +#define OCOTP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02C000) +#define AXI_AHB0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02E000) +#define LCDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x030000) +#define CAN0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x032000) +#define CAN1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x034000) +#define SIMDBG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C000) +#define SIMGPMISEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C200) +#define SIMSSPSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C300) +#define SIMMEMSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C400) +#define GPIOMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C500) +#define SIMENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C700) +#define ARMJTAG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C800) +#define CLKCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x040000) +#define SAIF0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x042000) +#define POWER_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x044000) +#define SAIF1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x046000) +#define LRADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x050000) +#define SPDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x054000) +#define RTC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x056000) +#define I2C0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x058000) +#define I2C1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x05A000) +#define PWM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x064000) +#define TIMROT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x068000) +#define AUART0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06A000) +#define AUART1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06C000) +#define AUART2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06E000) +#define AUART3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x070000) +#define AUART4_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x072000) +#define DUART_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x074000) +#define USBPHY0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07C000) +#define USBPHY1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07E000) +#define USBCTRL0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x080000) +#define USBCTRL1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x090000) +#define DFLPT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0C0000) +#define DRAM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0E0000) +#define ENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0F0000) + +/* IRQ Definitions */ +#define IRQ_BATT_BRNOUT 0 +#define IRQ_VDDD_BRNOUT 1 +#define IRQ_VDDIO_BRNOUT 2 +#define IRQ_VDDA_BRNOUT 3 +#define IRQ_VDD5V_DROOP 4 +#define IRQ_DCDC4P2_BRNOUT 5 +#define IRQ_VDD5V 6 +#define IRQ_RESV7 7 +#define IRQ_CAN0 8 +#define IRQ_CAN1 9 +#define IRQ_LRADC_TOUCH 10 +#define IRQ_RESV11 11 +#define IRQ_RESV12 12 +#define IRQ_HSADC 13 +#define IRQ_IRADC_THRESH0 14 +#define IRQ_IRADC_THRESH1 15 +#define IRQ_LRADC_CH0 16 +#define IRQ_LRADC_CH1 17 +#define IRQ_LRADC_CH2 18 +#define IRQ_LRADC_CH3 19 +#define IRQ_LRADC_CH4 20 +#define IRQ_LRADC_CH5 21 +#define IRQ_LRADC_CH6 22 +#define IRQ_LRADC_CH7 23 +#define IRQ_LRADC_BUTTON0 24 +#define IRQ_LRADC_BUTTON1 25 +#define IRQ_RESV26 26 +#define IRQ_PERFMON 27 +#define IRQ_RTC_1MSEC 28 +#define IRQ_RTC_ALARM 29 +#define IRQ_RESV30 30 +#define IRQ_COMMS 31 +#define IRQ_EMI_ERR 32 +#define IRQ_RESV33 33 +#define IRQ_RESV34 34 +#define IRQ_RESV35 35 +#define IRQ_RESV36 36 +#define IRQ_RESV37 37 +#define IRQ_LCDIF 38 +#define IRQ_PXP 39 +#define IRQ_RESV40 40 +#define IRQ_BCH 41 +#define IRQ_GPMI 42 +#define IRQ_RESV43 43 +#define IRQ_RESV44 44 +#define IRQ_SPDIF_ERROR 45 +#define IRQ_RESV46 46 +#define IRQ_DUART 47 +#define IRQ_TIMER0 48 +#define IRQ_TIMER1 49 +#define IRQ_TIMER2 50 +#define IRQ_TIMER3 51 +#define IRQ_DCP_VMI 52 +#define IRQ_DCP 53 +#define IRQ_DCP_SECURE 54 +#define IRQ_RESV55 55 +#define IRQ_RESV56 56 +#define IRQ_RESV57 57 +#define IRQ_SAIF1 58 +#define IRQ_SAIF0 59 +#define IRQ_RESV60 60 +#define IRQ_RESV61 61 +#define IRQ_RESV62 62 +#define IRQ_RESV63 63 +#define IRQ_RESV64 64 +#define IRQ_RESV65 65 +#define IRQ_SPDIF_DMA 66 +#define IRQ_RESV67 67 +#define IRQ_I2C0_DMA 68 +#define IRQ_I2C1_DMA 69 +#define IRQ_AUART0_RX_DMA 70 +#define IRQ_AUART0_TX_DMA 71 +#define IRQ_AUART1_RX_DMA 72 +#define IRQ_AUART1_TX_DMA 73 +#define IRQ_AUART2_RX_DMA 74 +#define IRQ_AUART2_TX_DMA 75 +#define IRQ_AUART3_RX_DMA 76 +#define IRQ_AUART3_TX_DMA 77 +#define IRQ_AUART4_RX_DMA 78 +#define IRQ_AUART4_TX_DMA 79 +#define IRQ_SAIF0_DMA 80 +#define IRQ_SAIF1_DMA 81 +#define IRQ_SSP0_DMA 82 +#define IRQ_SSP1_DMA 83 +#define IRQ_SSP2_DMA 84 +#define IRQ_SSP3_DMA 85 +#define IRQ_LCDIF_DMA 86 +#define IRQ_HSADC_DMA 87 +#define IRQ_GPMI_DMA 88 +#define IRQ_DIGCTL_DEBUG_TRAP 89 +#define IRQ_RESV90 90 +#define IRQ_RESV91 91 +#define IRQ_USB1 92 +#define IRQ_USB0 93 +#define IRQ_USB1_WAKEUP 94 +#define IRQ_USB0_WAKEUP 95 +#define IRQ_SSP0 96 +#define IRQ_SSP1 97 +#define IRQ_SSP2 98 +#define IRQ_SSP3 99 +#define IRQ_ENET_SWI 100 +#define IRQ_ENET_MAC0 101 +#define IRQ_ENET_MAC1 102 +#define IRQ_ENET_MAC0_1588 103 +#define IRQ_ENET_MAC1_1588 104 +#define IRQ_RESV105 105 +#define IRQ_RESV106 106 +#define IRQ_RESV107 107 +#define IRQ_RESV108 108 +#define IRQ_RESV109 109 +#define IRQ_I2C1_ERROR 110 +#define IRQ_I2C0_ERROR 111 +#define IRQ_AUART0 112 +#define IRQ_AUART1 113 +#define IRQ_AUART2 114 +#define IRQ_AUART3 115 +#define IRQ_AUART4 116 +#define IRQ_RESV117 117 +#define IRQ_RESV118 118 +#define IRQ_RESV119 119 +#define IRQ_RESV120 120 +#define IRQ_RESV121 121 +#define IRQ_RESV122 122 +#define IRQ_GPIO4 123 +#define IRQ_GPIO3 124 +#define IRQ_GPIO2 125 +#define IRQ_GPIO1 126 +#define IRQ_GPIO0 127 + +#define ARCH_NR_IRQS 128 + +/* On i.MX28, all interrupt sources can be configured as FIQ */ +#define FIQ_START IRQ_BATT_BRNOUT + +#define MX28_SOC_IO_ADDRESS(x) \ + ((x) - MX28_SOC_IO_PHYS_BASE + MX28_SOC_IO_VIRT_BASE) + +#ifdef __ASSEMBLER__ +#define IO_ADDRESS(x) \ + MX28_SOC_IO_ADDRESS(x) +#else +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + (((x) >= (unsigned long)MX28_SOC_IO_PHYS_BASE) && \ + ((x) < (unsigned long)MX28_SOC_IO_PHYS_BASE + \ + MX28_SOC_IO_AREA_SIZE) ? \ + MX28_SOC_IO_ADDRESS(x) : 0xDEADBEEF) +#endif + +#ifdef CONFIG_MXS_EARLY_CONSOLE +#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR +#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR) +#endif +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/regs-apbh.h b/arch/arm/mach-mx28/include/mach/regs-apbh.h new file mode 100644 index 000000000000..23f26ca10e9e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-apbh.h @@ -0,0 +1,535 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 16) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_CHANNEL_CTRL (0x00000030) +#define HW_APBH_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBH_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBH_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__LCDIF 0x2000 +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_DEVSEL (0x00000040) + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 +#define BF_APBH_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBH_DEVSEL_CH15) +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 +#define BF_APBH_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH14) +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 +#define BF_APBH_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBH_DEVSEL_CH13) +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 +#define BF_APBH_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH12) +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 +#define BF_APBH_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBH_DEVSEL_CH11) +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 +#define BF_APBH_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH10) +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 +#define BF_APBH_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBH_DEVSEL_CH9) +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 +#define BF_APBH_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH8) +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +#define HW_APBH_DMA_BURST_SIZE (0x00000050) + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 +#define BF_APBH_DMA_BURST_SIZE_CH15(v) \ + (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 +#define BF_APBH_DMA_BURST_SIZE_CH14(v) \ + (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 +#define BF_APBH_DMA_BURST_SIZE_CH13(v) \ + (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 +#define BF_APBH_DMA_BURST_SIZE_CH12(v) \ + (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 +#define BF_APBH_DMA_BURST_SIZE_CH11(v) \ + (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 +#define BF_APBH_DMA_BURST_SIZE_CH10(v) \ + (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 +#define BF_APBH_DMA_BURST_SIZE_CH9(v) \ + (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 +#define BF_APBH_DMA_BURST_SIZE_CH8(v) \ + (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 +#define BF_APBH_DMA_BURST_SIZE_CH7(v) \ + (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 +#define BF_APBH_DMA_BURST_SIZE_CH6(v) \ + (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 +#define BF_APBH_DMA_BURST_SIZE_CH5(v) \ + (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 +#define BF_APBH_DMA_BURST_SIZE_CH4(v) \ + (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 +#define BF_APBH_DMA_BURST_SIZE_CH3(v) \ + (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 +#define BF_APBH_DMA_BURST_SIZE_CH2(v) \ + (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C +#define BF_APBH_DMA_BURST_SIZE_CH1(v) \ + (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 +#define BF_APBH_DMA_BURST_SIZE_CH0(v) \ + (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST8 0x2 + +#define HW_APBH_DEBUG (0x00000060) + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE +#define BF_APBH_DEBUG_RSVD(v) \ + (((v) << 1) & BM_APBH_DEBUG_RSVD) +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x00000800) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-i2c.h b/arch/arm/mach-mx28/include/mach/regs-i2c.h new file mode 100644 index 000000000000..71997445f44e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-i2c.h @@ -0,0 +1,498 @@ +/* + * Freescale I2C Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.54 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___I2C_H +#define __ARCH_ARM___I2C_H + + +#define HW_I2C_CTRL0 (0x00000000) +#define HW_I2C_CTRL0_SET (0x00000004) +#define HW_I2C_CTRL0_CLR (0x00000008) +#define HW_I2C_CTRL0_TOG (0x0000000c) + +#define BM_I2C_CTRL0_SFTRST 0x80000000 +#define BV_I2C_CTRL0_SFTRST__RUN 0x0 +#define BV_I2C_CTRL0_SFTRST__RESET 0x1 +#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#define BV_I2C_CTRL0_CLKGATE__RUN 0x0 +#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_I2C_CTRL0_RUN 0x20000000 +#define BV_I2C_CTRL0_RUN__HALT 0x0 +#define BV_I2C_CTRL0_RUN__RUN 0x1 +#define BM_I2C_CTRL0_RSVD2 0x10000000 +#define BM_I2C_CTRL0_PRE_ACK 0x08000000 +#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000 +#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_CTRL0_RSVD1 0x01000000 +#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000 +#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000 +#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 +#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 +#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 +#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 +#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 +#define BM_I2C_CTRL0_DIRECTION 0x00010000 +#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 +#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_CTRL0_XFER_COUNT 0 +#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_I2C_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT) + +#define HW_I2C_TIMING0 (0x00000010) +#define HW_I2C_TIMING0_SET (0x00000014) +#define HW_I2C_TIMING0_CLR (0x00000018) +#define HW_I2C_TIMING0_TOG (0x0000001c) + +#define BP_I2C_TIMING0_RSVD2 26 +#define BM_I2C_TIMING0_RSVD2 0xFC000000 +#define BF_I2C_TIMING0_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING0_RSVD2) +#define BP_I2C_TIMING0_HIGH_COUNT 16 +#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000 +#define BF_I2C_TIMING0_HIGH_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT) +#define BP_I2C_TIMING0_RSVD1 10 +#define BM_I2C_TIMING0_RSVD1 0x0000FC00 +#define BF_I2C_TIMING0_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING0_RSVD1) +#define BP_I2C_TIMING0_RCV_COUNT 0 +#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF +#define BF_I2C_TIMING0_RCV_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT) + +#define HW_I2C_TIMING1 (0x00000020) +#define HW_I2C_TIMING1_SET (0x00000024) +#define HW_I2C_TIMING1_CLR (0x00000028) +#define HW_I2C_TIMING1_TOG (0x0000002c) + +#define BP_I2C_TIMING1_RSVD2 26 +#define BM_I2C_TIMING1_RSVD2 0xFC000000 +#define BF_I2C_TIMING1_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING1_RSVD2) +#define BP_I2C_TIMING1_LOW_COUNT 16 +#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000 +#define BF_I2C_TIMING1_LOW_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT) +#define BP_I2C_TIMING1_RSVD1 10 +#define BM_I2C_TIMING1_RSVD1 0x0000FC00 +#define BF_I2C_TIMING1_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING1_RSVD1) +#define BP_I2C_TIMING1_XMIT_COUNT 0 +#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF +#define BF_I2C_TIMING1_XMIT_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT) + +#define HW_I2C_TIMING2 (0x00000030) +#define HW_I2C_TIMING2_SET (0x00000034) +#define HW_I2C_TIMING2_CLR (0x00000038) +#define HW_I2C_TIMING2_TOG (0x0000003c) + +#define BP_I2C_TIMING2_RSVD2 26 +#define BM_I2C_TIMING2_RSVD2 0xFC000000 +#define BF_I2C_TIMING2_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING2_RSVD2) +#define BP_I2C_TIMING2_BUS_FREE 16 +#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000 +#define BF_I2C_TIMING2_BUS_FREE(v) \ + (((v) << 16) & BM_I2C_TIMING2_BUS_FREE) +#define BP_I2C_TIMING2_RSVD1 10 +#define BM_I2C_TIMING2_RSVD1 0x0000FC00 +#define BF_I2C_TIMING2_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING2_RSVD1) +#define BP_I2C_TIMING2_LEADIN_COUNT 0 +#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF +#define BF_I2C_TIMING2_LEADIN_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT) + +#define HW_I2C_CTRL1 (0x00000040) +#define HW_I2C_CTRL1_SET (0x00000044) +#define HW_I2C_CTRL1_CLR (0x00000048) +#define HW_I2C_CTRL1_TOG (0x0000004c) + +#define BM_I2C_CTRL1_RSVD1 0x80000000 +#define BM_I2C_CTRL1_RD_QUEUE_IRQ 0x40000000 +#define BV_I2C_CTRL1_RD_QUEUE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_RD_QUEUE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_WR_QUEUE_IRQ 0x20000000 +#define BV_I2C_CTRL1_WR_QUEUE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_WR_QUEUE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 +#define BM_I2C_CTRL1_ACK_MODE 0x08000000 +#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 +#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 +#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000 +#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000 +#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 +#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 +#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000 +#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \ + (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE) +#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 +#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 + +#define HW_I2C_STAT (0x00000050) + +#define BM_I2C_STAT_MASTER_PRESENT 0x80000000 +#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 +#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 +#define BM_I2C_STAT_GOT_A_NAK 0x10000000 +#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 +#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 +#define BP_I2C_STAT_RSVD1 24 +#define BM_I2C_STAT_RSVD1 0x0F000000 +#define BF_I2C_STAT_RSVD1(v) \ + (((v) << 24) & BM_I2C_STAT_RSVD1) +#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 +#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000 +#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \ + (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR) +#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 +#define BM_I2C_STAT_SLAVE_FOUND 0x00004000 +#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 +#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000 +#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 +#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 +#define BM_I2C_STAT_BUS_BUSY 0x00000800 +#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 +#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 +#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400 +#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 +#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 +#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_SLAVE_BUSY 0x00000100 +#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 + +#define HW_I2C_QUEUECTRL (0x00000060) +#define HW_I2C_QUEUECTRL_SET (0x00000064) +#define HW_I2C_QUEUECTRL_CLR (0x00000068) +#define HW_I2C_QUEUECTRL_TOG (0x0000006c) + +#define BP_I2C_QUEUECTRL_RSVD3 21 +#define BM_I2C_QUEUECTRL_RSVD3 0xFFE00000 +#define BF_I2C_QUEUECTRL_RSVD3(v) \ + (((v) << 21) & BM_I2C_QUEUECTRL_RSVD3) +#define BP_I2C_QUEUECTRL_RD_THRESH 16 +#define BM_I2C_QUEUECTRL_RD_THRESH 0x001F0000 +#define BF_I2C_QUEUECTRL_RD_THRESH(v) \ + (((v) << 16) & BM_I2C_QUEUECTRL_RD_THRESH) +#define BP_I2C_QUEUECTRL_RSVD2 13 +#define BM_I2C_QUEUECTRL_RSVD2 0x0000E000 +#define BF_I2C_QUEUECTRL_RSVD2(v) \ + (((v) << 13) & BM_I2C_QUEUECTRL_RSVD2) +#define BP_I2C_QUEUECTRL_WR_THRESH 8 +#define BM_I2C_QUEUECTRL_WR_THRESH 0x00001F00 +#define BF_I2C_QUEUECTRL_WR_THRESH(v) \ + (((v) << 8) & BM_I2C_QUEUECTRL_WR_THRESH) +#define BP_I2C_QUEUECTRL_RSVD1 6 +#define BM_I2C_QUEUECTRL_RSVD1 0x000000C0 +#define BF_I2C_QUEUECTRL_RSVD1(v) \ + (((v) << 6) & BM_I2C_QUEUECTRL_RSVD1) +#define BM_I2C_QUEUECTRL_QUEUE_RUN 0x00000020 +#define BV_I2C_QUEUECTRL_QUEUE_RUN__STOP 0x0 +#define BV_I2C_QUEUECTRL_QUEUE_RUN__START 0x1 +#define BM_I2C_QUEUECTRL_RD_CLEAR 0x00000010 +#define BM_I2C_QUEUECTRL_WR_CLEAR 0x00000008 +#define BM_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x00000004 +#define BM_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN 0x00000002 +#define BV_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN 0x00000001 +#define BV_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN__ENABLED 0x1 + +#define HW_I2C_QUEUESTAT (0x00000070) +#define HW_I2C_QUEUESTAT_SET (0x00000074) +#define HW_I2C_QUEUESTAT_CLR (0x00000078) +#define HW_I2C_QUEUESTAT_TOG (0x0000007c) + +#define BP_I2C_QUEUESTAT_RSVD2 15 +#define BM_I2C_QUEUESTAT_RSVD2 0xFFFF8000 +#define BF_I2C_QUEUESTAT_RSVD2(v) \ + (((v) << 15) & BM_I2C_QUEUESTAT_RSVD2) +#define BM_I2C_QUEUESTAT_RD_QUEUE_FULL 0x00004000 +#define BM_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 +#define BP_I2C_QUEUESTAT_RD_QUEUE_CNT 8 +#define BM_I2C_QUEUESTAT_RD_QUEUE_CNT 0x00001F00 +#define BF_I2C_QUEUESTAT_RD_QUEUE_CNT(v) \ + (((v) << 8) & BM_I2C_QUEUESTAT_RD_QUEUE_CNT) +#define BM_I2C_QUEUESTAT_RSVD1 0x00000080 +#define BM_I2C_QUEUESTAT_WR_QUEUE_FULL 0x00000040 +#define BM_I2C_QUEUESTAT_WR_QUEUE_EMPTY 0x00000020 +#define BP_I2C_QUEUESTAT_WR_QUEUE_CNT 0 +#define BM_I2C_QUEUESTAT_WR_QUEUE_CNT 0x0000001F +#define BF_I2C_QUEUESTAT_WR_QUEUE_CNT(v) \ + (((v) << 0) & BM_I2C_QUEUESTAT_WR_QUEUE_CNT) + +#define HW_I2C_QUEUECMD (0x00000080) +#define HW_I2C_QUEUECMD_SET (0x00000084) +#define HW_I2C_QUEUECMD_CLR (0x00000088) +#define HW_I2C_QUEUECMD_TOG (0x0000008c) + +#define BP_I2C_QUEUECMD_RSVD2 28 +#define BM_I2C_QUEUECMD_RSVD2 0xF0000000 +#define BF_I2C_QUEUECMD_RSVD2(v) \ + (((v) << 28) & BM_I2C_QUEUECMD_RSVD2) +#define BM_I2C_QUEUECMD_PRE_ACK 0x08000000 +#define BM_I2C_QUEUECMD_ACKNOWLEDGE 0x04000000 +#define BV_I2C_QUEUECMD_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_QUEUECMD_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_QUEUECMD_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_QUEUECMD_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_QUEUECMD_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_QUEUECMD_RSVD1 0x01000000 +#define BM_I2C_QUEUECMD_MULTI_MASTER 0x00800000 +#define BV_I2C_QUEUECMD_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_QUEUECMD_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_QUEUECMD_CLOCK_HELD 0x00400000 +#define BV_I2C_QUEUECMD_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_QUEUECMD_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_QUEUECMD_RETAIN_CLOCK 0x00200000 +#define BV_I2C_QUEUECMD_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_QUEUECMD_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_QUEUECMD_POST_SEND_STOP 0x00100000 +#define BV_I2C_QUEUECMD_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_QUEUECMD_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_QUEUECMD_PRE_SEND_START 0x00080000 +#define BV_I2C_QUEUECMD_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_QUEUECMD_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_QUEUECMD_MASTER_MODE 0x00020000 +#define BV_I2C_QUEUECMD_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_QUEUECMD_MASTER_MODE__MASTER 0x1 +#define BM_I2C_QUEUECMD_DIRECTION 0x00010000 +#define BV_I2C_QUEUECMD_DIRECTION__RECEIVE 0x0 +#define BV_I2C_QUEUECMD_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_QUEUECMD_XFER_COUNT 0 +#define BM_I2C_QUEUECMD_XFER_COUNT 0x0000FFFF +#define BF_I2C_QUEUECMD_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_QUEUECMD_XFER_COUNT) + +#define HW_I2C_QUEUEDATA (0x00000090) + +#define BP_I2C_QUEUEDATA_DATA 0 +#define BM_I2C_QUEUEDATA_DATA 0xFFFFFFFF +#define BF_I2C_QUEUEDATA_DATA(v) (v) + +#define HW_I2C_DATA (0x000000a0) + +#define BP_I2C_DATA_DATA 0 +#define BM_I2C_DATA_DATA 0xFFFFFFFF +#define BF_I2C_DATA_DATA(v) (v) + +#define HW_I2C_DEBUG0 (0x000000b0) +#define HW_I2C_DEBUG0_SET (0x000000b4) +#define HW_I2C_DEBUG0_CLR (0x000000b8) +#define HW_I2C_DEBUG0_TOG (0x000000bc) + +#define BM_I2C_DEBUG0_DMAREQ 0x80000000 +#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 +#define BM_I2C_DEBUG0_DMAKICK 0x20000000 +#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 +#define BP_I2C_DEBUG0_STATE_VALUE 26 +#define BM_I2C_DEBUG0_STATE_VALUE 0x0C000000 +#define BF_I2C_DEBUG0_STATE_VALUE(v) \ + (((v) << 26) & BM_I2C_DEBUG0_STATE_VALUE) +#define BP_I2C_DEBUG0_DMA_STATE 16 +#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000 +#define BF_I2C_DEBUG0_DMA_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE) +#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000 +#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000 +#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000 +#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000 +#define BM_I2C_DEBUG0_STATE_LATCH 0x00000800 +#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400 +#define BP_I2C_DEBUG0_SLAVE_STATE 0 +#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF +#define BF_I2C_DEBUG0_SLAVE_STATE(v) \ + (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE) + +#define HW_I2C_DEBUG1 (0x000000c0) +#define HW_I2C_DEBUG1_SET (0x000000c4) +#define HW_I2C_DEBUG1_CLR (0x000000c8) +#define HW_I2C_DEBUG1_TOG (0x000000cc) + +#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 +#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 +#define BP_I2C_DEBUG1_RSVD4 28 +#define BM_I2C_DEBUG1_RSVD4 0x30000000 +#define BF_I2C_DEBUG1_RSVD4(v) \ + (((v) << 28) & BM_I2C_DEBUG1_RSVD4) +#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 +#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000 +#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \ + (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES) +#define BP_I2C_DEBUG1_CLK_GEN_STATE 16 +#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000 +#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE) +#define BP_I2C_DEBUG1_RSVD2 11 +#define BM_I2C_DEBUG1_RSVD2 0x0000F800 +#define BF_I2C_DEBUG1_RSVD2(v) \ + (((v) << 11) & BM_I2C_DEBUG1_RSVD2) +#define BP_I2C_DEBUG1_LST_MODE 9 +#define BM_I2C_DEBUG1_LST_MODE 0x00000600 +#define BF_I2C_DEBUG1_LST_MODE(v) \ + (((v) << 9) & BM_I2C_DEBUG1_LST_MODE) +#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 +#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 +#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 +#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 +#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100 +#define BP_I2C_DEBUG1_RSVD1 5 +#define BM_I2C_DEBUG1_RSVD1 0x000000E0 +#define BF_I2C_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_I2C_DEBUG1_RSVD1) +#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010 +#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008 +#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004 +#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002 +#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001 + +#define HW_I2C_VERSION (0x000000d0) + +#define BP_I2C_VERSION_MAJOR 24 +#define BM_I2C_VERSION_MAJOR 0xFF000000 +#define BF_I2C_VERSION_MAJOR(v) \ + (((v) << 24) & BM_I2C_VERSION_MAJOR) +#define BP_I2C_VERSION_MINOR 16 +#define BM_I2C_VERSION_MINOR 0x00FF0000 +#define BF_I2C_VERSION_MINOR(v) \ + (((v) << 16) & BM_I2C_VERSION_MINOR) +#define BP_I2C_VERSION_STEP 0 +#define BM_I2C_VERSION_STEP 0x0000FFFF +#define BF_I2C_VERSION_STEP(v) \ + (((v) << 0) & BM_I2C_VERSION_STEP) +#endif /* __ARCH_ARM___I2C_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-icoll.h b/arch/arm/mach-mx28/include/mach/regs-icoll.h new file mode 100644 index 000000000000..f06ac0d4720b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-icoll.h @@ -0,0 +1,293 @@ +/* + * Freescale ICOLL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H + +#define HW_ICOLL_VECTOR (0x00000000) +#define HW_ICOLL_VECTOR_SET (0x00000004) +#define HW_ICOLL_VECTOR_CLR (0x00000008) +#define HW_ICOLL_VECTOR_TOG (0x0000000c) + +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +#define BP_ICOLL_VECTOR_RSRVD1 0 +#define BM_ICOLL_VECTOR_RSRVD1 0x00000003 +#define BF_ICOLL_VECTOR_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VECTOR_RSRVD1) + +#define HW_ICOLL_LEVELACK (0x00000010) + +#define BP_ICOLL_LEVELACK_RSRVD1 4 +#define BM_ICOLL_LEVELACK_RSRVD1 0xFFFFFFF0 +#define BF_ICOLL_LEVELACK_RSRVD1(v) \ + (((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1) +#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 + +#define HW_ICOLL_CTRL (0x00000020) +#define HW_ICOLL_CTRL_SET (0x00000024) +#define HW_ICOLL_CTRL_CLR (0x00000028) +#define HW_ICOLL_CTRL_TOG (0x0000002c) + +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_RSRVD3 24 +#define BM_ICOLL_CTRL_RSRVD3 0x3F000000 +#define BF_ICOLL_CTRL_RSRVD3(v) \ + (((v) << 24) & BM_ICOLL_CTRL_RSRVD3) +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +#define BP_ICOLL_CTRL_RSRVD1 0 +#define BM_ICOLL_CTRL_RSRVD1 0x0000FFFF +#define BF_ICOLL_CTRL_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_CTRL_RSRVD1) + +#define HW_ICOLL_VBASE (0x00000040) +#define HW_ICOLL_VBASE_SET (0x00000044) +#define HW_ICOLL_VBASE_CLR (0x00000048) +#define HW_ICOLL_VBASE_TOG (0x0000004c) + +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +#define BP_ICOLL_VBASE_RSRVD1 0 +#define BM_ICOLL_VBASE_RSRVD1 0x00000003 +#define BF_ICOLL_VBASE_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VBASE_RSRVD1) + +#define HW_ICOLL_STAT (0x00000070) + +#define BP_ICOLL_STAT_RSRVD1 7 +#define BM_ICOLL_STAT_RSRVD1 0xFFFFFF80 +#define BF_ICOLL_STAT_RSRVD1(v) \ + (((v) << 7) & BM_ICOLL_STAT_RSRVD1) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) + +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_RAWn(n) (0x000000a0 + (n) * 0x10) +#define HW_ICOLL_RAWn_SET(n) (0x000000a4 + (n) * 0x10) +#define HW_ICOLL_RAWn_CLR(n) (0x000000a8 + (n) * 0x10) +#define HW_ICOLL_RAWn_TOG(n) (0x000000ac + (n) * 0x10) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) + +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +#define HW_ICOLL_INTERRUPTn(n) (0x00000120 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (0x00000124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x00000128 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_TOG(n) (0x0000012c + (n) * 0x10) +#define BP_ICOLL_INTERRUPTn_RSRVD1 5 +#define BM_ICOLL_INTERRUPTn_RSRVD1 0xFFFFFFE0 +#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \ + (((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 + +#define HW_ICOLL_DEBUG (0x00001120) +#define HW_ICOLL_DEBUG_SET (0x00001124) +#define HW_ICOLL_DEBUG_CLR (0x00001128) +#define HW_ICOLL_DEBUG_TOG (0x0000112c) + +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_RSRVD2 18 +#define BM_ICOLL_DEBUG_RSRVD2 0x000C0000 +#define BF_ICOLL_DEBUG_RSRVD2(v) \ + (((v) << 18) & BM_ICOLL_DEBUG_RSRVD2) +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_RSRVD1 10 +#define BM_ICOLL_DEBUG_RSRVD1 0x0000FC00 +#define BF_ICOLL_DEBUG_RSRVD1(v) \ + (((v) << 10) & BM_ICOLL_DEBUG_RSRVD1) +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 + +#define HW_ICOLL_DBGREAD0 (0x00001130) +#define HW_ICOLL_DBGREAD0_SET (0x00001134) +#define HW_ICOLL_DBGREAD0_CLR (0x00001138) +#define HW_ICOLL_DBGREAD0_TOG (0x0000113c) + +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) + +#define HW_ICOLL_DBGREAD1 (0x00001140) +#define HW_ICOLL_DBGREAD1_SET (0x00001144) +#define HW_ICOLL_DBGREAD1_CLR (0x00001148) +#define HW_ICOLL_DBGREAD1_TOG (0x0000114c) + +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) + +#define HW_ICOLL_DBGFLAG (0x00001150) +#define HW_ICOLL_DBGFLAG_SET (0x00001154) +#define HW_ICOLL_DBGFLAG_CLR (0x00001158) +#define HW_ICOLL_DBGFLAG_TOG (0x0000115c) + +#define BP_ICOLL_DBGFLAG_RSRVD1 16 +#define BM_ICOLL_DBGFLAG_RSRVD1 0xFFFF0000 +#define BF_ICOLL_DBGFLAG_RSRVD1(v) \ + (((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) + +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_DBGREQUESTn(n) (0x00001160 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_SET(n) (0x00001164 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_CLR(n) (0x00001168 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_TOG(n) (0x0000116c + (n) * 0x10) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) + +#define HW_ICOLL_VERSION (0x000011e0) + +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-lcdif.h b/arch/arm/mach-mx28/include/mach/regs-lcdif.h new file mode 100644 index 000000000000..6a0e008be308 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-lcdif.h @@ -0,0 +1,680 @@ +/* + * Freescale LCDIF Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.32 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LCDIF_H +#define __ARCH_ARM___LCDIF_H + + +#define HW_LCDIF_CTRL (0x00000000) +#define HW_LCDIF_CTRL_SET (0x00000004) +#define HW_LCDIF_CTRL_CLR (0x00000008) +#define HW_LCDIF_CTRL_TOG (0x0000000c) + +#define BM_LCDIF_CTRL_SFTRST 0x80000000 +#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_LCDIF_CTRL_READ_WRITEB 0x10000000 +#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_LCDIF_CTRL_WORD_LENGTH 8 +#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_LCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH) +#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 +#define BM_LCDIF_CTRL_RSRVD0 0x00000010 +#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_LCDIF_CTRL_RUN 0x00000001 + +#define HW_LCDIF_CTRL1 (0x00000010) +#define HW_LCDIF_CTRL1_SET (0x00000014) +#define HW_LCDIF_CTRL1_CLR (0x00000018) +#define HW_LCDIF_CTRL1_TOG (0x0000001c) + +#define BP_LCDIF_CTRL1_RSRVD1 28 +#define BM_LCDIF_CTRL1_RSRVD1 0xF0000000 +#define BF_LCDIF_CTRL1_RSRVD1(v) \ + (((v) << 28) & BM_LCDIF_CTRL1_RSRVD1) +#define BM_LCDIF_CTRL1_COMBINE_MPU_WR_STRB 0x08000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BP_LCDIF_CTRL1_RSRVD0 3 +#define BM_LCDIF_CTRL1_RSRVD0 0x000000F8 +#define BF_LCDIF_CTRL1_RSRVD0(v) \ + (((v) << 3) & BM_LCDIF_CTRL1_RSRVD0) +#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_LCDIF_CTRL1_MODE86 0x00000002 +#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_LCDIF_CTRL1_RESET 0x00000001 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_LCDIF_CTRL2 (0x00000020) +#define HW_LCDIF_CTRL2_SET (0x00000024) +#define HW_LCDIF_CTRL2_CLR (0x00000028) +#define HW_LCDIF_CTRL2_TOG (0x0000002c) + +#define BP_LCDIF_CTRL2_RSRVD5 24 +#define BM_LCDIF_CTRL2_RSRVD5 0xFF000000 +#define BF_LCDIF_CTRL2_RSRVD5(v) \ + (((v) << 24) & BM_LCDIF_CTRL2_RSRVD5) +#define BP_LCDIF_CTRL2_OUTSTANDING_REQS 21 +#define BM_LCDIF_CTRL2_OUTSTANDING_REQS 0x00E00000 +#define BF_LCDIF_CTRL2_OUTSTANDING_REQS(v) \ + (((v) << 21) & BM_LCDIF_CTRL2_OUTSTANDING_REQS) +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_1 0x0 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_2 0x1 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_4 0x2 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_8 0x3 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4 +#define BM_LCDIF_CTRL2_BURST_LEN_8 0x00100000 +#define BM_LCDIF_CTRL2_RSRVD4 0x00080000 +#define BP_LCDIF_CTRL2_ODD_LINE_PATTERN 16 +#define BM_LCDIF_CTRL2_ODD_LINE_PATTERN 0x00070000 +#define BF_LCDIF_CTRL2_ODD_LINE_PATTERN(v) \ + (((v) << 16) & BM_LCDIF_CTRL2_ODD_LINE_PATTERN) +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5 +#define BM_LCDIF_CTRL2_RSRVD3 0x00008000 +#define BP_LCDIF_CTRL2_EVEN_LINE_PATTERN 12 +#define BM_LCDIF_CTRL2_EVEN_LINE_PATTERN 0x00007000 +#define BF_LCDIF_CTRL2_EVEN_LINE_PATTERN(v) \ + (((v) << 12) & BM_LCDIF_CTRL2_EVEN_LINE_PATTERN) +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5 +#define BM_LCDIF_CTRL2_RSRVD2 0x00000800 +#define BM_LCDIF_CTRL2_READ_PACK_DIR 0x00000400 +#define BM_LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT 0x00000200 +#define BM_LCDIF_CTRL2_READ_MODE_6_BIT_INPUT 0x00000100 +#define BM_LCDIF_CTRL2_RSRVD1 0x00000080 +#define BP_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 4 +#define BM_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 0x00000070 +#define BF_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v) \ + (((v) << 4) & BM_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS) +#define BP_LCDIF_CTRL2_INITIAL_DUMMY_READ 1 +#define BM_LCDIF_CTRL2_INITIAL_DUMMY_READ 0x0000000E +#define BF_LCDIF_CTRL2_INITIAL_DUMMY_READ(v) \ + (((v) << 1) & BM_LCDIF_CTRL2_INITIAL_DUMMY_READ) +#define BM_LCDIF_CTRL2_RSRVD0 0x00000001 + +#define HW_LCDIF_TRANSFER_COUNT (0x00000030) + +#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT) + +#define HW_LCDIF_CUR_BUF (0x00000040) + +#define BP_LCDIF_CUR_BUF_ADDR 0 +#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_CUR_BUF_ADDR(v) (v) + +#define HW_LCDIF_NEXT_BUF (0x00000050) + +#define BP_LCDIF_NEXT_BUF_ADDR 0 +#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_LCDIF_TIMING (0x00000060) + +#define BP_LCDIF_TIMING_CMD_HOLD 24 +#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_LCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD) +#define BP_LCDIF_TIMING_CMD_SETUP 16 +#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_LCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP) +#define BP_LCDIF_TIMING_DATA_HOLD 8 +#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_LCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD) +#define BP_LCDIF_TIMING_DATA_SETUP 0 +#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_LCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP) + +#define HW_LCDIF_VDCTRL0 (0x00000070) +#define HW_LCDIF_VDCTRL0_SET (0x00000074) +#define HW_LCDIF_VDCTRL0_CLR (0x00000078) +#define HW_LCDIF_VDCTRL0_TOG (0x0000007c) + +#define BP_LCDIF_VDCTRL0_RSRVD2 30 +#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_LCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2) +#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_LCDIF_VDCTRL0_RSRVD1 22 +#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_LCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1) +#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_LCDIF_VDCTRL1 (0x00000080) + +#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_LCDIF_VDCTRL2 (0x00000090) + +#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 18 +#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFFFC0000 +#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 18) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD) + +#define HW_LCDIF_VDCTRL3 (0x000000a0) + +#define BP_LCDIF_VDCTRL3_RSRVD0 30 +#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0) +#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 +#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT) + +#define HW_LCDIF_VDCTRL4 (0x000000b0) + +#define BP_LCDIF_VDCTRL4_DOTCLK_DLY_SEL 29 +#define BM_LCDIF_VDCTRL4_DOTCLK_DLY_SEL 0xE0000000 +#define BF_LCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \ + (((v) << 29) & BM_LCDIF_VDCTRL4_DOTCLK_DLY_SEL) +#define BP_LCDIF_VDCTRL4_RSRVD0 19 +#define BM_LCDIF_VDCTRL4_RSRVD0 0x1FF80000 +#define BF_LCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0) +#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) + +#define HW_LCDIF_DVICTRL0 (0x000000c0) + +#define BP_LCDIF_DVICTRL0_RSRVD1 28 +#define BM_LCDIF_DVICTRL0_RSRVD1 0xF0000000 +#define BF_LCDIF_DVICTRL0_RSRVD1(v) \ + (((v) << 28) & BM_LCDIF_DVICTRL0_RSRVD1) +#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 16 +#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x0FFF0000 +#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_LCDIF_DVICTRL0_RSRVD0 12 +#define BM_LCDIF_DVICTRL0_RSRVD0 0x0000F000 +#define BF_LCDIF_DVICTRL0_RSRVD0(v) \ + (((v) << 12) & BM_LCDIF_DVICTRL0_RSRVD0) +#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 0 +#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x00000FFF +#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT) + +#define HW_LCDIF_DVICTRL1 (0x000000d0) + +#define BP_LCDIF_DVICTRL1_RSRVD0 30 +#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0) +#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE) +#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE) +#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE) + +#define HW_LCDIF_DVICTRL2 (0x000000e0) + +#define BP_LCDIF_DVICTRL2_RSRVD0 30 +#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0) +#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL3 (0x000000f0) + +#define BP_LCDIF_DVICTRL3_RSRVD0 30 +#define BM_LCDIF_DVICTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL3_RSRVD0) +#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 20 +#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 10 +#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE) +#define BP_LCDIF_DVICTRL3_V_LINES_CNT 0 +#define BM_LCDIF_DVICTRL3_V_LINES_CNT 0x000003FF +#define BF_LCDIF_DVICTRL3_V_LINES_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL3_V_LINES_CNT) + +#define HW_LCDIF_DVICTRL4 (0x00000100) + +#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT) + +#define HW_LCDIF_CSC_COEFF0 (0x00000110) + +#define BP_LCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1) +#define BP_LCDIF_CSC_COEFF0_C0 16 +#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_LCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0) +#define BP_LCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0) +#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 + +#define HW_LCDIF_CSC_COEFF1 (0x00000120) + +#define BP_LCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1) +#define BP_LCDIF_CSC_COEFF1_C2 16 +#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_LCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2) +#define BP_LCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0) +#define BP_LCDIF_CSC_COEFF1_C1 0 +#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_LCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1) + +#define HW_LCDIF_CSC_COEFF2 (0x00000130) + +#define BP_LCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1) +#define BP_LCDIF_CSC_COEFF2_C4 16 +#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_LCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4) +#define BP_LCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0) +#define BP_LCDIF_CSC_COEFF2_C3 0 +#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_LCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3) + +#define HW_LCDIF_CSC_COEFF3 (0x00000140) + +#define BP_LCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1) +#define BP_LCDIF_CSC_COEFF3_C6 16 +#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_LCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6) +#define BP_LCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0) +#define BP_LCDIF_CSC_COEFF3_C5 0 +#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_LCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5) + +#define HW_LCDIF_CSC_COEFF4 (0x00000150) + +#define BP_LCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1) +#define BP_LCDIF_CSC_COEFF4_C8 16 +#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_LCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8) +#define BP_LCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0) +#define BP_LCDIF_CSC_COEFF4_C7 0 +#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_LCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7) + +#define HW_LCDIF_CSC_OFFSET (0x00000160) + +#define BP_LCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1) +#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_LCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0) +#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_LCDIF_CSC_LIMIT (0x00000170) + +#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN) +#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX) + +#define HW_LCDIF_DATA (0x00000180) + +#define BP_LCDIF_DATA_DATA_THREE 24 +#define BM_LCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_LCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_LCDIF_DATA_DATA_THREE) +#define BP_LCDIF_DATA_DATA_TWO 16 +#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_LCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_LCDIF_DATA_DATA_TWO) +#define BP_LCDIF_DATA_DATA_ONE 8 +#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_LCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_LCDIF_DATA_DATA_ONE) +#define BP_LCDIF_DATA_DATA_ZERO 0 +#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_LCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO) + +#define HW_LCDIF_BM_ERROR_STAT (0x00000190) + +#define BP_LCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_LCDIF_CRC_STAT (0x000001a0) + +#define BP_LCDIF_CRC_STAT_CRC_VALUE 0 +#define BM_LCDIF_CRC_STAT_CRC_VALUE 0xFFFFFFFF +#define BF_LCDIF_CRC_STAT_CRC_VALUE(v) (v) + +#define HW_LCDIF_STAT (0x000001b0) + +#define BM_LCDIF_STAT_PRESENT 0x80000000 +#define BM_LCDIF_STAT_DMA_REQ 0x40000000 +#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000 +#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_LCDIF_STAT_BUSY 0x02000000 +#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_LCDIF_STAT_RSRVD0 9 +#define BM_LCDIF_STAT_RSRVD0 0x00FFFE00 +#define BF_LCDIF_STAT_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_STAT_RSRVD0) +#define BP_LCDIF_STAT_LFIFO_COUNT 0 +#define BM_LCDIF_STAT_LFIFO_COUNT 0x000001FF +#define BF_LCDIF_STAT_LFIFO_COUNT(v) \ + (((v) << 0) & BM_LCDIF_STAT_LFIFO_COUNT) + +#define HW_LCDIF_VERSION (0x000001c0) + +#define BP_LCDIF_VERSION_MAJOR 24 +#define BM_LCDIF_VERSION_MAJOR 0xFF000000 +#define BF_LCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LCDIF_VERSION_MAJOR) +#define BP_LCDIF_VERSION_MINOR 16 +#define BM_LCDIF_VERSION_MINOR 0x00FF0000 +#define BF_LCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_LCDIF_VERSION_MINOR) +#define BP_LCDIF_VERSION_STEP 0 +#define BM_LCDIF_VERSION_STEP 0x0000FFFF +#define BF_LCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_LCDIF_VERSION_STEP) + +#define HW_LCDIF_DEBUG0 (0x000001d0) + +#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_LCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_LCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_LCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_LCDIF_DEBUG0_CUR_STATE 16 +#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_LCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE) +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000 +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000 +#define BP_LCDIF_DEBUG0_CUR_REQ_STATE 10 +#define BM_LCDIF_DEBUG0_CUR_REQ_STATE 0x00000C00 +#define BF_LCDIF_DEBUG0_CUR_REQ_STATE(v) \ + (((v) << 10) & BM_LCDIF_DEBUG0_CUR_REQ_STATE) +#define BM_LCDIF_DEBUG0_MST_AVALID 0x00000200 +#define BP_LCDIF_DEBUG0_MST_OUTSTANDING_REQS 4 +#define BM_LCDIF_DEBUG0_MST_OUTSTANDING_REQS 0x000001F0 +#define BF_LCDIF_DEBUG0_MST_OUTSTANDING_REQS(v) \ + (((v) << 4) & BM_LCDIF_DEBUG0_MST_OUTSTANDING_REQS) +#define BP_LCDIF_DEBUG0_MST_WORDS 0 +#define BM_LCDIF_DEBUG0_MST_WORDS 0x0000000F +#define BF_LCDIF_DEBUG0_MST_WORDS(v) \ + (((v) << 0) & BM_LCDIF_DEBUG0_MST_WORDS) + +#define HW_LCDIF_DEBUG1 (0x000001e0) + +#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT) +#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT) + +#define HW_LCDIF_DEBUG2 (0x000001f0) + +#define BP_LCDIF_DEBUG2_MST_ADDRESS 0 +#define BM_LCDIF_DEBUG2_MST_ADDRESS 0xFFFFFFFF +#define BF_LCDIF_DEBUG2_MST_ADDRESS(v) (v) +#endif /* __ARCH_ARM___LCDIF_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-lradc.h b/arch/arm/mach-mx28/include/mach/regs-lradc.h new file mode 100644 index 000000000000..d7906b91c72e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-lradc.h @@ -0,0 +1,772 @@ +/* + * Freescale LRADC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LRADC_H +#define __ARCH_ARM___LRADC_H + + +#define HW_LRADC_CTRL0 (0x00000000) +#define HW_LRADC_CTRL0_SET (0x00000004) +#define HW_LRADC_CTRL0_CLR (0x00000008) +#define HW_LRADC_CTRL0_TOG (0x0000000c) + +#define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BP_LRADC_CTRL0_RSRVD2 27 +#define BM_LRADC_CTRL0_RSRVD2 0x38000000 +#define BF_LRADC_CTRL0_RSRVD2(v) \ + (((v) << 27) & BM_LRADC_CTRL0_RSRVD2) +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x04000000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BM_LRADC_CTRL0_BUTTON1_DETECT_ENABLE 0x02000000 +#define BV_LRADC_CTRL0_BUTTON1_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_BUTTON1_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_BUTTON0_DETECT_ENABLE 0x01000000 +#define BV_LRADC_CTRL0_BUTTON0_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_BUTTON0_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00800000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_SCREEN_TYPE 0x00400000 +#define BM_LRADC_CTRL0_YNLRSW 0x00200000 +#define BP_LRADC_CTRL0_YPLLSW 19 +#define BM_LRADC_CTRL0_YPLLSW 0x00180000 +#define BF_LRADC_CTRL0_YPLLSW(v) \ + (((v) << 19) & BM_LRADC_CTRL0_YPLLSW) +#define BP_LRADC_CTRL0_XNURSW 17 +#define BM_LRADC_CTRL0_XNURSW 0x00060000 +#define BF_LRADC_CTRL0_XNURSW(v) \ + (((v) << 17) & BM_LRADC_CTRL0_XNURSW) +#define BM_LRADC_CTRL0_XPULSW 0x00010000 +#define BP_LRADC_CTRL0_RSRVD1 8 +#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00 +#define BF_LRADC_CTRL0_RSRVD1(v) \ + (((v) << 8) & BM_LRADC_CTRL0_RSRVD1) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF +#define BF_LRADC_CTRL0_SCHEDULE(v) \ + (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE) + +#define HW_LRADC_CTRL1 (0x00000010) +#define HW_LRADC_CTRL1_SET (0x00000014) +#define HW_LRADC_CTRL1_CLR (0x00000018) +#define HW_LRADC_CTRL1_TOG (0x0000001c) + +#define BP_LRADC_CTRL1_RSRVD2 29 +#define BM_LRADC_CTRL1_RSRVD2 0xE0000000 +#define BF_LRADC_CTRL1_RSRVD2(v) \ + (((v) << 29) & BM_LRADC_CTRL1_RSRVD2) +#define BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN 0x10000000 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN 0x08000000 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN 0x04000000 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN 0x02000000 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BP_LRADC_CTRL1_RSRVD1 13 +#define BM_LRADC_CTRL1_RSRVD1 0x0000E000 +#define BF_LRADC_CTRL1_RSRVD1(v) \ + (((v) << 13) & BM_LRADC_CTRL1_RSRVD1) +#define BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ 0x00001000 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_BUTTON0_DETECT_IRQ 0x00000800 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ 0x00000400 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ 0x00000200 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 + +#define HW_LRADC_CTRL2 (0x00000020) +#define HW_LRADC_CTRL2_SET (0x00000024) +#define HW_LRADC_CTRL2_CLR (0x00000028) +#define HW_LRADC_CTRL2_TOG (0x0000002c) + +#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \ + (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO) +#define BP_LRADC_CTRL2_RSRVD3 16 +#define BM_LRADC_CTRL2_RSRVD3 0x00FF0000 +#define BF_LRADC_CTRL2_RSRVD3(v) \ + (((v) << 16) & BM_LRADC_CTRL2_RSRVD3) +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 +#define BP_LRADC_CTRL2_VTHSENSE 13 +#define BM_LRADC_CTRL2_VTHSENSE 0x00006000 +#define BF_LRADC_CTRL2_VTHSENSE(v) \ + (((v) << 13) & BM_LRADC_CTRL2_VTHSENSE) +#define BM_LRADC_CTRL2_DISABLE_MUXAMP_BYPASS 0x00001000 +#define BP_LRADC_CTRL2_RSRVD2 10 +#define BM_LRADC_CTRL2_RSRVD2 0x00000C00 +#define BF_LRADC_CTRL2_RSRVD2(v) \ + (((v) << 10) & BM_LRADC_CTRL2_RSRVD2) +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \ + (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1) +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \ + (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0) +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 + +#define HW_LRADC_CTRL3 (0x00000030) +#define HW_LRADC_CTRL3_SET (0x00000034) +#define HW_LRADC_CTRL3_CLR (0x00000038) +#define HW_LRADC_CTRL3_TOG (0x0000003c) + +#define BP_LRADC_CTRL3_RSRVD5 26 +#define BM_LRADC_CTRL3_RSRVD5 0xFC000000 +#define BF_LRADC_CTRL3_RSRVD5(v) \ + (((v) << 26) & BM_LRADC_CTRL3_RSRVD5) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x03000000 +#define BF_LRADC_CTRL3_DISCARD(v) \ + (((v) << 24) & BM_LRADC_CTRL3_DISCARD) +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BP_LRADC_CTRL3_RSRVD4 14 +#define BM_LRADC_CTRL3_RSRVD4 0x003FC000 +#define BF_LRADC_CTRL3_RSRVD4(v) \ + (((v) << 14) & BM_LRADC_CTRL3_RSRVD4) +#define BP_LRADC_CTRL3_RSRVD3 10 +#define BM_LRADC_CTRL3_RSRVD3 0x00003C00 +#define BF_LRADC_CTRL3_RSRVD3(v) \ + (((v) << 10) & BM_LRADC_CTRL3_RSRVD3) +#define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) \ + (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME) +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BP_LRADC_CTRL3_RSRVD2 6 +#define BM_LRADC_CTRL3_RSRVD2 0x000000C0 +#define BF_LRADC_CTRL3_RSRVD2(v) \ + (((v) << 6) & BM_LRADC_CTRL3_RSRVD2) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030 +#define BF_LRADC_CTRL3_HIGH_TIME(v) \ + (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME) +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BP_LRADC_CTRL3_RSRVD1 2 +#define BM_LRADC_CTRL3_RSRVD1 0x0000000C +#define BF_LRADC_CTRL3_RSRVD1(v) \ + (((v) << 2) & BM_LRADC_CTRL3_RSRVD1) +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 + +#define HW_LRADC_STATUS (0x00000040) +#define HW_LRADC_STATUS_SET (0x00000044) +#define HW_LRADC_STATUS_CLR (0x00000048) +#define HW_LRADC_STATUS_TOG (0x0000004c) + +#define BP_LRADC_STATUS_RSRVD3 29 +#define BM_LRADC_STATUS_RSRVD3 0xE0000000 +#define BF_LRADC_STATUS_RSRVD3(v) \ + (((v) << 29) & BM_LRADC_STATUS_RSRVD3) +#define BM_LRADC_STATUS_BUTTON1_PRESENT 0x10000000 +#define BM_LRADC_STATUS_BUTTON0_PRESENT 0x08000000 +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000 +#define BP_LRADC_STATUS_RSRVD2 3 +#define BM_LRADC_STATUS_RSRVD2 0x0000FFF8 +#define BF_LRADC_STATUS_RSRVD2(v) \ + (((v) << 3) & BM_LRADC_STATUS_RSRVD2) +#define BM_LRADC_STATUS_BUTTON1_DETECT_RAW 0x00000004 +#define BV_LRADC_STATUS_BUTTON1_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_BUTTON1_DETECT_RAW__HIT 0x1 +#define BM_LRADC_STATUS_BUTTON0_DETECT_RAW 0x00000002 +#define BV_LRADC_STATUS_BUTTON0_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_BUTTON0_DETECT_RAW__HIT 0x1 +#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 + +/* + * multi-register-define name HW_LRADC_CHn + * base 0x00000050 + * count 6 + * offset 0x10 + */ +#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10) +#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10) +#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10) +#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10) +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BM_LRADC_CHn_RSRVD2 0x40000000 +#define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES) +#define BP_LRADC_CHn_RSRVD1 18 +#define BM_LRADC_CHn_RSRVD1 0x00FC0000 +#define BF_LRADC_CHn_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CHn_RSRVD1) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x0003FFFF +#define BF_LRADC_CHn_VALUE(v) \ + (((v) << 0) & BM_LRADC_CHn_VALUE) + +#define HW_LRADC_CH6 (0x000000b0) +#define HW_LRADC_CH6_SET (0x000000b4) +#define HW_LRADC_CH6_CLR (0x000000b8) +#define HW_LRADC_CH6_TOG (0x000000bc) + +#define BM_LRADC_CH6_TOGGLE 0x80000000 +#define BM_LRADC_CH6_RSRVD2 0x40000000 +#define BM_LRADC_CH6_ACCUMULATE 0x20000000 +#define BP_LRADC_CH6_NUM_SAMPLES 24 +#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH6_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES) +#define BP_LRADC_CH6_RSRVD1 18 +#define BM_LRADC_CH6_RSRVD1 0x00FC0000 +#define BF_LRADC_CH6_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH6_RSRVD1) +#define BP_LRADC_CH6_VALUE 0 +#define BM_LRADC_CH6_VALUE 0x0003FFFF +#define BF_LRADC_CH6_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH6_VALUE) + +#define HW_LRADC_CH7 (0x000000c0) +#define HW_LRADC_CH7_SET (0x000000c4) +#define HW_LRADC_CH7_CLR (0x000000c8) +#define HW_LRADC_CH7_TOG (0x000000cc) + +#define BM_LRADC_CH7_TOGGLE 0x80000000 +#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000 +#define BM_LRADC_CH7_ACCUMULATE 0x20000000 +#define BP_LRADC_CH7_NUM_SAMPLES 24 +#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH7_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES) +#define BP_LRADC_CH7_RSRVD1 18 +#define BM_LRADC_CH7_RSRVD1 0x00FC0000 +#define BF_LRADC_CH7_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH7_RSRVD1) +#define BP_LRADC_CH7_VALUE 0 +#define BM_LRADC_CH7_VALUE 0x0003FFFF +#define BF_LRADC_CH7_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH7_VALUE) + +/* + * multi-register-define name HW_LRADC_DELAYn + * base 0x000000D0 + * count 4 + * offset 0x10 + */ +#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10) +#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10) +#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10) +#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10) +#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \ + (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS) +#define BP_LRADC_DELAYn_RSRVD2 21 +#define BM_LRADC_DELAYn_RSRVD2 0x00E00000 +#define BF_LRADC_DELAYn_RSRVD2(v) \ + (((v) << 21) & BM_LRADC_DELAYn_RSRVD2) +#define BM_LRADC_DELAYn_KICK 0x00100000 +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \ + (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) \ + (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x000007FF +#define BF_LRADC_DELAYn_DELAY(v) \ + (((v) << 0) & BM_LRADC_DELAYn_DELAY) + +#define HW_LRADC_DEBUG0 (0x00000110) +#define HW_LRADC_DEBUG0_SET (0x00000114) +#define HW_LRADC_DEBUG0_CLR (0x00000118) +#define HW_LRADC_DEBUG0_TOG (0x0000011c) + +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000 +#define BF_LRADC_DEBUG0_READONLY(v) \ + (((v) << 16) & BM_LRADC_DEBUG0_READONLY) +#define BP_LRADC_DEBUG0_RSRVD1 12 +#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000 +#define BF_LRADC_DEBUG0_RSRVD1(v) \ + (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0x00000FFF +#define BF_LRADC_DEBUG0_STATE(v) \ + (((v) << 0) & BM_LRADC_DEBUG0_STATE) + +#define HW_LRADC_DEBUG1 (0x00000120) +#define HW_LRADC_DEBUG1_SET (0x00000124) +#define HW_LRADC_DEBUG1_CLR (0x00000128) +#define HW_LRADC_DEBUG1_TOG (0x0000012c) + +#define BP_LRADC_DEBUG1_RSRVD3 24 +#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000 +#define BF_LRADC_DEBUG1_RSRVD3(v) \ + (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000 +#define BF_LRADC_DEBUG1_REQUEST(v) \ + (((v) << 16) & BM_LRADC_DEBUG1_REQUEST) +#define BP_LRADC_DEBUG1_RSRVD2 13 +#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000 +#define BF_LRADC_DEBUG1_RSRVD2(v) \ + (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \ + (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT) +#define BP_LRADC_DEBUG1_RSRVD1 3 +#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8 +#define BF_LRADC_DEBUG1_RSRVD1(v) \ + (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1) +#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE 0x00000001 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 + +#define HW_LRADC_CONVERSION (0x00000130) +#define HW_LRADC_CONVERSION_SET (0x00000134) +#define HW_LRADC_CONVERSION_CLR (0x00000138) +#define HW_LRADC_CONVERSION_TOG (0x0000013c) + +#define BP_LRADC_CONVERSION_RSRVD3 21 +#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000 +#define BF_LRADC_CONVERSION_RSRVD3(v) \ + (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3) +#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BP_LRADC_CONVERSION_RSRVD2 18 +#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000 +#define BF_LRADC_CONVERSION_RSRVD2(v) \ + (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \ + (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR) +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BP_LRADC_CONVERSION_RSRVD1 10 +#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00 +#define BF_LRADC_CONVERSION_RSRVD1(v) \ + (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \ + (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE) + +#define HW_LRADC_CTRL4 (0x00000140) +#define HW_LRADC_CTRL4_SET (0x00000144) +#define HW_LRADC_CTRL4_CLR (0x00000148) +#define HW_LRADC_CTRL4_TOG (0x0000014c) + +#define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 +#define BF_LRADC_CTRL4_LRADC7SELECT(v) \ + (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT) +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 +#define BF_LRADC_CTRL4_LRADC6SELECT(v) \ + (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT) +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000 +#define BF_LRADC_CTRL4_LRADC5SELECT(v) \ + (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT) +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000 +#define BF_LRADC_CTRL4_LRADC4SELECT(v) \ + (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT) +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000 +#define BF_LRADC_CTRL4_LRADC3SELECT(v) \ + (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT) +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00 +#define BF_LRADC_CTRL4_LRADC2SELECT(v) \ + (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT) +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0 +#define BF_LRADC_CTRL4_LRADC1SELECT(v) \ + (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT) +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F +#define BF_LRADC_CTRL4_LRADC0SELECT(v) \ + (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT) +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF + +#define HW_LRADC_THRESHOLD0 (0x00000150) +#define HW_LRADC_THRESHOLD0_SET (0x00000154) +#define HW_LRADC_THRESHOLD0_CLR (0x00000158) +#define HW_LRADC_THRESHOLD0_TOG (0x0000015c) + +#define BP_LRADC_THRESHOLD0_RSRVD1 25 +#define BM_LRADC_THRESHOLD0_RSRVD1 0xFE000000 +#define BF_LRADC_THRESHOLD0_RSRVD1(v) \ + (((v) << 25) & BM_LRADC_THRESHOLD0_RSRVD1) +#define BM_LRADC_THRESHOLD0_ENABLE 0x01000000 +#define BM_LRADC_THRESHOLD0_BATTCHRG_DISABLE 0x00800000 +#define BP_LRADC_THRESHOLD0_CHANNEL_SEL 20 +#define BM_LRADC_THRESHOLD0_CHANNEL_SEL 0x00700000 +#define BF_LRADC_THRESHOLD0_CHANNEL_SEL(v) \ + (((v) << 20) & BM_LRADC_THRESHOLD0_CHANNEL_SEL) +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL0 0x0 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL1 0x1 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL2 0x2 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL3 0x3 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL4 0x4 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL5 0x5 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL6 0x6 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL7 0x7 +#define BP_LRADC_THRESHOLD0_SETTING 18 +#define BM_LRADC_THRESHOLD0_SETTING 0x000C0000 +#define BF_LRADC_THRESHOLD0_SETTING(v) \ + (((v) << 18) & BM_LRADC_THRESHOLD0_SETTING) +#define BV_LRADC_THRESHOLD0_SETTING__NO_COMPARE 0x0 +#define BV_LRADC_THRESHOLD0_SETTING__DETECT_LOW 0x1 +#define BV_LRADC_THRESHOLD0_SETTING__DETECT_HIGH 0x2 +#define BV_LRADC_THRESHOLD0_SETTING__RESERVED 0x3 +#define BP_LRADC_THRESHOLD0_VALUE 0 +#define BM_LRADC_THRESHOLD0_VALUE 0x0003FFFF +#define BF_LRADC_THRESHOLD0_VALUE(v) \ + (((v) << 0) & BM_LRADC_THRESHOLD0_VALUE) + +#define HW_LRADC_THRESHOLD1 (0x00000160) +#define HW_LRADC_THRESHOLD1_SET (0x00000164) +#define HW_LRADC_THRESHOLD1_CLR (0x00000168) +#define HW_LRADC_THRESHOLD1_TOG (0x0000016c) + +#define BP_LRADC_THRESHOLD1_RSRVD1 25 +#define BM_LRADC_THRESHOLD1_RSRVD1 0xFE000000 +#define BF_LRADC_THRESHOLD1_RSRVD1(v) \ + (((v) << 25) & BM_LRADC_THRESHOLD1_RSRVD1) +#define BM_LRADC_THRESHOLD1_ENABLE 0x01000000 +#define BM_LRADC_THRESHOLD1_BATTCHRG_DISABLE 0x00800000 +#define BP_LRADC_THRESHOLD1_CHANNEL_SEL 20 +#define BM_LRADC_THRESHOLD1_CHANNEL_SEL 0x00700000 +#define BF_LRADC_THRESHOLD1_CHANNEL_SEL(v) \ + (((v) << 20) & BM_LRADC_THRESHOLD1_CHANNEL_SEL) +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL0 0x0 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL1 0x1 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL2 0x2 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL3 0x3 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL4 0x4 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL5 0x5 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL6 0x6 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL7 0x7 +#define BP_LRADC_THRESHOLD1_SETTING 18 +#define BM_LRADC_THRESHOLD1_SETTING 0x000C0000 +#define BF_LRADC_THRESHOLD1_SETTING(v) \ + (((v) << 18) & BM_LRADC_THRESHOLD1_SETTING) +#define BV_LRADC_THRESHOLD1_SETTING__NO_COMPARE 0x0 +#define BV_LRADC_THRESHOLD1_SETTING__DETECT_LOW 0x1 +#define BV_LRADC_THRESHOLD1_SETTING__DETECT_HIGH 0x2 +#define BV_LRADC_THRESHOLD1_SETTING__RESERVED 0x3 +#define BP_LRADC_THRESHOLD1_VALUE 0 +#define BM_LRADC_THRESHOLD1_VALUE 0x0003FFFF +#define BF_LRADC_THRESHOLD1_VALUE(v) \ + (((v) << 0) & BM_LRADC_THRESHOLD1_VALUE) + +#define HW_LRADC_VERSION (0x00000170) + +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xFF000000 +#define BF_LRADC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LRADC_VERSION_MAJOR) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0x00FF0000 +#define BF_LRADC_VERSION_MINOR(v) \ + (((v) << 16) & BM_LRADC_VERSION_MINOR) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0x0000FFFF +#define BF_LRADC_VERSION_STEP(v) \ + (((v) << 0) & BM_LRADC_VERSION_STEP) +#endif /* __ARCH_ARM___LRADC_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-ocotp.h b/arch/arm/mach-mx28/include/mach/regs-ocotp.h new file mode 100644 index 000000000000..7907250116ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ocotp.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BP_OCOTP_CUSTCAP_RSRVD1 3 +#define BM_OCOTP_CUSTCAP_RSRVD1 0xFFFFFFF8 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 3) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BM_OCOTP_LOCK_SRK 0x00008000 +#define BP_OCOTP_LOCK_UNALLOCATED 12 +#define BM_OCOTP_LOCK_UNALLOCATED 0x00007000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 12) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_ROMn + * base 0x000001A0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_ROMn(n) (0x000001a0 + (n) * 0x10) +#define BP_OCOTP_ROMn_BOOT_MODE 24 +#define BM_OCOTP_ROMn_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROMn_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROMn_BOOT_MODE) +#define BP_OCOTP_ROMn_SD_MMC_MODE 22 +#define BM_OCOTP_ROMn_SD_MMC_MODE 0x00C00000 +#define BF_OCOTP_ROMn_SD_MMC_MODE(v) \ + (((v) << 22) & BM_OCOTP_ROMn_SD_MMC_MODE) +#define BP_OCOTP_ROMn_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROMn_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROMn_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROMn_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROMn_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROMn_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROMn_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROMn_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROMn_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROMn_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROMn_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROMn_SD_BUS_WIDTH) +#define BP_OCOTP_ROMn_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROMn_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROMn_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROMn_SSP_SCK_INDEX) +#define BM_OCOTP_ROMn_EMMC_USE_DDR 0x00000080 +#define BM_OCOTP_ROMn_DISABLE_SPI_NOR_FAST_READ 0x00000040 +#define BM_OCOTP_ROMn_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROMn_ENABLE_UNENCRYPTED_BOOT 0x00000010 +#define BM_OCOTP_ROMn_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROMn_RSRVD2 0x00000004 +#define BM_OCOTP_ROMn_RSRVD1 0x00000002 +#define BM_OCOTP_ROMn_RSRVD0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x00000220 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x00000220 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x000002a0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-power.h b/arch/arm/mach-mx28/include/mach/regs-power.h new file mode 100644 index 000000000000..8f6a8eeefa4b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-power.h @@ -0,0 +1,683 @@ +/* + * Freescale POWER Register Definitions + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H + + +#include <mach/mx28.h> + +#define REGS_POWER_BASE IO_ADDRESS(POWER_PHYS_ADDR) +#define REGS_POWER_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 + +#define HW_POWER_CTRL (0x00000000) +#define HW_POWER_CTRL_SET (0x00000004) +#define HW_POWER_CTRL_CLR (0x00000008) +#define HW_POWER_CTRL_TOG (0x0000000c) + +#define BP_POWER_CTRL_RSRVD2 28 +#define BM_POWER_CTRL_RSRVD2 0xF0000000 +#define BF_POWER_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_POWER_CTRL_RSRVD2) +#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000 +#define BP_POWER_CTRL_RSRVD1 25 +#define BM_POWER_CTRL_RSRVD1 0x06000000 +#define BF_POWER_CTRL_RSRVD1(v) \ + (((v) << 25) & BM_POWER_CTRL_RSRVD1) +#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000 +#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000 +#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000 +#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000 +#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 +#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000 +#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000 +#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 +#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000 +#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000 +#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000 +#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000 +#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000 +#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800 +#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400 +#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200 +#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100 +#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080 +#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040 +#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020 +#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010 +#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008 +#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004 +#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002 +#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 + +#define HW_POWER_5VCTRL (0x00000010) +#define HW_POWER_5VCTRL_SET (0x00000014) +#define HW_POWER_5VCTRL_CLR (0x00000018) +#define HW_POWER_5VCTRL_TOG (0x0000001c) + +#define BP_POWER_5VCTRL_RSRVD6 30 +#define BM_POWER_5VCTRL_RSRVD6 0xC0000000 +#define BF_POWER_5VCTRL_RSRVD6(v) \ + (((v) << 30) & BM_POWER_5VCTRL_RSRVD6) +#define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28 +#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000 +#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) \ + (((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH) +#define BM_POWER_5VCTRL_RSRVD5 0x08000000 +#define BP_POWER_5VCTRL_HEADROOM_ADJ 24 +#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000 +#define BF_POWER_5VCTRL_HEADROOM_ADJ(v) \ + (((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ) +#define BP_POWER_5VCTRL_RSRVD4 22 +#define BM_POWER_5VCTRL_RSRVD4 0x00C00000 +#define BF_POWER_5VCTRL_RSRVD4(v) \ + (((v) << 22) & BM_POWER_5VCTRL_RSRVD4) +#define BP_POWER_5VCTRL_PWD_CHARGE_4P2 20 +#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00300000 +#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v) \ + (((v) << 20) & BM_POWER_5VCTRL_PWD_CHARGE_4P2) +#define BP_POWER_5VCTRL_RSRVD3 18 +#define BM_POWER_5VCTRL_RSRVD3 0x000C0000 +#define BF_POWER_5VCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_5VCTRL_RSRVD3) +#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12 +#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000 +#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) \ + (((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) +#define BM_POWER_5VCTRL_RSRVD2 0x00000800 +#define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 +#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700 +#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) \ + (((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH) +#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080 +#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 +#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020 +#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010 +#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008 +#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004 +#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002 +#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001 + +#define HW_POWER_MINPWR (0x00000020) +#define HW_POWER_MINPWR_SET (0x00000024) +#define HW_POWER_MINPWR_CLR (0x00000028) +#define HW_POWER_MINPWR_TOG (0x0000002c) + +#define BP_POWER_MINPWR_RSRVD1 15 +#define BM_POWER_MINPWR_RSRVD1 0xFFFF8000 +#define BF_POWER_MINPWR_RSRVD1(v) \ + (((v) << 15) & BM_POWER_MINPWR_RSRVD1) +#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000 +#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000 +#define BM_POWER_MINPWR_PWD_BO 0x00001000 +#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800 +#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400 +#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200 +#define BM_POWER_MINPWR_SELECT_OSC 0x00000100 +#define BM_POWER_MINPWR_VBG_OFF 0x00000080 +#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040 +#define BM_POWER_MINPWR_HALF_FETS 0x00000020 +#define BM_POWER_MINPWR_LESSANA_I 0x00000010 +#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008 +#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004 +#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002 +#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001 + +#define HW_POWER_CHARGE (0x00000030) +#define HW_POWER_CHARGE_SET (0x00000034) +#define HW_POWER_CHARGE_CLR (0x00000038) +#define HW_POWER_CHARGE_TOG (0x0000003c) + +#define BP_POWER_CHARGE_RSRVD6 27 +#define BM_POWER_CHARGE_RSRVD6 0xF8000000 +#define BF_POWER_CHARGE_RSRVD6(v) \ + (((v) << 27) & BM_POWER_CHARGE_RSRVD6) +#define BP_POWER_CHARGE_ADJ_VOLT 24 +#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000 +#define BF_POWER_CHARGE_ADJ_VOLT(v) \ + (((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT) +#define BM_POWER_CHARGE_RSRVD5 0x00800000 +#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000 +#define BM_POWER_CHARGE_RSRVD4 0x00200000 +#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000 +#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000 +#define BM_POWER_CHARGE_LIION_4P1 0x00040000 +#define BM_POWER_CHARGE_RSRVD3 0x00020000 +#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000 +#define BP_POWER_CHARGE_RSRVD2 14 +#define BM_POWER_CHARGE_RSRVD2 0x0000C000 +#define BF_POWER_CHARGE_RSRVD2(v) \ + (((v) << 14) & BM_POWER_CHARGE_RSRVD2) +#define BM_POWER_CHARGE_ENABLE_CHARGER_USB1 0x00002000 +#define BM_POWER_CHARGE_ENABLE_CHARGER_USB0 0x00001000 +#define BP_POWER_CHARGE_STOP_ILIMIT 8 +#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00 +#define BF_POWER_CHARGE_STOP_ILIMIT(v) \ + (((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT) +#define BP_POWER_CHARGE_RSRVD1 6 +#define BM_POWER_CHARGE_RSRVD1 0x000000C0 +#define BF_POWER_CHARGE_RSRVD1(v) \ + (((v) << 6) & BM_POWER_CHARGE_RSRVD1) +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F +#define BF_POWER_CHARGE_BATTCHRG_I(v) \ + (((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I) + +#define HW_POWER_VDDDCTRL (0x00000040) + +#define BP_POWER_VDDDCTRL_ADJTN 28 +#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000 +#define BF_POWER_VDDDCTRL_ADJTN(v) \ + (((v) << 28) & BM_POWER_VDDDCTRL_ADJTN) +#define BP_POWER_VDDDCTRL_RSRVD4 24 +#define BM_POWER_VDDDCTRL_RSRVD4 0x0F000000 +#define BF_POWER_VDDDCTRL_RSRVD4(v) \ + (((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4) +#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000 +#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000 +#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000 +#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000 +#define BP_POWER_VDDDCTRL_RSRVD3 18 +#define BM_POWER_VDDDCTRL_RSRVD3 0x000C0000 +#define BF_POWER_VDDDCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3) +#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 +#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000 +#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) \ + (((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD2 11 +#define BM_POWER_VDDDCTRL_RSRVD2 0x0000F800 +#define BF_POWER_VDDDCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2) +#define BP_POWER_VDDDCTRL_BO_OFFSET 8 +#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDDCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD1 5 +#define BM_POWER_VDDDCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDDCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1) +#define BP_POWER_VDDDCTRL_TRG 0 +#define BM_POWER_VDDDCTRL_TRG 0x0000001F +#define BF_POWER_VDDDCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDDCTRL_TRG) + +#define HW_POWER_VDDACTRL (0x00000050) + +#define BP_POWER_VDDACTRL_RSRVD4 20 +#define BM_POWER_VDDACTRL_RSRVD4 0xFFF00000 +#define BF_POWER_VDDACTRL_RSRVD4(v) \ + (((v) << 20) & BM_POWER_VDDACTRL_RSRVD4) +#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000 +#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000 +#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000 +#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDACTRL_RSRVD3 14 +#define BM_POWER_VDDACTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDACTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDACTRL_RSRVD3) +#define BP_POWER_VDDACTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET) +#define BM_POWER_VDDACTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDACTRL_BO_OFFSET 8 +#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDACTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET) +#define BP_POWER_VDDACTRL_RSRVD1 5 +#define BM_POWER_VDDACTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDACTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDACTRL_RSRVD1) +#define BP_POWER_VDDACTRL_TRG 0 +#define BM_POWER_VDDACTRL_TRG 0x0000001F +#define BF_POWER_VDDACTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDACTRL_TRG) + +#define HW_POWER_VDDIOCTRL (0x00000060) + +#define BP_POWER_VDDIOCTRL_RSRVD5 24 +#define BM_POWER_VDDIOCTRL_RSRVD5 0xFF000000 +#define BF_POWER_VDDIOCTRL_RSRVD5(v) \ + (((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5) +#define BP_POWER_VDDIOCTRL_ADJTN 20 +#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000 +#define BF_POWER_VDDIOCTRL_ADJTN(v) \ + (((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN) +#define BM_POWER_VDDIOCTRL_RSRVD4 0x00080000 +#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000 +#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000 +#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDIOCTRL_RSRVD3 14 +#define BM_POWER_VDDIOCTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDIOCTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3) +#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET) +#define BM_POWER_VDDIOCTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDIOCTRL_BO_OFFSET 8 +#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET) +#define BP_POWER_VDDIOCTRL_RSRVD1 5 +#define BM_POWER_VDDIOCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDIOCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1) +#define BP_POWER_VDDIOCTRL_TRG 0 +#define BM_POWER_VDDIOCTRL_TRG 0x0000001F +#define BF_POWER_VDDIOCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDIOCTRL_TRG) + +#define HW_POWER_VDDMEMCTRL (0x00000070) + +#define BP_POWER_VDDMEMCTRL_RSRVD2 11 +#define BM_POWER_VDDMEMCTRL_RSRVD2 0xFFFFF800 +#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2) +#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400 +#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200 +#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100 +#define BP_POWER_VDDMEMCTRL_BO_OFFSET 5 +#define BM_POWER_VDDMEMCTRL_BO_OFFSET 0x000000E0 +#define BF_POWER_VDDMEMCTRL_BO_OFFSET(v) \ + (((v) << 5) & BM_POWER_VDDMEMCTRL_BO_OFFSET) +#define BP_POWER_VDDMEMCTRL_TRG 0 +#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F +#define BF_POWER_VDDMEMCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDMEMCTRL_TRG) + +#define HW_POWER_DCDC4P2 (0x00000080) + +#define BP_POWER_DCDC4P2_DROPOUT_CTRL 28 +#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000 +#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \ + (((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL) +#define BP_POWER_DCDC4P2_RSRVD5 26 +#define BM_POWER_DCDC4P2_RSRVD5 0x0C000000 +#define BF_POWER_DCDC4P2_RSRVD5(v) \ + (((v) << 26) & BM_POWER_DCDC4P2_RSRVD5) +#define BP_POWER_DCDC4P2_ISTEAL_THRESH 24 +#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000 +#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) \ + (((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH) +#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000 +#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000 +#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000 +#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000 +#define BM_POWER_DCDC4P2_RSRVD3 0x00080000 +#define BP_POWER_DCDC4P2_TRG 16 +#define BM_POWER_DCDC4P2_TRG 0x00070000 +#define BF_POWER_DCDC4P2_TRG(v) \ + (((v) << 16) & BM_POWER_DCDC4P2_TRG) +#define BP_POWER_DCDC4P2_RSRVD2 13 +#define BM_POWER_DCDC4P2_RSRVD2 0x0000E000 +#define BF_POWER_DCDC4P2_RSRVD2(v) \ + (((v) << 13) & BM_POWER_DCDC4P2_RSRVD2) +#define BP_POWER_DCDC4P2_BO 8 +#define BM_POWER_DCDC4P2_BO 0x00001F00 +#define BF_POWER_DCDC4P2_BO(v) \ + (((v) << 8) & BM_POWER_DCDC4P2_BO) +#define BP_POWER_DCDC4P2_RSRVD1 5 +#define BM_POWER_DCDC4P2_RSRVD1 0x000000E0 +#define BF_POWER_DCDC4P2_RSRVD1(v) \ + (((v) << 5) & BM_POWER_DCDC4P2_RSRVD1) +#define BP_POWER_DCDC4P2_CMPTRIP 0 +#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F +#define BF_POWER_DCDC4P2_CMPTRIP(v) \ + (((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP) + +#define HW_POWER_MISC (0x00000090) + +#define BP_POWER_MISC_RSRVD2 7 +#define BM_POWER_MISC_RSRVD2 0xFFFFFF80 +#define BF_POWER_MISC_RSRVD2(v) \ + (((v) << 7) & BM_POWER_MISC_RSRVD2) +#define BP_POWER_MISC_FREQSEL 4 +#define BM_POWER_MISC_FREQSEL 0x00000070 +#define BF_POWER_MISC_FREQSEL(v) \ + (((v) << 4) & BM_POWER_MISC_FREQSEL) +#define BM_POWER_MISC_DISABLEFET_BO_LOGIC 0x00000008 +#define BM_POWER_MISC_DELAY_TIMING 0x00000004 +#define BM_POWER_MISC_TEST 0x00000002 +#define BM_POWER_MISC_SEL_PLLCLK 0x00000001 + +#define HW_POWER_DCLIMITS (0x000000a0) + +#define BP_POWER_DCLIMITS_RSRVD3 16 +#define BM_POWER_DCLIMITS_RSRVD3 0xFFFF0000 +#define BF_POWER_DCLIMITS_RSRVD3(v) \ + (((v) << 16) & BM_POWER_DCLIMITS_RSRVD3) +#define BM_POWER_DCLIMITS_RSRVD2 0x00008000 +#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 +#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00 +#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) \ + (((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK) +#define BM_POWER_DCLIMITS_RSRVD1 0x00000080 +#define BP_POWER_DCLIMITS_NEGLIMIT 0 +#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F +#define BF_POWER_DCLIMITS_NEGLIMIT(v) \ + (((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT) + +#define HW_POWER_LOOPCTRL (0x000000b0) +#define HW_POWER_LOOPCTRL_SET (0x000000b4) +#define HW_POWER_LOOPCTRL_CLR (0x000000b8) +#define HW_POWER_LOOPCTRL_TOG (0x000000bc) + +#define BP_POWER_LOOPCTRL_RSRVD3 21 +#define BM_POWER_LOOPCTRL_RSRVD3 0xFFE00000 +#define BF_POWER_LOOPCTRL_RSRVD3(v) \ + (((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3) +#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000 +#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000 +#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000 +#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000 +#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000 +#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000 +#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000 +#define BP_POWER_LOOPCTRL_EN_RCSCALE 12 +#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000 +#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) \ + (((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE) +#define BM_POWER_LOOPCTRL_RSRVD2 0x00000800 +#define BP_POWER_LOOPCTRL_DC_FF 8 +#define BM_POWER_LOOPCTRL_DC_FF 0x00000700 +#define BF_POWER_LOOPCTRL_DC_FF(v) \ + (((v) << 8) & BM_POWER_LOOPCTRL_DC_FF) +#define BP_POWER_LOOPCTRL_DC_R 4 +#define BM_POWER_LOOPCTRL_DC_R 0x000000F0 +#define BF_POWER_LOOPCTRL_DC_R(v) \ + (((v) << 4) & BM_POWER_LOOPCTRL_DC_R) +#define BP_POWER_LOOPCTRL_RSRVD1 2 +#define BM_POWER_LOOPCTRL_RSRVD1 0x0000000C +#define BF_POWER_LOOPCTRL_RSRVD1(v) \ + (((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1) +#define BP_POWER_LOOPCTRL_DC_C 0 +#define BM_POWER_LOOPCTRL_DC_C 0x00000003 +#define BF_POWER_LOOPCTRL_DC_C(v) \ + (((v) << 0) & BM_POWER_LOOPCTRL_DC_C) + +#define HW_POWER_STS (0x000000c0) + +#define BP_POWER_STS_RSRVD3 30 +#define BM_POWER_STS_RSRVD3 0xC0000000 +#define BF_POWER_STS_RSRVD3(v) \ + (((v) << 30) & BM_POWER_STS_RSRVD3) +#define BP_POWER_STS_PWRUP_SOURCE 24 +#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000 +#define BF_POWER_STS_PWRUP_SOURCE(v) \ + (((v) << 24) & BM_POWER_STS_PWRUP_SOURCE) +#define BP_POWER_STS_RSRVD2 22 +#define BM_POWER_STS_RSRVD2 0x00C00000 +#define BF_POWER_STS_RSRVD2(v) \ + (((v) << 22) & BM_POWER_STS_RSRVD2) +#define BP_POWER_STS_PSWITCH 20 +#define BM_POWER_STS_PSWITCH 0x00300000 +#define BF_POWER_STS_PSWITCH(v) \ + (((v) << 20) & BM_POWER_STS_PSWITCH) +#define BM_POWER_STS_THERMAL_WARNING 0x00080000 +#define BM_POWER_STS_VDDMEM_BO 0x00040000 +#define BM_POWER_STS_AVALID0_STATUS 0x00020000 +#define BM_POWER_STS_BVALID0_STATUS 0x00010000 +#define BM_POWER_STS_VBUSVALID0_STATUS 0x00008000 +#define BM_POWER_STS_SESSEND0_STATUS 0x00004000 +#define BM_POWER_STS_BATT_BO 0x00002000 +#define BM_POWER_STS_VDD5V_FAULT 0x00001000 +#define BM_POWER_STS_CHRGSTS 0x00000800 +#define BM_POWER_STS_DCDC_4P2_BO 0x00000400 +#define BM_POWER_STS_DC_OK 0x00000200 +#define BM_POWER_STS_VDDIO_BO 0x00000100 +#define BM_POWER_STS_VDDA_BO 0x00000080 +#define BM_POWER_STS_VDDD_BO 0x00000040 +#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020 +#define BM_POWER_STS_VDD5V_DROOP 0x00000010 +#define BM_POWER_STS_AVALID0 0x00000008 +#define BM_POWER_STS_BVALID0 0x00000004 +#define BM_POWER_STS_VBUSVALID0 0x00000002 +#define BM_POWER_STS_SESSEND0 0x00000001 + +#define HW_POWER_SPEED (0x000000d0) +#define HW_POWER_SPEED_SET (0x000000d4) +#define HW_POWER_SPEED_CLR (0x000000d8) +#define HW_POWER_SPEED_TOG (0x000000dc) + +#define BP_POWER_SPEED_RSRVD1 24 +#define BM_POWER_SPEED_RSRVD1 0xFF000000 +#define BF_POWER_SPEED_RSRVD1(v) \ + (((v) << 24) & BM_POWER_SPEED_RSRVD1) +#define BP_POWER_SPEED_STATUS 8 +#define BM_POWER_SPEED_STATUS 0x00FFFF00 +#define BF_POWER_SPEED_STATUS(v) \ + (((v) << 8) & BM_POWER_SPEED_STATUS) +#define BP_POWER_SPEED_STATUS_SEL 6 +#define BM_POWER_SPEED_STATUS_SEL 0x000000C0 +#define BF_POWER_SPEED_STATUS_SEL(v) \ + (((v) << 6) & BM_POWER_SPEED_STATUS_SEL) +#define BV_POWER_SPEED_STATUS_SEL__DCDC_STAT 0x0 +#define BV_POWER_SPEED_STATUS_SEL__CORE_STAT 0x1 +#define BV_POWER_SPEED_STATUS_SEL__ARM_STAT 0x2 +#define BP_POWER_SPEED_RSRVD0 2 +#define BM_POWER_SPEED_RSRVD0 0x0000003C +#define BF_POWER_SPEED_RSRVD0(v) \ + (((v) << 2) & BM_POWER_SPEED_RSRVD0) +#define BP_POWER_SPEED_CTRL 0 +#define BM_POWER_SPEED_CTRL 0x00000003 +#define BF_POWER_SPEED_CTRL(v) \ + (((v) << 0) & BM_POWER_SPEED_CTRL) + +#define HW_POWER_BATTMONITOR (0x000000e0) + +#define BP_POWER_BATTMONITOR_RSRVD3 26 +#define BM_POWER_BATTMONITOR_RSRVD3 0xFC000000 +#define BF_POWER_BATTMONITOR_RSRVD3(v) \ + (((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3) +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000 +#define BF_POWER_BATTMONITOR_BATT_VAL(v) \ + (((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL) +#define BP_POWER_BATTMONITOR_RSRVD2 12 +#define BM_POWER_BATTMONITOR_RSRVD2 0x0000F000 +#define BF_POWER_BATTMONITOR_RSRVD2(v) \ + (((v) << 12) & BM_POWER_BATTMONITOR_RSRVD2) +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_ENABLE 0x00000800 +#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400 +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200 +#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100 +#define BP_POWER_BATTMONITOR_RSRVD1 5 +#define BM_POWER_BATTMONITOR_RSRVD1 0x000000E0 +#define BF_POWER_BATTMONITOR_RSRVD1(v) \ + (((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1) +#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 +#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F +#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) \ + (((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL) + +#define HW_POWER_RESET (0x00000100) +#define HW_POWER_RESET_SET (0x00000104) +#define HW_POWER_RESET_CLR (0x00000108) +#define HW_POWER_RESET_TOG (0x0000010c) + +#define BP_POWER_RESET_UNLOCK 16 +#define BM_POWER_RESET_UNLOCK 0xFFFF0000 +#define BF_POWER_RESET_UNLOCK(v) \ + (((v) << 16) & BM_POWER_RESET_UNLOCK) +#define BV_POWER_RESET_UNLOCK__KEY 0x3E77 +#define BP_POWER_RESET_RSRVD1 3 +#define BM_POWER_RESET_RSRVD1 0x0000FFF8 +#define BF_POWER_RESET_RSRVD1(v) \ + (((v) << 3) & BM_POWER_RESET_RSRVD1) +#define BM_POWER_RESET_FASTFALLPSWITCH_OFF 0x00000004 +#define BM_POWER_RESET_PWD_OFF 0x00000002 +#define BM_POWER_RESET_PWD 0x00000001 + +#define HW_POWER_DEBUG (0x00000110) +#define HW_POWER_DEBUG_SET (0x00000114) +#define HW_POWER_DEBUG_CLR (0x00000118) +#define HW_POWER_DEBUG_TOG (0x0000011c) + +#define BP_POWER_DEBUG_RSRVD0 4 +#define BM_POWER_DEBUG_RSRVD0 0xFFFFFFF0 +#define BF_POWER_DEBUG_RSRVD0(v) \ + (((v) << 4) & BM_POWER_DEBUG_RSRVD0) +#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001 + +#define HW_POWER_THERMAL (0x00000120) +#define HW_POWER_THERMAL_SET (0x00000124) +#define HW_POWER_THERMAL_CLR (0x00000128) +#define HW_POWER_THERMAL_TOG (0x0000012c) + +#define BP_POWER_THERMAL_RSRVD0 9 +#define BM_POWER_THERMAL_RSRVD0 0xFFFFFE00 +#define BF_POWER_THERMAL_RSRVD0(v) \ + (((v) << 9) & BM_POWER_THERMAL_RSRVD0) +#define BM_POWER_THERMAL_TEST 0x00000100 +#define BM_POWER_THERMAL_PWD 0x00000080 +#define BM_POWER_THERMAL_LOW_POWER 0x00000040 +#define BP_POWER_THERMAL_OFFSET_ADJ 4 +#define BM_POWER_THERMAL_OFFSET_ADJ 0x00000030 +#define BF_POWER_THERMAL_OFFSET_ADJ(v) \ + (((v) << 4) & BM_POWER_THERMAL_OFFSET_ADJ) +#define BM_POWER_THERMAL_OFFSET_ADJ_ENABLE 0x00000008 +#define BP_POWER_THERMAL_TEMP_THRESHOLD 0 +#define BM_POWER_THERMAL_TEMP_THRESHOLD 0x00000007 +#define BF_POWER_THERMAL_TEMP_THRESHOLD(v) \ + (((v) << 0) & BM_POWER_THERMAL_TEMP_THRESHOLD) + +#define HW_POWER_USB1CTRL (0x00000130) +#define HW_POWER_USB1CTRL_SET (0x00000134) +#define HW_POWER_USB1CTRL_CLR (0x00000138) +#define HW_POWER_USB1CTRL_TOG (0x0000013c) + +#define BP_POWER_USB1CTRL_RSRVD0 4 +#define BM_POWER_USB1CTRL_RSRVD0 0xFFFFFFF0 +#define BF_POWER_USB1CTRL_RSRVD0(v) \ + (((v) << 4) & BM_POWER_USB1CTRL_RSRVD0) +#define BM_POWER_USB1CTRL_AVALID1 0x00000008 +#define BM_POWER_USB1CTRL_BVALID1 0x00000004 +#define BM_POWER_USB1CTRL_VBUSVALID1 0x00000002 +#define BM_POWER_USB1CTRL_SESSEND1 0x00000001 + +#define HW_POWER_SPECIAL (0x00000140) +#define HW_POWER_SPECIAL_SET (0x00000144) +#define HW_POWER_SPECIAL_CLR (0x00000148) +#define HW_POWER_SPECIAL_TOG (0x0000014c) + +#define BP_POWER_SPECIAL_TEST 0 +#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF +#define BF_POWER_SPECIAL_TEST(v) (v) + +#define HW_POWER_VERSION (0x00000150) + +#define BP_POWER_VERSION_MAJOR 24 +#define BM_POWER_VERSION_MAJOR 0xFF000000 +#define BF_POWER_VERSION_MAJOR(v) \ + (((v) << 24) & BM_POWER_VERSION_MAJOR) +#define BP_POWER_VERSION_MINOR 16 +#define BM_POWER_VERSION_MINOR 0x00FF0000 +#define BF_POWER_VERSION_MINOR(v) \ + (((v) << 16) & BM_POWER_VERSION_MINOR) +#define BP_POWER_VERSION_STEP 0 +#define BM_POWER_VERSION_STEP 0x0000FFFF +#define BF_POWER_VERSION_STEP(v) \ + (((v) << 0) & BM_POWER_VERSION_STEP) + +#define HW_POWER_ANACLKCTRL (0x00000160) +#define HW_POWER_ANACLKCTRL_SET (0x00000164) +#define HW_POWER_ANACLKCTRL_CLR (0x00000168) +#define HW_POWER_ANACLKCTRL_TOG (0x0000016c) + +#define BM_POWER_ANACLKCTRL_CKGATE_O 0x80000000 +#define BP_POWER_ANACLKCTRL_OUTDIV 28 +#define BM_POWER_ANACLKCTRL_OUTDIV 0x70000000 +#define BF_POWER_ANACLKCTRL_OUTDIV(v) \ + (((v) << 28) & BM_POWER_ANACLKCTRL_OUTDIV) +#define BM_POWER_ANACLKCTRL_INVERT_OUTCLK 0x08000000 +#define BM_POWER_ANACLKCTRL_CKGATE_I 0x04000000 +#define BP_POWER_ANACLKCTRL_RSRVD4 11 +#define BM_POWER_ANACLKCTRL_RSRVD4 0x03FFF800 +#define BF_POWER_ANACLKCTRL_RSRVD4(v) \ + (((v) << 11) & BM_POWER_ANACLKCTRL_RSRVD4) +#define BM_POWER_ANACLKCTRL_DITHER_OFF 0x00000400 +#define BM_POWER_ANACLKCTRL_SLOW_DITHER 0x00000200 +#define BM_POWER_ANACLKCTRL_INVERT_INCLK 0x00000100 +#define BP_POWER_ANACLKCTRL_RSRVD3 6 +#define BM_POWER_ANACLKCTRL_RSRVD3 0x000000C0 +#define BF_POWER_ANACLKCTRL_RSRVD3(v) \ + (((v) << 6) & BM_POWER_ANACLKCTRL_RSRVD3) +#define BP_POWER_ANACLKCTRL_INCLK_SHIFT 4 +#define BM_POWER_ANACLKCTRL_INCLK_SHIFT 0x00000030 +#define BF_POWER_ANACLKCTRL_INCLK_SHIFT(v) \ + (((v) << 4) & BM_POWER_ANACLKCTRL_INCLK_SHIFT) +#define BM_POWER_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_POWER_ANACLKCTRL_INDIV 0 +#define BM_POWER_ANACLKCTRL_INDIV 0x00000007 +#define BF_POWER_ANACLKCTRL_INDIV(v) \ + (((v) << 0) & BM_POWER_ANACLKCTRL_INDIV) + +#define HW_POWER_REFCTRL (0x00000170) +#define HW_POWER_REFCTRL_SET (0x00000174) +#define HW_POWER_REFCTRL_CLR (0x00000178) +#define HW_POWER_REFCTRL_TOG (0x0000017c) + +#define BP_POWER_REFCTRL_RSRVD5 27 +#define BM_POWER_REFCTRL_RSRVD5 0xF8000000 +#define BF_POWER_REFCTRL_RSRVD5(v) \ + (((v) << 27) & BM_POWER_REFCTRL_RSRVD5) +#define BM_POWER_REFCTRL_FASTSETTLING 0x04000000 +#define BM_POWER_REFCTRL_RAISE_REF 0x02000000 +#define BM_POWER_REFCTRL_XTAL_BGR_BIAS 0x01000000 +#define BM_POWER_REFCTRL_RSRVD4 0x00800000 +#define BP_POWER_REFCTRL_VBG_ADJ 20 +#define BM_POWER_REFCTRL_VBG_ADJ 0x00700000 +#define BF_POWER_REFCTRL_VBG_ADJ(v) \ + (((v) << 20) & BM_POWER_REFCTRL_VBG_ADJ) +#define BM_POWER_REFCTRL_LOW_PWR 0x00080000 +#define BM_POWER_REFCTRL_RSRVD3 0x00040000 +#define BP_POWER_REFCTRL_BIAS_CTRL 16 +#define BM_POWER_REFCTRL_BIAS_CTRL 0x00030000 +#define BF_POWER_REFCTRL_BIAS_CTRL(v) \ + (((v) << 16) & BM_POWER_REFCTRL_BIAS_CTRL) +#define BM_POWER_REFCTRL_RSRVD2 0x00008000 +#define BM_POWER_REFCTRL_VDDXTAL_TO_VDDD 0x00004000 +#define BM_POWER_REFCTRL_ADJ_ANA 0x00002000 +#define BM_POWER_REFCTRL_ADJ_VAG 0x00001000 +#define BP_POWER_REFCTRL_ANA_REFVAL 8 +#define BM_POWER_REFCTRL_ANA_REFVAL 0x00000F00 +#define BF_POWER_REFCTRL_ANA_REFVAL(v) \ + (((v) << 8) & BM_POWER_REFCTRL_ANA_REFVAL) +#define BP_POWER_REFCTRL_VAG_VAL 4 +#define BM_POWER_REFCTRL_VAG_VAL 0x000000F0 +#define BF_POWER_REFCTRL_VAG_VAL(v) \ + (((v) << 4) & BM_POWER_REFCTRL_VAG_VAL) +#define BP_POWER_REFCTRL_RSRVD1 0 +#define BM_POWER_REFCTRL_RSRVD1 0x0000000F +#define BF_POWER_REFCTRL_RSRVD1(v) \ + (((v) << 0) & BM_POWER_REFCTRL_RSRVD1) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-pwm.h b/arch/arm/mach-mx28/include/mach/regs-pwm.h new file mode 100644 index 000000000000..ac0ebfbb7cca --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-pwm.h @@ -0,0 +1,147 @@ +/* + * Freescale PWM Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PWM_H +#define __ARCH_ARM___PWM_H + +#include <mach/mx28.h> + +#define REGS_PWM_BASE IO_ADDRESS(PWM_PHYS_ADDR) +#define REGS_PWM_PHYS (0x80064000) +#define REGS_PWM_SIZE 0x00002000 + +#define HW_PWM_CTRL (0x00000000) +#define HW_PWM_CTRL_SET (0x00000004) +#define HW_PWM_CTRL_CLR (0x00000008) +#define HW_PWM_CTRL_TOG (0x0000000c) + +#define BM_PWM_CTRL_SFTRST 0x80000000 +#define BM_PWM_CTRL_CLKGATE 0x40000000 +#define BM_PWM_CTRL_PWM7_PRESENT 0x20000000 +#define BM_PWM_CTRL_PWM6_PRESENT 0x10000000 +#define BM_PWM_CTRL_PWM5_PRESENT 0x08000000 +#define BM_PWM_CTRL_PWM4_PRESENT 0x04000000 +#define BM_PWM_CTRL_PWM3_PRESENT 0x02000000 +#define BM_PWM_CTRL_PWM2_PRESENT 0x01000000 +#define BM_PWM_CTRL_PWM1_PRESENT 0x00800000 +#define BM_PWM_CTRL_PWM0_PRESENT 0x00400000 +#define BP_PWM_CTRL_RSRVD1 10 +#define BM_PWM_CTRL_RSRVD1 0x003FFC00 +#define BF_PWM_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_PWM_CTRL_RSRVD1) +#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000200 +#define BM_PWM_CTRL_RSRVD2 0x00000100 +#define BM_PWM_CTRL_PWM7_ENABLE 0x00000080 +#define BM_PWM_CTRL_PWM6_ENABLE 0x00000040 +#define BM_PWM_CTRL_PWM5_ENABLE 0x00000020 +#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010 +#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008 +#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 +#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002 +#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PWM_ACTIVEn + * base 0x00000010 + * count 8 + * offset 0x20 + */ +#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20) +#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20) +#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20) +#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20) +#define BP_PWM_ACTIVEn_INACTIVE 16 +#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 +#define BF_PWM_ACTIVEn_INACTIVE(v) \ + (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE) +#define BP_PWM_ACTIVEn_ACTIVE 0 +#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF +#define BF_PWM_ACTIVEn_ACTIVE(v) \ + (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE) + +/* + * multi-register-define name HW_PWM_PERIODn + * base 0x00000020 + * count 8 + * offset 0x20 + */ +#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20) +#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_PWM_PERIODn_RSRVD2 27 +#define BM_PWM_PERIODn_RSRVD2 0xF8000000 +#define BF_PWM_PERIODn_RSRVD2(v) \ + (((v) << 27) & BM_PWM_PERIODn_RSRVD2) +#define BM_PWM_PERIODn_HSADC_OUT 0x04000000 +#define BM_PWM_PERIODn_HSADC_CLK_SEL 0x02000000 +#define BM_PWM_PERIODn_MATT_SEL 0x01000000 +#define BM_PWM_PERIODn_MATT 0x00800000 +#define BP_PWM_PERIODn_CDIV 20 +#define BM_PWM_PERIODn_CDIV 0x00700000 +#define BF_PWM_PERIODn_CDIV(v) \ + (((v) << 20) & BM_PWM_PERIODn_CDIV) +#define BV_PWM_PERIODn_CDIV__DIV_1 0x0 +#define BV_PWM_PERIODn_CDIV__DIV_2 0x1 +#define BV_PWM_PERIODn_CDIV__DIV_4 0x2 +#define BV_PWM_PERIODn_CDIV__DIV_8 0x3 +#define BV_PWM_PERIODn_CDIV__DIV_16 0x4 +#define BV_PWM_PERIODn_CDIV__DIV_64 0x5 +#define BV_PWM_PERIODn_CDIV__DIV_256 0x6 +#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 +#define BP_PWM_PERIODn_INACTIVE_STATE 18 +#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 +#define BF_PWM_PERIODn_INACTIVE_STATE(v) \ + (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE) +#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_ACTIVE_STATE 16 +#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 +#define BF_PWM_PERIODn_ACTIVE_STATE(v) \ + (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE) +#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_PERIOD 0 +#define BM_PWM_PERIODn_PERIOD 0x0000FFFF +#define BF_PWM_PERIODn_PERIOD(v) \ + (((v) << 0) & BM_PWM_PERIODn_PERIOD) + +#define HW_PWM_VERSION (0x00000110) + +#define BP_PWM_VERSION_MAJOR 24 +#define BM_PWM_VERSION_MAJOR 0xFF000000 +#define BF_PWM_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PWM_VERSION_MAJOR) +#define BP_PWM_VERSION_MINOR 16 +#define BM_PWM_VERSION_MINOR 0x00FF0000 +#define BF_PWM_VERSION_MINOR(v) \ + (((v) << 16) & BM_PWM_VERSION_MINOR) +#define BP_PWM_VERSION_STEP 0 +#define BM_PWM_VERSION_STEP 0x0000FFFF +#define BF_PWM_VERSION_STEP(v) \ + (((v) << 0) & BM_PWM_VERSION_STEP) +#endif /* __ARCH_ARM___PWM_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-pxp.h b/arch/arm/mach-mx28/include/mach/regs-pxp.h new file mode 100644 index 000000000000..2feb8f8db649 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-pxp.h @@ -0,0 +1,518 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BP_PXP_CTRL_RSVD2 28 +#define BM_PXP_CTRL_RSVD2 0x30000000 +#define BF_PXP_CTRL_RSVD2(v) \ + (((v) << 28) & BM_PXP_CTRL_RSVD2) +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 +#define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_S0_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_S0_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_S0_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_S0_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTBUF_FORMAT 4 +#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTBUF_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT) +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444 0x7 +#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUTBUF (0x00000020) + +#define BP_PXP_OUTBUF_ADDR 0 +#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF_ADDR(v) (v) + +#define HW_PXP_OUTBUF2 (0x00000030) + +#define BP_PXP_OUTBUF2_ADDR 0 +#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF2_ADDR(v) (v) + +#define HW_PXP_OUTSIZE (0x00000040) + +#define BP_PXP_OUTSIZE_ALPHA 24 +#define BM_PXP_OUTSIZE_ALPHA 0xFF000000 +#define BF_PXP_OUTSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUTSIZE_ALPHA) +#define BP_PXP_OUTSIZE_WIDTH 12 +#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000 +#define BF_PXP_OUTSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_OUTSIZE_WIDTH) +#define BP_PXP_OUTSIZE_HEIGHT 0 +#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF +#define BF_PXP_OUTSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OUTSIZE_HEIGHT) + +#define HW_PXP_S0BUF (0x00000050) + +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) + +#define HW_PXP_S0UBUF (0x00000060) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) + +#define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) + +#define HW_PXP_S0BACKGROUND (0x00000090) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) + +#define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) + +#define HW_PXP_S0SCALE (0x000000b0) + +#define BM_PXP_S0SCALE_RSVD2 0x80000000 +#define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BM_PXP_S0SCALE_RSVD1 0x00008000 +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00007FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) + +#define HW_PXP_S0OFFSET (0x000000c0) + +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) + +#define HW_PXP_CSCCOEFF0 (0x000000d0) + +#define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000 +#define BP_PXP_CSCCOEFF0_RSVD1 29 +#define BM_PXP_CSCCOEFF0_RSVD1 0x60000000 +#define BF_PXP_CSCCOEFF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSCCOEFF0_RSVD1) +#define BP_PXP_CSCCOEFF0_C0 18 +#define BM_PXP_CSCCOEFF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEFF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEFF0_C0) +#define BP_PXP_CSCCOEFF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEFF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEFF0_UV_OFFSET) +#define BP_PXP_CSCCOEFF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEFF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF0_Y_OFFSET) + +#define HW_PXP_CSCCOEFF1 (0x000000e0) + +#define BP_PXP_CSCCOEFF1_RSVD1 27 +#define BM_PXP_CSCCOEFF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF1_RSVD1) +#define BP_PXP_CSCCOEFF1_C1 16 +#define BM_PXP_CSCCOEFF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF1_C1) +#define BP_PXP_CSCCOEFF1_RSVD0 11 +#define BM_PXP_CSCCOEFF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF1_RSVD0) +#define BP_PXP_CSCCOEFF1_C4 0 +#define BM_PXP_CSCCOEFF1_C4 0x000007FF +#define BF_PXP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF1_C4) + +#define HW_PXP_CSCCOEFF2 (0x000000f0) + +#define BP_PXP_CSCCOEFF2_RSVD1 27 +#define BM_PXP_CSCCOEFF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF2_RSVD1) +#define BP_PXP_CSCCOEFF2_C2 16 +#define BM_PXP_CSCCOEFF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF2_C2) +#define BP_PXP_CSCCOEFF2_RSVD0 11 +#define BM_PXP_CSCCOEFF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF2_RSVD0) +#define BP_PXP_CSCCOEFF2_C3 0 +#define BM_PXP_CSCCOEFF2_C3 0x000007FF +#define BF_PXP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF2_C3) + +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) + +#define BP_PXP_DEBUGCTRL_RSVD 9 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFE00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 9) & BM_PXP_DEBUGCTRL_RSVD) +#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x00000100 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__TLBCOUNT 0xF0 +#define BV_PXP_DEBUGCTRL_SELECT__TLBHIT 0xF1 +#define BV_PXP_DEBUGCTRL_SELECT__TLBMISS 0xF2 +#define BV_PXP_DEBUGCTRL_SELECT__TLBLAT 0xF3 +#define BV_PXP_DEBUGCTRL_SELECT__TLBSTATE 0xF8 + +#define HW_PXP_DEBUG (0x000001e0) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB +#define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-rtc.h b/arch/arm/mach-mx28/include/mach/regs-rtc.h new file mode 100644 index 000000000000..bdb3ac23a2a0 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-rtc.h @@ -0,0 +1,226 @@ +/* + * Freescale RTC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.75 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___RTC_H +#define __ARCH_ARM___RTC_H + + +#define HW_RTC_CTRL (0x00000000) +#define HW_RTC_CTRL_SET (0x00000004) +#define HW_RTC_CTRL_CLR (0x00000008) +#define HW_RTC_CTRL_TOG (0x0000000c) + +#define BM_RTC_CTRL_SFTRST 0x80000000 +#define BM_RTC_CTRL_CLKGATE 0x40000000 +#define BP_RTC_CTRL_RSVD0 7 +#define BM_RTC_CTRL_RSVD0 0x3FFFFF80 +#define BF_RTC_CTRL_RSVD0(v) \ + (((v) << 7) & BM_RTC_CTRL_RSVD0) +#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040 +#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020 +#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 +#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 +#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 +#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 + +#define HW_RTC_STAT (0x00000010) +#define HW_RTC_STAT_SET (0x00000014) +#define HW_RTC_STAT_CLR (0x00000018) +#define HW_RTC_STAT_TOG (0x0000001c) + +#define BM_RTC_STAT_RTC_PRESENT 0x80000000 +#define BM_RTC_STAT_ALARM_PRESENT 0x40000000 +#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 +#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 +#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000 +#define BP_RTC_STAT_RSVD1 24 +#define BM_RTC_STAT_RSVD1 0x07000000 +#define BF_RTC_STAT_RSVD1(v) \ + (((v) << 24) & BM_RTC_STAT_RSVD1) +#define BP_RTC_STAT_STALE_REGS 16 +#define BM_RTC_STAT_STALE_REGS 0x00FF0000 +#define BF_RTC_STAT_STALE_REGS(v) \ + (((v) << 16) & BM_RTC_STAT_STALE_REGS) +#define BP_RTC_STAT_NEW_REGS 8 +#define BM_RTC_STAT_NEW_REGS 0x0000FF00 +#define BF_RTC_STAT_NEW_REGS(v) \ + (((v) << 8) & BM_RTC_STAT_NEW_REGS) +#define BP_RTC_STAT_RSVD0 0 +#define BM_RTC_STAT_RSVD0 0x000000FF +#define BF_RTC_STAT_RSVD0(v) \ + (((v) << 0) & BM_RTC_STAT_RSVD0) + +#define HW_RTC_MILLISECONDS (0x00000020) +#define HW_RTC_MILLISECONDS_SET (0x00000024) +#define HW_RTC_MILLISECONDS_CLR (0x00000028) +#define HW_RTC_MILLISECONDS_TOG (0x0000002c) + +#define BP_RTC_MILLISECONDS_COUNT 0 +#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_MILLISECONDS_COUNT(v) (v) + +#define HW_RTC_SECONDS (0x00000030) +#define HW_RTC_SECONDS_SET (0x00000034) +#define HW_RTC_SECONDS_CLR (0x00000038) +#define HW_RTC_SECONDS_TOG (0x0000003c) + +#define BP_RTC_SECONDS_COUNT 0 +#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_SECONDS_COUNT(v) (v) + +#define HW_RTC_ALARM (0x00000040) +#define HW_RTC_ALARM_SET (0x00000044) +#define HW_RTC_ALARM_CLR (0x00000048) +#define HW_RTC_ALARM_TOG (0x0000004c) + +#define BP_RTC_ALARM_VALUE 0 +#define BM_RTC_ALARM_VALUE 0xFFFFFFFF +#define BF_RTC_ALARM_VALUE(v) (v) + +#define HW_RTC_WATCHDOG (0x00000050) +#define HW_RTC_WATCHDOG_SET (0x00000054) +#define HW_RTC_WATCHDOG_CLR (0x00000058) +#define HW_RTC_WATCHDOG_TOG (0x0000005c) + +#define BP_RTC_WATCHDOG_COUNT 0 +#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF +#define BF_RTC_WATCHDOG_COUNT(v) (v) + +#define HW_RTC_PERSISTENT0 (0x00000060) +#define HW_RTC_PERSISTENT0_SET (0x00000064) +#define HW_RTC_PERSISTENT0_CLR (0x00000068) +#define HW_RTC_PERSISTENT0_TOG (0x0000006c) + +#define BP_RTC_PERSISTENT0_ADJ_POSLIMITBUCK 28 +#define BM_RTC_PERSISTENT0_ADJ_POSLIMITBUCK 0xF0000000 +#define BF_RTC_PERSISTENT0_ADJ_POSLIMITBUCK(v) \ + (((v) << 28) & BM_RTC_PERSISTENT0_ADJ_POSLIMITBUCK) +#define BP_RTC_PERSISTENT0_SPARE_ANALOG 22 +#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0x0FC00000 +#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \ + (((v) << 22) & BM_RTC_PERSISTENT0_SPARE_ANALOG) +#define BM_RTC_PERSISTENT0_EXTERNAL_RESET 0x00200000 +#define BM_RTC_PERSISTENT0_THERMAL_RESET 0x00100000 +#define BM_RTC_PERSISTENT0_RELEASE_GND 0x00080000 +#define BM_RTC_PERSISTENT0_ENABLE_LRADC_PWRUP 0x00040000 +#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000 +#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000 +#define BP_RTC_PERSISTENT0_LOWERBIAS 14 +#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000 +#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \ + (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS) +#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000 +#define BP_RTC_PERSISTENT0_MSEC_RES 8 +#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00 +#define BF_RTC_PERSISTENT0_MSEC_RES(v) \ + (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES) +#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 +#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040 +#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 +#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 +#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008 +#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 +#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 +#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001 + +#define HW_RTC_PERSISTENT1 (0x00000070) +#define HW_RTC_PERSISTENT1_SET (0x00000074) +#define HW_RTC_PERSISTENT1_CLR (0x00000078) +#define HW_RTC_PERSISTENT1_TOG (0x0000007c) + +#define BP_RTC_PERSISTENT1_GENERAL 0 +#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT1_GENERAL(v) (v) +#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 +#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800 +#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400 +#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080 + +#define HW_RTC_PERSISTENT2 (0x00000080) +#define HW_RTC_PERSISTENT2_SET (0x00000084) +#define HW_RTC_PERSISTENT2_CLR (0x00000088) +#define HW_RTC_PERSISTENT2_TOG (0x0000008c) + +#define BP_RTC_PERSISTENT2_GENERAL 0 +#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT2_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT3 (0x00000090) +#define HW_RTC_PERSISTENT3_SET (0x00000094) +#define HW_RTC_PERSISTENT3_CLR (0x00000098) +#define HW_RTC_PERSISTENT3_TOG (0x0000009c) + +#define BP_RTC_PERSISTENT3_GENERAL 0 +#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT3_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT4 (0x000000a0) +#define HW_RTC_PERSISTENT4_SET (0x000000a4) +#define HW_RTC_PERSISTENT4_CLR (0x000000a8) +#define HW_RTC_PERSISTENT4_TOG (0x000000ac) + +#define BP_RTC_PERSISTENT4_GENERAL 0 +#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT4_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT5 (0x000000b0) +#define HW_RTC_PERSISTENT5_SET (0x000000b4) +#define HW_RTC_PERSISTENT5_CLR (0x000000b8) +#define HW_RTC_PERSISTENT5_TOG (0x000000bc) + +#define BP_RTC_PERSISTENT5_GENERAL 0 +#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT5_GENERAL(v) (v) + +#define HW_RTC_DEBUG (0x000000c0) +#define HW_RTC_DEBUG_SET (0x000000c4) +#define HW_RTC_DEBUG_CLR (0x000000c8) +#define HW_RTC_DEBUG_TOG (0x000000cc) + +#define BP_RTC_DEBUG_RSVD0 2 +#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC +#define BF_RTC_DEBUG_RSVD0(v) \ + (((v) << 2) & BM_RTC_DEBUG_RSVD0) +#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002 +#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001 + +#define HW_RTC_VERSION (0x000000d0) + +#define BP_RTC_VERSION_MAJOR 24 +#define BM_RTC_VERSION_MAJOR 0xFF000000 +#define BF_RTC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_RTC_VERSION_MAJOR) +#define BP_RTC_VERSION_MINOR 16 +#define BM_RTC_VERSION_MINOR 0x00FF0000 +#define BF_RTC_VERSION_MINOR(v) \ + (((v) << 16) & BM_RTC_VERSION_MINOR) +#define BP_RTC_VERSION_STEP 0 +#define BM_RTC_VERSION_STEP 0x0000FFFF +#define BF_RTC_VERSION_STEP(v) \ + (((v) << 0) & BM_RTC_VERSION_STEP) +#endif /* __ARCH_ARM___RTC_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-ssp.h b/arch/arm/mach-mx28/include/mach/regs-ssp.h new file mode 100644 index 000000000000..1d4793b25a3b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ssp.h @@ -0,0 +1,474 @@ +/* + * Freescale SSP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 4.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H + +#ifndef BF +#define BF(value, field) (((value) << BP_##field) & BM_##field) +#endif + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) + +#define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_RSVD0 0 +#define BM_SSP_CTRL0_RSVD0 0x0000FFFF +#define BF_SSP_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_SSP_CTRL0_RSVD0) + +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) + +#define BP_SSP_CMD0_RSVD0 27 +#define BM_SSP_CMD0_RSVD0 0xF8000000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 27) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SOFT_TERMINATE 0x04000000 +#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000 +#define BM_SSP_CMD0_PRIM_BOOT_OP_EN 0x01000000 +#define BM_SSP_CMD0_BOOT_ACK_EN 0x00800000 +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 +#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 +#define BP_SSP_CMD0_RSVD1 8 +#define BM_SSP_CMD0_RSVD1 0x000FFF00 +#define BF_SSP_CMD0_RSVD1(v) \ + (((v) << 8) & BM_SSP_CMD0_RSVD1) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) + +#define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_XFER_SIZE (0x00000030) + +#define BP_SSP_XFER_SIZE_XFER_COUNT 0 +#define BM_SSP_XFER_SIZE_XFER_COUNT 0xFFFFFFFF +#define BF_SSP_XFER_SIZE_XFER_COUNT(v) (v) + +#define HW_SSP_BLOCK_SIZE (0x00000040) + +#define BP_SSP_BLOCK_SIZE_RSVD0 28 +#define BM_SSP_BLOCK_SIZE_RSVD0 0xF0000000 +#define BF_SSP_BLOCK_SIZE_RSVD0(v) \ + (((v) << 28) & BM_SSP_BLOCK_SIZE_RSVD0) +#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4 +#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0FFFFFF0 +#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \ + (((v) << 4) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT) +#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0 +#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x0000000F +#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \ + (((v) << 0) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE) + +#define HW_SSP_COMPREF (0x00000050) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000060) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000070) + +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000080) +#define HW_SSP_CTRL1_SET (0x00000084) +#define HW_SSP_CTRL1_CLR (0x00000088) +#define HW_SSP_CTRL1_TOG (0x0000008c) + +#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 + +#define HW_SSP_DATA (0x00000090) + +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) + +#define HW_SSP_SDRESP0 (0x000000a0) + +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) + +#define HW_SSP_SDRESP1 (0x000000b0) + +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000c0) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000d0) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_DDR_CTRL (0x000000e0) + +#define BP_SSP_DDR_CTRL_DMA_BURST_TYPE 30 +#define BM_SSP_DDR_CTRL_DMA_BURST_TYPE 0xC0000000 +#define BF_SSP_DDR_CTRL_DMA_BURST_TYPE(v) \ + (((v) << 30) & BM_SSP_DDR_CTRL_DMA_BURST_TYPE) +#define BP_SSP_DDR_CTRL_RSVD0 2 +#define BM_SSP_DDR_CTRL_RSVD0 0x3FFFFFFC +#define BF_SSP_DDR_CTRL_RSVD0(v) \ + (((v) << 2) & BM_SSP_DDR_CTRL_RSVD0) +#define BM_SSP_DDR_CTRL_NIBBLE_POS 0x00000002 +#define BM_SSP_DDR_CTRL_TXCLK_DELAY_TYPE 0x00000001 + +#define HW_SSP_DLL_CTRL (0x000000f0) + +#define BP_SSP_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_SSP_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_SSP_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_SSP_DLL_CTRL_REF_UPDATE_INT) +#define BP_SSP_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_SSP_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_SSP_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_SSP_DLL_CTRL_SLV_UPDATE_INT) +#define BP_SSP_DLL_CTRL_RSVD1 16 +#define BM_SSP_DLL_CTRL_RSVD1 0x000F0000 +#define BF_SSP_DLL_CTRL_RSVD1(v) \ + (((v) << 16) & BM_SSP_DLL_CTRL_RSVD1) +#define BP_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 0x0000FC00 +#define BF_SSP_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_SSP_DLL_CTRL_RSVD0 0x00000100 +#define BM_SSP_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_SSP_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_SSP_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_SSP_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_SSP_DLL_CTRL_SLV_DLY_TARGET) +#define BM_SSP_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_SSP_DLL_CTRL_RESET 0x00000002 +#define BM_SSP_DLL_CTRL_ENABLE 0x00000001 + +#define HW_SSP_STATUS (0x00000100) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 +#define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 23 +#define BM_SSP_STATUS_RSVD3 0x0F800000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 23) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMABURST 0x00400000 +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DLL_STS (0x00000110) + +#define BP_SSP_DLL_STS_RSVD0 14 +#define BM_SSP_DLL_STS_RSVD0 0xFFFFC000 +#define BF_SSP_DLL_STS_RSVD0(v) \ + (((v) << 14) & BM_SSP_DLL_STS_RSVD0) +#define BP_SSP_DLL_STS_REF_SEL 8 +#define BM_SSP_DLL_STS_REF_SEL 0x00003F00 +#define BF_SSP_DLL_STS_REF_SEL(v) \ + (((v) << 8) & BM_SSP_DLL_STS_REF_SEL) +#define BP_SSP_DLL_STS_SLV_SEL 2 +#define BM_SSP_DLL_STS_SLV_SEL 0x000000FC +#define BF_SSP_DLL_STS_SLV_SEL(v) \ + (((v) << 2) & BM_SSP_DLL_STS_SLV_SEL) +#define BM_SSP_DLL_STS_REF_LOCK 0x00000002 +#define BM_SSP_DLL_STS_SLV_LOCK 0x00000001 + +#define HW_SSP_DEBUG (0x00000120) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000130) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-timrot.h b/arch/arm/mach-mx28/include/mach/regs-timrot.h new file mode 100644 index 000000000000..125b835e19ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-timrot.h @@ -0,0 +1,293 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.40 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40) +#define BP_TIMROT_TIMCTRLn_RSRVD3 16 +#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD2 12 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF + +/* + * multi-register-define name HW_TIMROT_RUNNING_COUNTn + * base 0x00000030 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40) +#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_FIXED_COUNTn + * base 0x00000040 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40) +#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_MATCH_COUNTn + * base 0x00000050 + * count 4 + * offset 0x40 + */ +#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40) +#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0 +#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF +#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v) + +#define HW_TIMROT_TIMCTRL3 (0x000000e0) +#define HW_TIMROT_TIMCTRL3_SET (0x000000e4) +#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8) +#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 12 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800 +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF + +#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0) + +#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v) + +#define HW_TIMROT_FIXED_COUNT3 (0x00000100) + +#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v) + +#define HW_TIMROT_VERSION (0x00000120) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-mx28/include/mach/regulator.h b/arch/arm/mach-mx28/include/mach/regulator.h new file mode 100644 index 000000000000..1b073586268b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regulator.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __PLAT_REGULATOR_H_ +#define __PLAT_REGULATOR_H_ + +#define MXS_REG5V_NOT_USB 0 +#define MXS_REG5V_IS_USB 1 +#define MXS_VDDD 0 +#define MXS_VDDA 1 +#define MXS_VDDIO 2 +#define MXS_VDDDBO 3 +#define MXS_OVERALL_CUR 4 + +#endif |