diff options
Diffstat (limited to 'arch/arm/plat-mxc/include')
54 files changed, 12045 insertions, 285 deletions
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h new file mode 100644 index 000000000000..b6494e5fa219 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h @@ -0,0 +1,18 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_3DS_DB_H__ +#define __ASM_ARCH_MXC_3DS_DB_H__ + +extern int __init mxc_expio_init(u32 base, u32 p_irq); + +#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h new file mode 100644 index 000000000000..320fd7d11495 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/arc_otg.h @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_ARC_OTG_H__ +#define __ASM_ARCH_MXC_ARC_OTG_H__ + +#ifdef CONFIG_ARCH_MX3 +extern volatile u32 *mx3_usb_otg_addr; +#define OTG_BASE_ADDR mx3_usb_otg_addr +#endif +#define USB_OTGREGS_BASE (OTG_BASE_ADDR + 0x000) +#define USB_H1REGS_BASE (OTG_BASE_ADDR + 0x200) +#define USB_H2REGS_BASE (OTG_BASE_ADDR + 0x400) +#ifdef CONFIG_ARCH_MX5 +#define USB_H3REGS_BASE (OTG_BASE_ADDR + 0x600) +#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x800) +#else +#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x600) +#endif + + +#define USBOTG_REG32(offset) (*((volatile u32 *)(IO_ADDRESS(USB_OTGREGS_BASE + (offset))))) +#define USBOTG_REG16(offset) (*((volatile u16 *)(IO_ADDRESS(USB_OTGREGS_BASE + (offset))))) + +#define USBH1_REG32(offset) (*((volatile u32 *)(IO_ADDRESS(USB_H1REGS_BASE + (offset))))) +#define USBH1_REG16(offset) (*((volatile u16 *)(IO_ADDRESS(USB_H1REGS_BASE + (offset))))) + +#define USBH2_REG32(offset) (*((volatile u32 *)(IO_ADDRESS(USB_H2REGS_BASE + (offset))))) +#define USBH2_REG16(offset) (*((volatile u16 *)(IO_ADDRESS(USB_H2REGS_BASE + (offset))))) + +#define USBOTHER_REG(offset) (*((volatile u32 *)(IO_ADDRESS(USB_OTHERREGS_BASE + (offset))))) + +/* + * OTG registers + */ +#define UOG_ID USBOTG_REG32(0x00) /* Host ID */ +#define UOG_HWGENERAL USBOTG_REG32(0x04) /* Host General */ +#define UOG_HWHOST USBOTG_REG32(0x08) /* Host h/w params */ +#define UOG_HWTXBUF USBOTG_REG32(0x10) /* TX buffer h/w params */ +#define UOG_HWRXBUF USBOTG_REG32(0x14) /* RX buffer h/w params */ +#define UOG_CAPLENGTH USBOTG_REG16(0x100) /* Capability register length */ +#define UOG_HCIVERSION USBOTG_REG16(0x102) /* Host Interface version */ +#define UOG_HCSPARAMS USBOTG_REG32(0x104) /* Host control structural params */ +#define UOG_HCCPARAMS USBOTG_REG32(0x108) /* control capability params */ +#define UOG_DCIVERSION USBOTG_REG32(0x120) /* device interface version */ +/* start EHCI registers: */ +#define UOG_USBCMD USBOTG_REG32(0x140) /* USB command register */ +#define UOG_USBSTS USBOTG_REG32(0x144) /* USB status register */ +#define UOG_USBINTR USBOTG_REG32(0x148) /* interrupt enable register */ +#define UOG_FRINDEX USBOTG_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UOG_PERIODICLISTBASE USBOTG_REG32(0x154) /* host crtlr frame list base addr */ +#define UOG_DEVICEADDR USBOTG_REG32(0x154) /* device crtlr device address */ +#define UOG_ASYNCLISTADDR USBOTG_REG32(0x158) /* host ctrlr next async addr */ +#define UOG_EPLISTADDR USBOTG_REG32(0x158) /* device ctrlr endpoint list addr */ +#define UOG_BURSTSIZE USBOTG_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UOG_TXFILLTUNING USBOTG_REG32(0x164) /* TX FIFO fill tuning */ +#define UOG_ULPIVIEW USBOTG_REG32(0x170) /* ULPI viewport */ +#define UOG_CFGFLAG USBOTG_REG32(0x180) /* configflag (supports HS) */ +#define UOG_PORTSC1 USBOTG_REG32(0x184) /* port status and control */ +/* end EHCI registers: */ +#define UOG_OTGSC USBOTG_REG32(0x1a4) /* OTG status and control */ +#define UOG_USBMODE USBOTG_REG32(0x1a8) /* USB device mode */ +#define UOG_ENDPTSETUPSTAT USBOTG_REG32(0x1ac) /* endpoint setup status */ +#define UOG_ENDPTPRIME USBOTG_REG32(0x1b0) /* endpoint initialization */ +#define UOG_ENDPTFLUSH USBOTG_REG32(0x1b4) /* endpoint de-initialize */ +#define UOG_ENDPTSTAT USBOTG_REG32(0x1b8) /* endpoint status */ +#define UOG_ENDPTCOMPLETE USBOTG_REG32(0x1bc) /* endpoint complete */ +#define UOG_EPCTRL0 USBOTG_REG32(0x1c0) /* endpoint control0 */ +#define UOG_EPCTRL1 USBOTG_REG32(0x1c4) /* endpoint control1 */ +#define UOG_EPCTRL2 USBOTG_REG32(0x1c8) /* endpoint control2 */ +#define UOG_EPCTRL3 USBOTG_REG32(0x1cc) /* endpoint control3 */ +#define UOG_EPCTRL4 USBOTG_REG32(0x1d0) /* endpoint control4 */ +#define UOG_EPCTRL5 USBOTG_REG32(0x1d4) /* endpoint control5 */ +#define UOG_EPCTRL6 USBOTG_REG32(0x1d8) /* endpoint control6 */ +#define UOG_EPCTRL7 USBOTG_REG32(0x1dc) /* endpoint control7 */ + +/* + * Host 1 registers + */ +#define UH1_ID USBH1_REG32(0x00) /* Host ID */ +#define UH1_HWGENERAL USBH1_REG32(0x04) /* Host General */ +#define UH1_HWHOST USBH1_REG32(0x08) /* Host h/w params */ +#define UH1_HWTXBUF USBH1_REG32(0x10) /* TX buffer h/w params */ +#define UH1_HWRXBUF USBH1_REG32(0x14) /* RX buffer h/w params */ +#define UH1_CAPLENGTH USBH1_REG16(0x100) /* Capability register length */ +#define UH1_HCIVERSION USBH1_REG16(0x102) /* Host Interface version */ +#define UH1_HCSPARAMS USBH1_REG32(0x104) /* Host control structural params */ +#define UH1_HCCPARAMS USBH1_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH1_USBCMD USBH1_REG32(0x140) /* USB command register */ +#define UH1_USBSTS USBH1_REG32(0x144) /* USB status register */ +#define UH1_USBINTR USBH1_REG32(0x148) /* interrupt enable register */ +#define UH1_FRINDEX USBH1_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH1_PERIODICLISTBASE USBH1_REG32(0x154) /* host crtlr frame list base addr */ +#define UH1_ASYNCLISTADDR USBH1_REG32(0x158) /* host ctrlr nest async addr */ +#define UH1_BURSTSIZE USBH1_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH1_TXFILLTUNING USBH1_REG32(0x164) /* TX FIFO fill tuning */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH1_PORTSC1 USBH1_REG32(0x184) /* port status and control */ +/* end EHCI registers: */ +#define UH1_USBMODE USBH1_REG32(0x1a8) /* USB device mode */ + +/* + * Host 2 registers + */ +#define UH2_ID USBH2_REG32(0x00) /* Host ID */ +#define UH2_HWGENERAL USBH2_REG32(0x04) /* Host General */ +#define UH2_HWHOST USBH2_REG32(0x08) /* Host h/w params */ +#define UH2_HWTXBUF USBH2_REG32(0x10) /* TX buffer h/w params */ +#define UH2_HWRXBUF USBH2_REG32(0x14) /* RX buffer h/w params */ +#define UH2_CAPLENGTH USBH2_REG16(0x100) /* Capability register length */ +#define UH2_HCIVERSION USBH2_REG16(0x102) /* Host Interface version */ +#define UH2_HCSPARAMS USBH2_REG32(0x104) /* Host control structural params */ +#define UH2_HCCPARAMS USBH2_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH2_USBCMD USBH2_REG32(0x140) /* USB command register */ +#define UH2_USBSTS USBH2_REG32(0x144) /* USB status register */ +#define UH2_USBINTR USBH2_REG32(0x148) /* interrupt enable register */ +#define UH2_FRINDEX USBH2_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH2_PERIODICLISTBASE USBH2_REG32(0x154) /* host crtlr frame list base addr */ +#define UH2_ASYNCLISTADDR USBH2_REG32(0x158) /* host ctrlr nest async addr */ +#define UH2_BURSTSIZE USBH2_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH2_TXFILLTUNING USBH2_REG32(0x164) /* TX FIFO fill tuning */ +#define UH2_ULPIVIEW USBH2_REG32(0x170) /* ULPI viewport */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH2_PORTSC1 USBH2_REG32(0x184) /* port status and control */ +/* end EHCI registers */ +#define UH2_USBMODE USBH2_REG32(0x1a8) /* USB device mode */ + +/* + * other regs (not part of ARC core) + */ +#define USBCTRL USBOTHER_REG(0x00) /* USB Control register */ +#define USB_OTG_MIRROR USBOTHER_REG(0x04) /* USB OTG mirror register */ +#define USB_PHY_CTR_FUNC USBOTHER_REG(0x08) /* OTG UTMI PHY Function Control register */ +#define USB_PHY_CTR_FUNC2 USBOTHER_REG(0x0c) /* OTG UTMI PHY Function Control register */ +#define USB_CTRL_1 USBOTHER_REG(0x10) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST2 USBOTHER_REG(0x14) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/ +#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */ + +/* + * register bits + */ + +/* x_PORTSCx */ +#define PORTSC_PTS_MASK (3 << 30) /* parallel xcvr select mask */ +#define PORTSC_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */ +#define PORTSC_PTS_PHILIPS (1 << 30) /* Philips classic */ +#define PORTSC_PTS_ULPI (2 << 30) /* ULPI */ +#define PORTSC_PTS_SERIAL (3 << 30) /* serial */ +#define PORTSC_STS (1 << 29) /* serial xcvr select */ +#define PORTSC_PTW (1 << 28) /* UTMI width */ +#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */ +#define PORTSC_PORT_POWER (1 << 12) /* port power */ +#define PORTSC_LS_MASK (3 << 10) /* Line State mask */ +#define PORTSC_LS_SE0 (0 << 10) /* SE0 */ +#define PORTSC_LS_K_STATE (1 << 10) /* K-state */ +#define PORTSC_LS_J_STATE (2 << 10) /* J-state */ +#define PORTSC_PORT_RESET (1 << 8) /* Port reset */ +#define PORTSC_PORT_SUSPEND (1 << 7) /* Suspend */ +#define PORTSC_PORT_FORCE_RESUME (1 << 6) /* Force port resume */ +#define PORTSC_OVER_CURRENT_CHG (1 << 5) /* over current change */ +#define PORTSC_OVER_CURRENT_ACT (1 << 4) /* over currrent active */ +#define PORTSC_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change */ +#define PORTSC_PORT_ENABLE (1 << 2) /* port enabled */ +#define PORTSC_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */ +#define PORTSC_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */ + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CURRENT_CHG) + +/* UOG_OTGSC Register Bits */ +/* control bits: */ +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0) +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1) +#define OTGSC_CTRL_OTG_TERM (1 << 3) /* controls DM pulldown */ +#define OTGSC_CTRL_DATA_PULSING (1 << 4) +#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */ +/* current status: (R/O) */ +#define OTGSC_STS_USB_ID (1 << 8) /* 0=A-device 1=B-device */ +#define OTGSC_STS_A_VBUS_VALID (1 << 9) +#define OTGSC_STS_A_SESSION_VALID (1 << 10) +#define OTGSC_STS_B_SESSION_VALID (1 << 11) +#define OTGSC_STS_B_SESSION_END (1 << 12) +#define OTGSC_STS_1ms_TIMER (1 << 13) +#define OTGSC_STS_DATA_PULSE (1 << 14) +/* interrupt status: (write to clear) */ +#define OTGSC_IS_MASK (0x7f << 16) +#define OTGSC_IS_USB_ID (1 << 16) +#define OTGSC_IS_A_VBUS_VALID (1 << 17) +#define OTGSC_IS_A_SESSION_VALID (1 << 18) +#define OTGSC_IS_B_SESSION_VALID (1 << 19) +#define OTGSC_IS_B_SESSION_END (1 << 20) +#define OTGSC_IS_1ms_TIMER (1 << 21) +#define OTGSC_IS_DATA_PULSE (1 << 22) +/* interrupt enables: */ +#define OTGSC_IE_MASK (0x7f << 24) +#define OTGSC_IE_USB_ID (1 << 24) +#define OTGSC_IE_A_VBUS_VALID (1 << 25) +#define OTGSC_IE_A_SESSION_VALID (1 << 26) +#define OTGSC_IE_B_SESSION_VALID (1 << 27) +#define OTGSC_IE_B_SESSION_END (1 << 28) +#define OTGSC_IE_1ms_TIMER (1 << 29) +#define OTGSC_IE_DATA_PULSE (1 << 30) + +#if 1 /* FIXME these here for compatibility between my names and Leo's */ +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK +#define OTGSC_INTSTS_MASK OTGSC_IS_MASK + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_IS_MASK +#endif + +/* x_USBMODE */ +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */ +#define USBMODE_ES (1 << 2) /* (big) endian select */ +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ +#define USBMODE_CM_HOST (3 << 0) /* host */ +#define USBMODE_CM_DEVICE (2 << 0) /* device */ +#define USBMODE_CM_reserved (1 << 0) /* reserved */ + +/* USBCTRL */ +#define UCTRL_OWIR (1 << 31) /* OTG wakeup intr request received */ +#define UCTRL_OSIC_MASK (3 << 29) /* OTG Serial Interface Config: */ +#define UCTRL_OSIC_DU6 (0 << 29) /* Differential/unidirectional 6 wire */ +#define UCTRL_OSIC_DB4 (1 << 29) /* Differential/bidirectional 4 wire */ +#define UCTRL_OSIC_SU6 (2 << 29) /* single-ended/unidirectional 6 wire */ +#define UCTRL_OSIC_SB3 (3 << 29) /* single-ended/bidirectional 3 wire */ + +#define UCTRL_OUIE (1 << 28) /* OTG ULPI intr enable */ +#define UCTRL_OWIE (1 << 27) /* OTG wakeup intr enable */ +#define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */ +#define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */ +#define UCTRL_OPM (1 << 24) /* OTG power mask */ +#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */ +#ifdef CONFIG_ARCH_MX5 +#define UCTRL_H2WIR (1 << 17) /* HOST2 wakeup intr request received */ +#else +#define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */ +#endif +#define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */ +#define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */ +#define UCTRL_H2SIC_DB4 (1 << 21) /* Differential/bidirectional 4 wire */ +#define UCTRL_H2SIC_SU6 (2 << 21) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H2SIC_SB3 (3 << 21) /* single-ended/bidirectional 3 wire */ + +#ifdef CONFIG_ARCH_MX5 +#define UCTRL_H2UIE (1 << 8) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 7) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP 0 /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 4) /* HOST2 power mask */ +#else +#define UCTRL_H2UIE (1 << 20) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 19) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP (1 << 18) /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 16) /* HOST2 power mask */ +#endif +#define UCTRL_H2OVBWK_EN (1 << 6) /* OTG VBUS Wakeup Enable */ +#define UCTRL_H2OIDWK_EN (1 << 5) /* OTG ID Wakeup Enable */ + +#define UCTRL_H1WIR (1 << 15) /* HOST1 wakeup intr request received */ +#define UCTRL_H1SIC_MASK (3 << 13) /* HOST1 Serial Interface Config: */ +#define UCTRL_H1SIC_DU6 (0 << 13) /* Differential/unidirectional 6 wire */ +#define UCTRL_H1SIC_DB4 (1 << 13) /* Differential/bidirectional 4 wire */ +#define UCTRL_H1SIC_SU6 (2 << 13) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H1SIC_SB3 (3 << 13) /* single-ended/bidirectional 3 wire */ +#define UCTRL_OLOCKD (1 << 13) /* otg lock disable */ +#define UCTRL_H2LOCKD (1 << 12) /* HOST2 lock disable */ +#define UCTRL_H1UIE (1 << 12) /* Host1 ULPI interrupt enable */ + +#if defined(CONFIG_ARCH_MX37) +/* VBUS wakeup enable, UTMI only */ +#define UCTRL_VBUS_WKUP_EN (1 << 12) +#elif defined(CONFIG_ARCH_MX25) || defined(CONFIG_ARCH_MX35) +#define UCTRL_VBUS_WKUP_EN (1 << 15) +#endif + +#define UCTRL_PP (1 << 11) /* power polarity bit */ +#define UCTRL_H1WIE (1 << 11) /* HOST1 wakeup intr enable */ +#define UCTRL_H1BPVAL_RXDP (1 << 10) /* HOST1 RxDp status in bypass mode */ +#define UCTRL_XCSO (1 << 10) /* Xcvr Clock Select for OTG port */ +#define UCTRL_H1BPVAL_RXDM (1 << 9) /* HOST1 RxDm status in bypass mode */ +#define UCTRL_XCSH2 (1 << 9) /* Xcvr Clock Select for Host port */ +#define UCTRL_H1PM (1 << 8) /* HOST1 power mask */ +#define UCTRL_IP_PULIDP (1 << 8) /* Ipp_Puimpel_Pullup_Dp */ + +#define UCTRL_IP_PUE_UP (1 << 7) /* ipp_pue_pullup_dp */ +#define UCTRL_IP_PUE_DOWN (1 << 6) /* ipp_pue_pulldwn_dpdm */ +#define UCTRL_H2DT (1 << 5) /* HOST2 TLL disabled */ +#define UCTRL_H1DT (1 << 4) /* HOST1 TLL disabled */ +#define UCTRL_USBTE (1 << 4) /* USBT Transceiver enable */ +#define UCTRL_OCPOL (1 << 3) /* OverCurrent Polarity */ +#define UCTRL_OCE (1 << 2) /* OverCurrent Enable */ +#define UCTRL_H2OCPOL (1 << 2) /* OverCurrent Polarity of Host2 */ +#define UCTRL_H2OCS (1 << 1) /* Host OverCurrent State */ +#define UCTRL_BPE (1 << 0) /* bypass mode enable */ +#define UCTRL_OTD (1 << 0) /* OTG TLL Disable */ +#define UCTRL_OOCS (1 << 0) /* OTG OverCurrent State */ + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_ITC_NO_THRESHOLD (~(0xff << 16)) /* Interrupt Threshold Control */ + +/* OTG_MIRROR */ +#define OTGM_SESEND (1 << 4) /* B device session end */ +#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */ +#define OTGM_BSESVLD (1 << 2) /* B session Valid */ +#define OTGM_ASESVLD (1 << 1) /* A session Valid */ +#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */ + /* 1=high: Operate as B-device */ + /* 0=low : Operate as A-device */ + +/* USB_PHY_CTRL_FUNC */ +/* PHY control0 Register Bit Masks */ +#define USB_UTMI_PHYCTRL_CONF2 (1 << 26) + +#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24) +#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24) /* Enable Charger Detector */ +#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23) /* Charger Detector Power On Control */ +#define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */ +#define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */ +#define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */ +#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */ +/* USB_PHY_CTRL_FUNC2*/ +#define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3 +#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK 0x3 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT 19 + +/* USB_CTRL_1 */ +#define USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define USB_CTRL_UH2_EXT_CLK_EN (1 << 26) +#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY (1 << 2) +/* ULPIVIEW register bits */ +#define ULPIVW_OFF (0x170) +#define ULPIVW_WU (1 << 31) /* Wakeup */ +#define ULPIVW_RUN (1 << 30) /* read/write run */ +#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */ +#define ULPIVW_SS (1 << 27) /* SyncState */ +#define ULPIVW_PORT_MASK 0x07 /* Port field */ +#define ULPIVW_PORT_SHIFT 24 +#define ULPIVW_ADDR_MASK 0xFF /* data address field */ +#define ULPIVW_ADDR_SHIFT 16 +#define ULPIVW_RDATA_MASK 0xFF /* read data field */ +#define ULPIVW_RDATA_SHIFT 8 +#define ULPIVW_WDATA_MASK 0xFF /* write data field */ +#define ULPIVW_WDATA_SHIFT 0 + +#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ +/* USB Clock on/off Control Register */ +#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */ +#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */ +extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); +#endif diff --git a/arch/arm/plat-mxc/include/mach/audio_controls.h b/arch/arm/plat-mxc/include/mach/audio_controls.h new file mode 100644 index 000000000000..d314b9997443 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/audio_controls.h @@ -0,0 +1,220 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file include/asm-arm/arch-mxc/audio_controls.h + * @brief this file implements the mxc sound driver interface to OSS framework + * @ingroup SOUND_DRV + */ +#ifndef __ASM_ARCH_MXC_AUDIO_CONTROLS_H__ +#define __ASM_ARCH_MXC_AUDIO_CONTROLS_H__ + +/*! + * This ioctl can be used to get the adder configuration, use the audio control + * SNDCTL_MC13783_READ_OUT_MIXER.\n + * Possible returned values are : + * @see MC13783_AUDIO_ADDER_STEREO + * @see MC13783_AUDIO_ADDER_STEREO_OPPOSITE + * @see MC13783_AUDIO_ADDER_MONO + * @see MC13783_AUDIO_ADDER_MONO_OPPOSITE + * + */ +#define SNDCTL_MC13783_READ_OUT_ADDER _SIOR('Z', 6, int) + +/*! + * To set the adder configuration, use the audio control + * SNDCTL_MC13783_WRITE_OUT_MIXER. Possible arguments are : \n + * @see MC13783_AUDIO_ADDER_STEREO + * @see MC13783_AUDIO_ADDER_STEREO_OPPOSITE + * @see MC13783_AUDIO_ADDER_MONO + * @see MC13783_AUDIO_ADDER_MONO_OPPOSITE + * + */ +#define SNDCTL_MC13783_WRITE_OUT_ADDER _SIOWR('Z', 7, int) + +/*! + * To get the codec balance configuration, use the audio control + * SNDCTL_MC13783_READ_OUT_BALANCE.\n + * Range is 0 (-21 dB left) to 100 (-21 dB right), linear, 3dB step ; + * 50 is no balance. + * \n Examples: + * \n 0 : -21dB left 50 : balance deactivated 100 : -21 dB right + * + */ +#define SNDCTL_MC13783_READ_OUT_BALANCE _SIOR('Z', 8, int) + +/*! + * To set the codec balance configuration, use the audio control + * SNDCTL_MC13783_WRITE_OUT_BALANCE.\n + * Range is 0 (-21 dB left) to 100 (-21 dB right), linear, 3dB step ; + * 50 is no balance. + * \n Examples: + * \n 0 : -21dB left 50 : balance deactivated 100 : -21 dB right + * + */ +#define SNDCTL_MC13783_WRITE_OUT_BALANCE _SIOWR('Z', 9, int) + +/*! + * To set the codec filter configuration, use the audio control + * SNDCTL_MC13783_WRITE_CODEC_FILTER. + * The new configuration replaces the old one.\n + * Possible arguments are : + * @see MC13783_CODEC_FILTER_DISABLE + * @see MC13783_CODEC_FILTER_HIGH_PASS_IN + * @see MC13783_CODEC_FILTER_HIGH_PASS_OUT + * @see MC13783_CODEC_FILTER_DITHERING \n + * + */ +#define SNDCTL_MC13783_WRITE_CODEC_FILTER _SIOWR('Z', 20, int) + +/*! + * To get the codec filter configuration, use the audio control : + * SNDCTL_MC13783_READ_CODEC_FILTER. + * The new configuration replaces the old one.\n + * Possible returned values are : + * @see MC13783_CODEC_FILTER_DISABLE + * @see MC13783_CODEC_FILTER_HIGH_PASS_IN + * @see MC13783_CODEC_FILTER_HIGH_PASS_OUT + * @see MC13783_CODEC_FILTER_DITHERING \n + * + */ +#define SNDCTL_MC13783_READ_CODEC_FILTER _SIOR('Z', 21, int) + +/* + * To set the clock configuration, use the audio control + * SNDCTL_MC13783_WRITE_MASTER_CLOCK. \n + * Possible arguments are : \n + * 1 : to MCU master \n + * 2 : to MC13783 master + */ +#define SNDCTL_MC13783_WRITE_MASTER_CLOCK _SIOR('Z', 30, int) + +/*! + * To set the output port, use the audio control + * SNDCTL_MC13783_WRITE_PORT.\n + * Possible returned values are : + * \n 1 : to port 4 + * \n 2 : to port 5 + * Possible returned values are : + * \n 1 : port 4 + * \n 2 : port 5 + */ +#define SNDCTL_MC13783_WRITE_PORT _SIOR('Z', 31, int) + +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_STEREO 0x1 +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_STEREO_OPPOSITE 0x2 +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_MONO 0x4 +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_MONO_OPPOSITE 0x8 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DISABLE 0x0 +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_IN 0x1 +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_OUT 0x2 +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DITHERING 0x4 + +/*! + * Argument for the system audio clocking selection + * @see MXC_AUDIO_CLOCKING_MCU_MASTER + * @see SNDCTL_CLK_SET_MASTER + */ +#define MXC_AUDIO_CLOCKING_MC13783_MASTER 0x0 + +/*! + * Argument for the system audio clocking selection + * @see MXC_AUDIO_CLOCKING_MC13783_MASTER + * @see SNDCTL_CLK_SET_MASTER + */ +#define MXC_AUDIO_CLOCKING_MCU_MASTER 0x1 + +/*! + * Argument for the DAM output port selection + * @see SNDCTL_DAM_SET_OUT_PORT + * @see MXC_DAM_OUT_PORT_AD2 + */ +#define MXC_DAM_OUT_PORT_AD1 0x0 + +/*! + * Argument for the DAM output port selection + * @see SNDCTL_DAM_SET_OUT_PORT + * @see MXC_DAM_OUT_PORT_AD1 + */ +#define MXC_DAM_OUT_PORT_AD2 0x1 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DISABLE 0x0 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_IN 0x1 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_OUT 0x2 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DITHERING 0x4 + +#endif /* __ASM_ARCH_MXC_AUDIO_CONTROLS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h new file mode 100644 index 000000000000..2bcf9db26177 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h @@ -0,0 +1,55 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ +#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ + +#include <mach/irqs.h> + +#define MXC_PSEUDO_PARENT MXC_INT_FORCE +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX35_GPIO1_1) + +enum { + MCU_INT_HEADPHONE = 0, + MCU_INT_GPS, + MCU_INT_SD1_CD, + MCU_INT_SD1_WP, + MCU_INT_SD2_CD, + MCU_INT_SD2_WP, + MCU_INT_POWER_KEY, + MCU_INT_RTC, + MCU_INT_TS_ADC, + MCU_INT_KEYPAD, +}; + +#define MXC_PSEUDO_IRQ_HEADPHONE (MXC_PSEUDO_IO_BASE + MCU_INT_HEADPHONE) +#define MXC_PSEUDO_IRQ_GPS (MXC_PSEUDO_IO_BASE + MCU_INT_GPS) +#define MXC_PSEUDO_IRQ_SD1_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_CD) +#define MXC_PSEUDO_IRQ_SD1_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_WP) +#define MXC_PSEUDO_IRQ_SD2_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_CD) +#define MXC_PSEUDO_IRQ_SD2_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_WP) +#define MXC_PSEUDO_IRQ_POWER_KEY (MXC_PSEUDO_IO_BASE + MCU_INT_POWER_KEY) +#define MXC_PSEUDO_IRQ_KEYPAD (MXC_PSEUDO_IO_BASE + MCU_INT_KEYPAD) +#define MXC_PSEUDO_IRQ_RTC (MXC_PSEUDO_IO_BASE + MCU_INT_RTC) +#define MXC_PSEUDO_IRQ_TS_ADC (MXC_PSEUDO_IO_BASE + MCU_INT_TS_ADC) + +extern int is_suspend_ops_started(void); +extern int __init mx35_3stack_init_mc13892(void); +extern int __init mx35_3stack_init_mc9s08dz60(void); + +#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 753a5988d85c..b414aafac1f8 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -25,6 +25,12 @@ struct module; +struct mxc_clk { + struct list_head node; + char name[20]; + struct clk *reg_clk; +}; + struct clk { int id; /* Source clock this clk depends on */ @@ -57,8 +63,18 @@ struct clk { int (*set_parent) (struct clk *, struct clk *); }; -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); +int clk_register(struct mxc_clk *clk); +void clk_unregister(struct mxc_clk *clk); +int clk_get_usecount(struct clk *clk); +int clk_set_pll_dither(struct clk *clk, unsigned int pll_ppm); + +/* Clock flags */ +#define RATE_PROPAGATES (1 << 0) /* Program children too */ +#define ALWAYS_ENABLED (1 << 1) /* Clock cannot be disabled */ +#define RATE_FIXED (1 << 2) /* Fixed clock rate */ +#define CPU_FREQ_TRIG_UPDATE (1 << 3) /* CPUFREQ trig update */ +#define AHB_HIGH_SET_POINT (1 << 4) /* Requires max AHB clock */ +#define AHB_MED_SET_POINT (1 << 5) /* Requires med AHB clock */ unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 2941472582d2..75b739d254a3 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -20,7 +20,8 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); -extern void mx51_map_io(void); +extern void mx37_map_io(void); +extern void mx5_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); @@ -30,8 +31,9 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); -extern void mx51_init_irq(void); +extern void mx5_init_irq(void); extern void mxc91231_init_irq(void); +extern void mxc_tzic_init_irq(unsigned long); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); @@ -39,9 +41,16 @@ extern int mx25_clocks_init(void); extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); +extern int mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); +extern void mxc_cpu_init(void); +extern void mxc_cpu_common_init(void); +extern void early_console_setup(unsigned long base, struct clk *clk); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 0b6e11eaeb8c..a5a8df40257c 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -49,7 +49,7 @@ #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx51.h> +#include <mach/mx5x.h> #define UART_PADDR MX51_UART1_BASE_ADDR #define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h new file mode 100644 index 000000000000..6022a6a20376 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/init.h> + +struct platform_device *imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data); + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) +#include <linux/can/platform/flexcan.h> +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata); +#else +/* the ifdef can be removed once the flexcan driver has been merged */ +struct flexcan_platform_data; +static inline struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + return NULL; +} +#endif + +#include <mach/i2c.h> +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata); + +#include <mach/imx-uart.h> +struct imx_imx_uart_3irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irqrx; + resource_size_t irqtx; + resource_size_t irqrts; +}; +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, + const struct imxuart_platform_data *pdata); + +struct imx_imx_uart_1irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, + const struct imxuart_platform_data *pdata); + +#include <mach/mxc_nand.h> +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); + +#include <mach/spi.h> +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata); + +#include <mach/mmc.h> +struct platform_device *__init imx_add_imx_mmc(int id, + resource_size_t iobase, resource_size_t iosize, int irq1, + int irq2, const struct mxc_mmc_platform_data *pdata); diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h new file mode 100644 index 000000000000..7b10512f892b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dma.h @@ -0,0 +1,305 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_DMA_H__ +#define __ASM_ARCH_MXC_DMA_H__ + +#include <linux/scatterlist.h> + +#define MXC_DMA_DYNAMIC_CHANNEL 255 + +#define MXC_DMA_DONE 0x0 +#define MXC_DMA_REQUEST_TIMEOUT 0x1 +#define MXC_DMA_TRANSFER_ERROR 0x2 + +/*! This defines the list of device ID's for DMA */ +typedef enum mxc_dma_device { + MXC_DMA_UART1_RX, + MXC_DMA_UART1_TX, + MXC_DMA_UART2_RX, + MXC_DMA_UART2_TX, + MXC_DMA_UART3_RX, + MXC_DMA_UART3_TX, + MXC_DMA_UART4_RX, + MXC_DMA_UART4_TX, + MXC_DMA_UART5_RX, + MXC_DMA_UART5_TX, + MXC_DMA_UART6_RX, + MXC_DMA_UART6_TX, + MXC_DMA_MMC1_WIDTH_1, + MXC_DMA_MMC1_WIDTH_4, + MXC_DMA_MMC2_WIDTH_1, + MXC_DMA_MMC2_WIDTH_4, + MXC_DMA_SSI1_8BIT_RX0, + MXC_DMA_SSI1_8BIT_TX0, + MXC_DMA_SSI1_16BIT_RX0, + MXC_DMA_SSI1_16BIT_TX0, + MXC_DMA_SSI1_24BIT_RX0, + MXC_DMA_SSI1_24BIT_TX0, + MXC_DMA_SSI1_8BIT_RX1, + MXC_DMA_SSI1_8BIT_TX1, + MXC_DMA_SSI1_16BIT_RX1, + MXC_DMA_SSI1_16BIT_TX1, + MXC_DMA_SSI1_24BIT_RX1, + MXC_DMA_SSI1_24BIT_TX1, + MXC_DMA_SSI2_8BIT_RX0, + MXC_DMA_SSI2_8BIT_TX0, + MXC_DMA_SSI2_16BIT_RX0, + MXC_DMA_SSI2_16BIT_TX0, + MXC_DMA_SSI2_24BIT_RX0, + MXC_DMA_SSI2_24BIT_TX0, + MXC_DMA_SSI2_8BIT_RX1, + MXC_DMA_SSI2_8BIT_TX1, + MXC_DMA_SSI2_16BIT_RX1, + MXC_DMA_SSI2_16BIT_TX1, + MXC_DMA_SSI2_24BIT_RX1, + MXC_DMA_SSI2_24BIT_TX1, + MXC_DMA_SSI3_8BIT_RX0, + MXC_DMA_SSI3_8BIT_TX0, + MXC_DMA_SSI3_16BIT_RX0, + MXC_DMA_SSI3_16BIT_TX0, + MXC_DMA_SSI3_24BIT_RX0, + MXC_DMA_SSI3_24BIT_TX0, + MXC_DMA_SSI3_8BIT_RX1, + MXC_DMA_SSI3_8BIT_TX1, + MXC_DMA_SSI3_16BIT_RX1, + MXC_DMA_SSI3_16BIT_TX1, + MXC_DMA_SSI3_24BIT_RX1, + MXC_DMA_SSI3_24BIT_TX1, + MXC_DMA_FIR_RX, + MXC_DMA_FIR_TX, + MXC_DMA_CSPI1_RX, + MXC_DMA_CSPI1_TX, + MXC_DMA_CSPI2_RX, + MXC_DMA_CSPI2_TX, + MXC_DMA_CSPI3_RX, + MXC_DMA_CSPI3_TX, + MXC_DMA_ATA_RX, + MXC_DMA_ATA_TX, + MXC_DMA_MEMORY, + MXC_DMA_FIFO_MEMORY, + MXC_DMA_DSP_PACKET_DATA0_RD, + MXC_DMA_DSP_PACKET_DATA0_WR, + MXC_DMA_DSP_PACKET_DATA1_RD, + MXC_DMA_DSP_PACKET_DATA1_WR, + MXC_DMA_DSP_LOG0_CHNL, + MXC_DMA_DSP_LOG1_CHNL, + MXC_DMA_DSP_LOG2_CHNL, + MXC_DMA_DSP_LOG3_CHNL, + MXC_DMA_CSI_RX, + MXC_DMA_SPDIF_16BIT_TX, + MXC_DMA_SPDIF_16BIT_RX, + MXC_DMA_SPDIF_32BIT_TX, + MXC_DMA_SPDIF_32BIT_RX, + MXC_DMA_ASRC_A_RX, + MXC_DMA_ASRC_A_TX, + MXC_DMA_ASRC_B_RX, + MXC_DMA_ASRC_B_TX, + MXC_DMA_ASRC_C_RX, + MXC_DMA_ASRC_C_TX, + MXC_DMA_ASRCA_ESAI, + MXC_DMA_ASRCB_ESAI, + MXC_DMA_ASRCC_ESAI, + MXC_DMA_ASRCA_SSI1_TX0, + MXC_DMA_ASRCA_SSI1_TX1, + MXC_DMA_ASRCA_SSI2_TX0, + MXC_DMA_ASRCA_SSI2_TX1, + MXC_DMA_ASRCB_SSI1_TX0, + MXC_DMA_ASRCB_SSI1_TX1, + MXC_DMA_ASRCB_SSI2_TX0, + MXC_DMA_ASRCB_SSI2_TX1, + MXC_DMA_ESAI_16BIT_RX, + MXC_DMA_ESAI_16BIT_TX, + MXC_DMA_ESAI_24BIT_RX, + MXC_DMA_ESAI_24BIT_TX, + MXC_DMA_TEST_RAM2D2RAM, + MXC_DMA_TEST_RAM2RAM2D, + MXC_DMA_TEST_RAM2D2RAM2D, + MXC_DMA_TEST_RAM2RAM, + MXC_DMA_TEST_HW_CHAINING, + MXC_DMA_TEST_SW_CHAINING +} mxc_dma_device_t; + +/*! This defines the prototype of callback funtion registered by the drivers */ +typedef void (*mxc_dma_callback_t) (void *arg, int error_status, + unsigned int count); + +/*! This defines the type of DMA transfer requested */ +typedef enum mxc_dma_mode { + MXC_DMA_MODE_READ, + MXC_DMA_MODE_WRITE, +} mxc_dma_mode_t; + +/*! This defines the DMA channel parameters */ +typedef struct mxc_dma_channel { + unsigned int active:1; /*!< When there has a active tranfer, it is set to 1 */ + unsigned int lock; /*!< Defines the channel is allocated or not */ + int curr_buf; /*!< Current buffer */ + mxc_dma_mode_t mode; /*!< Read or Write */ + unsigned int channel; /*!< Channel info */ + unsigned int dynamic:1; /*!< Channel not statically allocated when 1 */ + char *dev_name; /*!< Device name */ + void *private; /*!< Private structure for platform */ + mxc_dma_callback_t cb_fn; /*!< The callback function */ + void *cb_args; /*!< The argument of callback function */ +} mxc_dma_channel_t; + +/*! This structure contains the information about a dma transfer */ +typedef struct mxc_dma_requestbuf { + dma_addr_t src_addr; /*!< source address */ + dma_addr_t dst_addr; /*!< destination address */ + int num_of_bytes; /*!< the length of this transfer : bytes */ +} mxc_dma_requestbuf_t; + +/*! This struct contains the information for asrc special*/ +struct dma_channel_asrc_info { + u32 channs; /*!< data channels in asrc */ +}; + +/*! This struct contains the information for device special*/ +struct dma_channel_info { + struct dma_channel_asrc_info asrc; /*!< asrc special information */ +}; + +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX21) +#include <mach/mx2_dma.h> +#else +#include <mach/sdma.h> +#endif + +/*! + * This function is generally called by the driver at open time. + * The DMA driver would do any initialization steps that is required + * to get the channel ready for data transfer. + * + * @param channel_id a pre-defined id. The peripheral driver would specify + * the id associated with its peripheral. This would be + * used by the DMA driver to identify the peripheral + * requesting DMA and do the necessary setup on the + * channel associated with the particular peripheral. + * The DMA driver could use static or dynamic DMA channel + * allocation. + * @param dev_name module name or device name + * @param data the customized parameter for special channel. + * @return returns a negative number on error if request for a DMA channel did not + * succeed, returns the channel number to be used on success. + */ +extern int mxc_dma_request_ext(mxc_dma_device_t channel_id, char *dev_name, + struct dma_channel_info *info); + +static inline int mxc_dma_request(mxc_dma_device_t channel_id, char *dev_name) +{ + return mxc_dma_request_ext(channel_id, dev_name, NULL); +} + +/*! + * This function is generally called by the driver at close time. The DMA + * driver would do any cleanup associated with this channel. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +extern int mxc_dma_free(int channel_num); + +/*! + * This function would just configure the buffers specified by the user into + * dma channel. The caller must call mxc_dma_enable to start this transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param dma_buf an array of physical addresses to the user defined + * buffers. The caller must guarantee the dma_buf is + * available until the transfer is completed. + * @param num_buf number of buffers in the array + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not be + * added with DMA for transfer. On Success, it returns 0 + */ +extern int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t *dma_buf, + int num_buf, mxc_dma_mode_t mode); + +/*! + * This function would just configure the scatterlist specified by the + * user into dma channel. This is a slight variation of mxc_dma_config(), + * it is provided for the convenience of drivers that have a scatterlist + * passed into them. It is the calling driver's responsibility to have the + * correct physical address filled in the "dma_address" field of the + * scatterlist. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param sg a scatterlist of buffers. The caller must guarantee + * the dma_buf is available until the transfer is + * completed. + * @param num_buf number of buffers in the array + * @param num_of_bytes total number of bytes to transfer. If set to 0, this + * would imply to use the length field of the scatterlist + * for each DMA transfer. Else it would calculate the size + * for each DMA transfer. + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not + * be added with DMA for transfer. On Success, it returns 0 + */ +extern int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, + mxc_dma_mode_t mode); + +/*! + * This function is provided if the driver would like to set/change its + * callback function. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param callback a callback function to provide notification on transfer + * completion, user could specify NULL if he does not wish + * to be notified + * @param arg an argument that gets passed in to the callback + * function, used by the user to do any driver specific + * operations. + * @return this function returns a negative number on error if the callback + * could not be set for the channel or 0 on success + */ +extern int mxc_dma_callback_set(int channel_num, mxc_dma_callback_t callback, + void *arg); + +/*! + * This stops the DMA channel and any ongoing transfers. Subsequent use of + * mxc_dma_enable() will restart the channel and restart the transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +extern int mxc_dma_disable(int channel_num); + +/*! + * This starts DMA transfer. Or it restarts DMA on a stopped channel + * previously stopped with mxc_dma_disable(). + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +extern int mxc_dma_enable(int channel_num); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/dmaengine.h b/arch/arm/plat-mxc/include/mach/dmaengine.h new file mode 100644 index 000000000000..8f7c84031ddd --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dmaengine.h @@ -0,0 +1,515 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DMA_H +#define __ASM_ARM_ARCH_DMA_H + +#ifndef ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 8 + +/** + * struct mxs_dma_cmd_bits - MXS DMA hardware command bits. + * + * This structure describes the in-memory layout of the command bits in a DMA + * command. See the appropriate reference manual for a detailed description + * of what these bits mean to the DMA hardware. + */ +struct mxs_dma_cmd_bits { + unsigned int command:2; +#define NO_DMA_XFER 0x00 +#define DMA_WRITE 0x01 +#define DMA_READ 0x02 +#define DMA_SENSE 0x03 + + unsigned int chain:1; + unsigned int irq:1; + unsigned int nand_lock:1; + unsigned int nand_wait_4_ready:1; + unsigned int dec_sem:1; + unsigned int wait4end:1; + unsigned int halt_on_terminate:1; + unsigned int terminate_flush:1; + unsigned int resv2:2; + unsigned int pio_words:4; + unsigned int bytes:16; +}; + +/* fill the word 1 of the DMA channel command structure */ +#define fill_dma_word1(cmdp, _cmd, _chain, _irq, _lock, _wait_ready, _dec_sem,\ + _wait4end, _halt_on_term, _term_flush, _pio_words, _bytes)\ + do { \ + struct mxs_dma_cmd_bits *bits = &(cmdp)->bits; \ + \ + /* reset all the fields first */ \ + (cmdp)->data = 0; \ + \ + bits->command = _cmd; \ + bits->chain = _chain; \ + bits->irq = _irq; \ + bits->nand_lock = _lock; \ + bits->nand_wait_4_ready = _wait_ready; \ + bits->dec_sem = _dec_sem; \ + bits->wait4end = _wait4end; \ + bits->halt_on_terminate = _halt_on_term; \ + bits->terminate_flush = _term_flush; \ + bits->pio_words = _pio_words; \ + bits->bytes = _bytes; \ + } while (0) + +/** + * struct mxs_dma_cmd - MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +struct mxs_dma_cmd { + unsigned long next; + union { + unsigned long data; + struct mxs_dma_cmd_bits bits; + } cmd; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/** + * struct mxs_dma_desc - MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + * + * @cmd: The MXS DMA hardware command block. + * @flags: Flags that represent the state of this DMA descriptor. + * @address: The physical address of this descriptor. + * @buffer: A convenient place for software to put the virtual address of the + * associated data buffer (the physical address of the buffer + * appears in the DMA command). The MXS platform DMA software doesn't + * use this field -- it is provided as a convenience. + * @node: Links this structure into a list. + */ +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; +#define MXS_DMA_DESC_READY 0x80000000 +#define MXS_DMA_DESC_FIRST 0x00000001 +#define MXS_DMA_DESC_LAST 0x00000002 + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +struct mxs_dma_info { + unsigned int status; +#define MXS_DMA_INFO_ERR 0x00000001 +#define MXS_DMA_INFO_ERR_STAT 0x00010000 + unsigned int buf_addr; +}; + +/** + * struct mxs_dma_chan - MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + * + * @name: A human-readable string that describes how this channel is + * being used or what software "owns" it. This field is set when + * when the channel is reserved by mxs_dma_request(). + * @dev: A pointer to a struct device *, cast to an unsigned long, and + * representing the software that "owns" the channel. This field + * is set when when the channel is reserved by mxs_dma_request(). + * @lock: Arbitrates access to this channel. + * @dma: A pointer to a struct mxs_dma_device representing the driver + * code that operates this channel. + * @flags: Flag bits that represent the state of this channel. + * @active_num: If the channel is not busy, this value is zero. If the channel + * is busy, this field contains the number of DMA command + * descriptors at the head of the active list that the hardware + * has been told to process. This value is set at the moment the + * channel is enabled by mxs_dma_enable(). More descriptors may + * arrive after the channel is enabled, so the number of + * descriptors on the active list may be greater than this value. + * In fact, it should always be active_num + pending_num. + * @pending_num: The number of DMA command descriptors at the tail of the + * active list that the hardware has not been told to process. + * @active: The list of DMA command descriptors either currently being + * processed by the hardware or waiting to be processed. + * Descriptors being processed appear at the head of the list, + * while pending descriptors appear at the tail. The total number + * should always be active_num + pending_num. + * @done: The list of DMA command descriptors that have either been + * processed by the DMA hardware or aborted by a call to + * mxs_dma_disable(). + */ +struct mxs_dma_chan { + const char *name; + unsigned long dev; + spinlock_t lock; + struct mxs_dma_device *dma; + unsigned int flags; +#define MXS_DMA_FLAGS_IDLE 0x00000000 +#define MXS_DMA_FLAGS_BUSY 0x00000001 +#define MXS_DMA_FLAGS_FREE 0x00000000 +#define MXS_DMA_FLAGS_ALLOCATED 0x00010000 +#define MXS_DMA_FLAGS_VALID 0x80000000 + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/** + * struct mxs_dma_device - DMA channel driver interface. + * + * This structure represents the driver that operates a DMA channel. Every + * struct mxs_dma_chan contains a pointer to a structure of this type, which is + * installed when the driver registers to "own" the channel (see + * mxs_dma_device_register()). + */ +struct mxs_dma_device { + struct list_head node; + const char *name; + void __iomem *base; + unsigned int chan_base; + unsigned int chan_num; + unsigned int data; + struct platform_device *pdev; + + /* operations */ + int (*enable) (struct mxs_dma_chan *, unsigned int); + void (*disable) (struct mxs_dma_chan *, unsigned int); + void (*reset) (struct mxs_dma_device *, unsigned int); + void (*freeze) (struct mxs_dma_device *, unsigned int); + void (*unfreeze) (struct mxs_dma_device *, unsigned int); + int (*read_semaphore) (struct mxs_dma_device *, unsigned int); + void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned); + void (*info)(struct mxs_dma_device *, + unsigned int, struct mxs_dma_info *info); + void (*enable_irq) (struct mxs_dma_device *, unsigned int, int); + int (*irq_is_pending) (struct mxs_dma_device *, unsigned int); + void (*ack_irq) (struct mxs_dma_device *, unsigned int); + + void (*set_target) (struct mxs_dma_device *, unsigned int, int); +}; + +/** + * mxs_dma_device_register - Register a DMA driver. + * + * This function registers a driver for a contiguous group of DMA channels (the + * ordering of DMA channels is specified by the globally unique DMA channel + * numbers given in mach/dma.h). + * + * @pdev: A pointer to a structure that represents the driver. This structure + * contains fields that specify the first DMA channel number and the + * number of channels. + */ +extern int mxs_dma_device_register(struct mxs_dma_device *pdev); + +/** + * mxs_dma_request - Request to reserve a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." + * @name: A human-readable string that identifies the channel owner or the + * purpose of the channel. + */ +extern int mxs_dma_request(int channel, struct device *dev, const char *name); + +/** + * mxs_dma_release - Release a DMA channel. + * + * This function releases a DMA channel from its current owner. + * + * The channel will NOT be released if it's marked "busy" (see + * mxs_dma_enable()). + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." If + * this doesn't match the owner given to mxs_dma_request(), the + * channel will NOT be released. + */ +extern void mxs_dma_release(int channel, struct device *dev); + +/** + * mxs_dma_enable - Enable a DMA channel. + * + * If the given channel has any DMA descriptors on its active list, this + * function causes the DMA hardware to begin processing them. + * + * This function marks the DMA channel as "busy," whether or not there are any + * descriptors to process. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_enable(int channel); + +/** + * mxs_dma_disable - Disable a DMA channel. + * + * This function shuts down a DMA channel and marks it as "not busy." Any + * descriptors on the active list are immediately moved to the head of the + * "done" list, whether or not they have actually been processed by the + * hardware. The "ready" flags of these descriptors are NOT cleared, so they + * still appear to be active. + * + * This function immediately shuts down a DMA channel's hardware, aborting any + * I/O that may be in progress, potentially leaving I/O hardware in an undefined + * state. It is unwise to call this function if there is ANY chance the hardware + * is still processing a command. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_disable(int channel); + +/** + * mxs_dma_reset - Resets the DMA channel hardware. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_reset(int channel); + +/** + * mxs_dma_freeze - Freeze a DMA channel. + * + * This function causes the channel to continuously fail arbitration for bus + * access, which halts all forward progress without losing any state. A call to + * mxs_dma_unfreeze() will cause the channel to continue its current operation + * with no ill effect. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_freeze(int channel); + +/** + * mxs_dma_unfreeze - Unfreeze a DMA channel. + * + * This function reverses the effect of mxs_dma_freeze(), enabling the DMA + * channel to continue from where it was frozen. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ + +extern void mxs_dma_unfreeze(int channel); + +/* get dma channel information */ +extern int mxs_dma_get_info(int channel, struct mxs_dma_info *info); + +/** + * mxs_dma_cooked - Clean up processed DMA descriptors. + * + * This function removes processed DMA descriptors from the "active" list. Pass + * in a non-NULL list head to get the descriptors moved to your list. Pass NULL + * to get the descriptors moved to the channel's "done" list. Descriptors on + * the "done" list can be retrieved with mxs_dma_get_cooked(). + * + * This function marks the DMA channel as "not busy" if no unprocessed + * descriptors remain on the "active" list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: If this is not NULL, it is the list to which the processed + * descriptors should be moved. If this list is NULL, the descriptors + * will be moved to the "done" list. + */ +extern int mxs_dma_cooked(int channel, struct list_head *head); + +/** + * mxs_dma_read_semaphore - Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_read_semaphore(int channel); + +/** + * mxs_dma_irq_is_pending - Check if a DMA interrupt is pending. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_irq_is_pending(int channel); + +/** + * mxs_dma_enable_irq - Enable or disable DMA interrupt. + * + * This function enables the given DMA channel to interrupt the CPU. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @en: True if the interrupt for this channel should be enabled. False + * otherwise. + */ +extern void mxs_dma_enable_irq(int channel, int en); + +/** + * mxs_dma_ack_irq - Clear DMA interrupt. + * + * The software that is using the DMA channel must register to receive its + * interrupts and, when they arrive, must call this function to clear them. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_ack_irq(int channel); + +/** + * mxs_dma_set_target - Set the target for a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @target: Indicates the target for the channel. + */ +extern void mxs_dma_set_target(int channel, int target); + +/* mxs dma utility functions */ +extern struct mxs_dma_desc *mxs_dma_alloc_desc(void); +extern void mxs_dma_free_desc(struct mxs_dma_desc *); + +/** + * mxs_dma_cmd_address - Return the address of the command within a descriptor. + * + * @desc: The DMA descriptor of interest. + */ +static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address += offsetof(struct mxs_dma_desc, cmd); +} + +/** + * mxs_dma_desc_pending - Check if descriptor is on a channel's active list. + * + * This function returns the state of a descriptor's "ready" flag. This flag is + * usually set only if the descriptor appears on a channel's active list. The + * descriptor may or may not have already been processed by the hardware. + * + * The "ready" flag is set when the descriptor is submitted to a channel by a + * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is + * cleared when a processed descriptor is moved off the active list by a call + * to mxs_dma_cooked(). The "ready" flag is NOT cleared if the descriptor is + * aborted by a call to mxs_dma_disable(). + * + * @desc: The DMA descriptor of interest. + */ +static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) +{ + return pdesc->flags & MXS_DMA_DESC_READY; +} + +/** + * mxs_dma_desc_append - Add a DMA descriptor to a channel. + * + * If the descriptor list for this channel is not empty, this function sets the + * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so + * it will chain to the new descriptor's command. + * + * Then, this function marks the new descriptor as "ready," adds it to the end + * of the active descriptor list, and increments the count of pending + * descriptors. + * + * The MXS platform DMA software imposes some rules on DMA commands to maintain + * important invariants. These rules are NOT checked, but they must be carefully + * applied by software that uses MXS DMA channels. + * + * Invariant: + * The DMA channel's hardware semaphore must reflect the number of DMA + * commands the hardware will process, but has not yet finished. + * + * Explanation: + * A DMA channel begins processing commands when its hardware semaphore is + * written with a value greater than zero, and it stops processing commands + * when the semaphore returns to zero. + * + * When a channel finishes a DMA command, it will decrement its semaphore if + * the DECREMENT_SEMAPHORE bit is set in that command's flags bits. + * + * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set, + * unless it suits the purposes of the software. For example, one could + * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE + * bit set only in the last one. Then, setting the DMA channel's hardware + * semaphore to one would cause the entire series of five commands to be + * processed. However, this example would violate the invariant given above. + * + * Rule: + * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA + * channel's hardware semaphore will be decremented EVERY time a command is + * processed. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @pdesc: A pointer to the new descriptor. + */ +extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +/** + * mxs_dma_desc_add_list - Add a list of DMA descriptors to a channel. + * + * This function marks all the new descriptors as "ready," adds them to the end + * of the active descriptor list, and adds the length of the list to the count + * of pending descriptors. + * + * See mxs_dma_desc_append() for important rules that apply to incoming DMA + * descriptors. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list of DMA descriptors to add. + */ +extern int mxs_dma_desc_add_list(int channel, struct list_head *head); + +/** + * mxs_dma_desc_get_cooked - Retrieve processed DMA descriptors. + * + * This function moves all the descriptors from the DMA channel's "done" list to + * the head of the given list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list that will receive the + * descriptors on the "done" list. + */ +extern int mxs_dma_get_cooked(int channel, struct list_head *head); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/dptc.h b/arch/arm/plat-mxc/include/mach/dptc.h new file mode 100644 index 000000000000..9f5ee9c6fe5d --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dptc.h @@ -0,0 +1,186 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_DPTC_H__ +#define __ASM_ARCH_MXC_DPTC_H__ + +#include <mach/dvfs_dptc_struct.h> + +/*! + * DPTC proc file system entry name + */ +#define PROC_NODE_NAME "dptc" + +int __init init_dptc_controller(dvfs_dptc_params_s *params); + +/*! + * This function enables the DPTC module. this function updates the DPTC + * thresholds, updates the PMIC, unmasks the DPTC interrupt and enables + * the DPTC module + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * + * @return 0 if DPTC module was enabled else returns -EINVAL. + */ +int start_dptc(dvfs_dptc_params_s *params); +/*! + * This function disables the DPTC module. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * + * @return 0 if DPTC module was disabled else returns -EINVAL. + */ +int stop_dptc(dvfs_dptc_params_s *params); +/*! + * This function updates the drivers current working point index. This index is + * used for access the current DTPC table entry and it corresponds to the + * current CPU working point measured by the DPTC hardware. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param new_wp New working point index value to be set. + * + */ +void set_dptc_wp(dvfs_dptc_params_s *params, int new_wp); +/*! + * This function updates the DPTC threshold registers. + * + * @param dvfs_dptc_tables_ptr pointer to the DPTC translation table. + * @param wp current wp value. + * @param freq_index translation table index of the current CPU + * frequency. + * + */ +void update_dptc_thresholds(dvfs_dptc_tables_s *dptc_tables_ptr, + int wp, int freq_index); +/*! + * This function adds a new entry to the DPTC log buffer. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param dptc_log pointer to the DPTC log buffer structure. + * @param wp value of the working point index written + * to the log buffer. + * @param freq_index value of the frequency index written to + * the log buffer. + * + * @return number of log buffer entries. + * + */ + +void add_dptc_log_entry(dvfs_dptc_params_s *params, + dptc_log_s *dptc_log, int wp, int freq_index); + +/*! + * This function updates the CPU voltage, produced by PMIC, by calling PMIC + * driver functions. + * + * @param dptc_tables_ptr pointer to the DPTC translation table. + * @param wp current wp value. + */ +void set_pmic_voltage(dvfs_dptc_tables_s *dptc_tables_ptr, int wp); + +/*! + * This function enables the DPTC reference circuits. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param rc_state each high bit specifies which + * reference circuite to enable. + * @return 0 on success, error code on failure + */ +int enable_ref_circuits(dvfs_dptc_params_s *params, unsigned char rc_state); + +/*! + * This function disables the DPTC reference circuits. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param rc_state each high bit specifies which + * reference circuite to disable + * @return 0 on success, error code on failure + */ +int disable_ref_circuits(dvfs_dptc_params_s *params, unsigned char rc_state); + +/*! + * This function is the DPTC Interrupt handler. + * This function wakes-up the dptc_workqueue_handler function that handles the + * DPTC interrupt. + */ +void dptc_irq(void); + +/*! + * This function updates the drivers current frequency index.This index is + * used for access the current DTPC table entry and it corresponds to the + * current CPU frequency (each CPU frequency has a separate index number + * according to the loaded DPTC table). + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param freq_index New frequency index value to be set. + * + * @return 0 if the frequency index was updated (the new index is a + * valid index and the DPTC module isn't active) else returns + * -EINVAL. + * + */ +int set_dptc_curr_freq(dvfs_dptc_params_s *params, unsigned int freq_index); + +#ifdef CONFIG_MXC_DVFS_SDMA +/* + * DPTC SDMA callback. + * Updates the PMIC voltage + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + */ +void dptc_sdma_callback(dvfs_dptc_params_s *params); +#endif + +/*! + * This function is called to put the DPTC in a low power state. + * + * @param pdev the device structure used to give information on which + * device to suspend (not relevant for DPTC) + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +int mxc_dptc_suspend(struct platform_device *pdev, pm_message_t state); + +/*! + * This function is called to put the DPTC in a low power state. + * + */ +void dptc_suspend(void); + +/*! + * This function is called to resume the DPTC from a low power state. + * + * @param pdev the device structure used to give information on which + * device to suspend (not relevant for DPTC) + * + * @return The function always returns 0. + */ +int mxc_dptc_resume(struct platform_device *dev); + +/*! + * This function is called to resume the DPTC from a low power state. + * + */ +void dptc_resume(void); + +/*! + * This function initializes DPTC according to turbo mode status + * + * @param status Turbo mode disable, 1 - turbo mode enabled + * + */ +void dptc_set_turbo_mode(unsigned int status); + +#endif /* __ASM_ARCH_MXC_DPTC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h new file mode 100644 index 000000000000..d24549ab97fe --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h @@ -0,0 +1,169 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file arch-mxc/dvfs_dptc_struct.h + * + * @brief MXC dvfs & dptc structure definitions file. + * + * @ingroup PM_MX27 PM_MX31 PM_MXC91321 PM_MXC91311 + */ +#ifndef __ASM_ARCH_MXC_DVFS_DPTC_STRUCT_H__ +#define __ASM_ARCH_MXC_DVFS_DPTC_STRUCT_H__ + +#include <linux/semaphore.h> +#include <mach/pm_api.h> + +/*! + * Number of entries in the DPTC log buffer + */ +#define LOG_ENTRIES 1024 + +/*! + * Log buffer Structure.\n + * This structure records the DPTC changes. \n + * This structure can be read by the user using the proc file system DPTC read entry. + */ +typedef struct { + /*! + * Index to the head of the log buffer + */ + int head; + + /*! + * Index to the tail of the log buffer + */ + int tail; + + /*! + * Mutex to allow access to the log buffer + */ + struct semaphore mutex; + + /*! + * Array of log buffer entries + */ + dptc_log_entry_s entries[LOG_ENTRIES]; +} dptc_log_s; + +/*! + * DPTC driver data structure.\n + * Holds all driver parameters and data structures. + */ +typedef struct { + /*! + * This variable holds the current frequency index + */ + int current_freq_index; + + /*! + * Boolean variable, if TRUE the DPTC module is enabled + * if FALSE the DPTC module is disabled + */ + int dptc_is_active; + + /*! + * Boolean variable, if TRUE turbo mode enable + * if FALSE turbo mode disabled + */ + int turbo_mode_active; + + /*! + * Boolean variable, if TRUE the DVFS module is enabled + * if FALSE the DPTC module is disabled + */ + int dvfs_is_active; + + /*! + * Boolean variable, if TRUE the DPTC module is suspended + */ + int suspended; + + unsigned char rc_state; + + /*! + * Pointer to the DVFS & DPTC translation table + */ + dvfs_dptc_tables_s *dvfs_dptc_tables_ptr; + + /*! + * The DPTC log buffer + */ + dptc_log_s dptc_log_buffer; + + /*! + * The DVFS log buffer + */ + unsigned char *dvfs_log_buffer; + + /*! + * The DVFS log buffer physical address (for SDMA) + */ + dma_addr_t dvfs_log_buffer_phys; + +#ifdef CONFIG_MXC_DVFS_SDMA + /*! + * SDMA channel number + */ + int sdma_channel; + + /*! + * This holds the previous working point + */ + int prev_wp; + + /*! + * Wait entry for predictive DVFS + */ + wait_queue_head_t dvfs_pred_wait; +#endif + + /*! + * This holds the current DVFS mode + */ + unsigned int dvfs_mode; + + /*! + * Log buffer read pointer + */ + unsigned char *read_ptr; + + /* + * Number of characters in log buffer + */ + int chars_in_buffer; +} dvfs_dptc_params_s; + +/*! + * This struct contains the array with values of supported frequencies in Hz + */ +typedef struct { + /* + * Number of supported states + */ + unsigned int num_of_states; + /*! + * Array of frequencies + */ + unsigned int *freqs; +} dvfs_states_table; + +/* + * if not defined define TREU and FALSE values. + */ +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif /* TRUE */ + +#endif diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h new file mode 100644 index 000000000000..71263360dc69 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h @@ -0,0 +1,100 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * USB Host side, platform-specific functionality. + */ + +#include <linux/usb/fsl_xcvr.h> +#include <mach/arc_otg.h> + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, + int port_offset); + +static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci) +{ + struct fsl_usb2_platform_data *pdata; + + pdata = ehci_to_hcd(ehci)->self.controller->platform_data; + fsl_setup_phy(ehci, pdata->phy_mode, 0); +} + +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) +{ + unsigned int temp; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) + pdata->xcvr_ops->set_host(); + + /* set host mode */ + temp = readl(hcd->regs + 0x1a8); + writel(temp | USBMODE_CM_HOST, hcd->regs + 0x1a8); +} + +/* Needed for enable PP and i2c/serial transceivers */ +static inline void +fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) +{ + u32 temp; + + /* HCSPARAMS */ + temp = readl(pdata->regs + 0x104); + /* Port Power Control */ + if (temp & HCSPARAMS_PPC) { + temp = readl(pdata->regs + FSL_SOC_USB_PORTSC1); + if (on) + temp |= PORT_POWER; + else + temp &= ~PORT_POWER; + + writel(temp, pdata->regs + FSL_SOC_USB_PORTSC1); + } + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} + +/* Set USB AHB burst length for host */ +static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd) +{ + struct fsl_usb2_platform_data *pdata; + unsigned int temp; + + pdata = hcd->self.controller->platform_data; + if (pdata->change_ahb_burst) { + temp = readl(hcd->regs + FSL_SOC_USB_SBUSCFG); + writel((temp & (~(0x7))) | pdata->ahb_burst_mode, + hcd->regs + FSL_SOC_USB_SBUSCFG); + } + + /* Increase TX fifo threshold for USB+ATA for i.mx35 2.0 */ + if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x20 */ + writel((temp & (~(0x3f << 16))) | (0x20 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + + /* Increase TX fifo threshold for USB+SD in Hostx */ + if (cpu_is_mx53() && (strcmp("DR", pdata->name))) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x08 */ + writel((temp & (~(0x3f << 16))) | (0x08 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + +} diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h new file mode 100644 index 000000000000..9bf3c07d7474 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h @@ -0,0 +1,40 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * USB Gadget side, platform-specific functionality. + */ + +#include <linux/usb/fsl_xcvr.h> + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device) + pdata->xcvr_ops->set_device(); +} + +static inline void +fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(1); +} + +static inline void +fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(0); +} diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 7a0dc5aa2479..84cd95df7b44 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -34,9 +34,12 @@ struct mxc_gpio_port { void __iomem *base; int irq; + int irq_high; int virtual_irq_start; struct gpio_chip chip; u32 both_edges; + u32 suspend_wakeup; + u32 saved_wakeup; spinlock_t lock; }; diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4ac43fc..9f6b61788d04 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -22,13 +22,34 @@ #include <asm/sizes.h> +/* + * --------------------------------------------------------------------------- + * Processor specific defines + * --------------------------------------------------------------------------- + */ +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 +#define CHIP_REV_2_2 0x22 +#define CHIP_REV_2_3 0x23 +#define CHIP_REV_3_0 0x30 +#define CHIP_REV_3_1 0x31 +#define CHIP_REV_3_2 0x32 + +#define BOARD_REV_1 0x000 +#define BOARD_REV_2 0x100 +#define BOARD_REV_3 0x200 + #define IMX_IO_ADDRESS(addr, module) \ ((void __force __iomem *) \ (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) #ifdef CONFIG_ARCH_MX5 -#include <mach/mx51.h> +#include <mach/mx5x.h> #endif #ifdef CONFIG_ARCH_MX3 @@ -37,6 +58,10 @@ #include <mach/mx35.h> #endif +#ifdef CONFIG_ARCH_MX37 +#include <mach/mx37.h> +#endif + #ifdef CONFIG_ARCH_MX2 # include <mach/mx2x.h> # ifdef CONFIG_MACH_MX21 @@ -59,6 +84,38 @@ # include <mach/mxc91231.h> #endif +#ifndef __ASSEMBLY__ +extern unsigned int system_rev; +#define board_is_rev(rev) (((system_rev & 0x0F00) == rev) ? 1 : 0) +#endif + +#ifdef CONFIG_ARCH_MX5 +#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(BOARD_REV_2)) +#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(BOARD_REV_1)) +#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(BOARD_REV_3)) +#endif + #include <mach/mxc.h> +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0x0004 + +#ifndef MXC_INT_FORCE +#define MXC_INT_FORCE -1 +#endif #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/hw_events.h b/arch/arm/plat-mxc/include/mach/hw_events.h new file mode 100644 index 000000000000..3c340fbab500 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/hw_events.h @@ -0,0 +1,65 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * hw_events.h + * include the headset/cvbs interrupt detect + */ + +#ifndef HW_EVENT_H +#define HW_EVENT_H + +#define HW_EVENT_GROUP 2 +#define HWE_DEF_PRIORITY 1 +#define HWE_HIGH_PRIORITY 0 + +typedef enum { + + HWE_PHONEJACK_PLUG = 0, + HWE_BAT_CHARGER_PLUG, + HWE_BAT_CHARGER_OVERVOLTAGE, + HWE_BAT_BATTERY_LOW, + HWE_BAT_POWER_FAILED, + HWE_BAT_CHARGER_FULL, + HWE_POWER_KEY, +} HW_EVENT_T; + +typedef enum { + + PJT_NONE = 0, + PJT_CVBS, + PJT_HEADSET, +} PHONEJACK_TYPE; + +typedef enum { + + PWRK_UNPRESS = 0, + PWRK_PRESS, +} POWERKEY_TYPE; + +typedef enum { + + UNPLUG = 0, + PLUGGED, +} PLUG_TYPE; + +struct mxc_hw_event { + unsigned int event; + int args; +}; + +#ifdef __KERNEL__ +extern int hw_event_send(int priority, struct mxc_hw_event *new_event); +#endif + +#endif /* HW_EVENT_H */ diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index b4f2de769466..0c8cc1fca4e8 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -14,29 +14,33 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -#ifdef CONFIG_ARCH_MX3 -#define __arch_ioremap __mx3_ioremap -#define __arch_iounmap __iounmap +extern void __iomem *__mxc_ioremap(unsigned long cookie, size_t size, + unsigned int mtype); -static inline void __iomem * -__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) -{ - if (mtype == MT_DEVICE) { - /* Access all peripherals below 0x80000000 as nonshared device - * but leave l2cc alone. - */ - if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || - (phys_addr >= 0x30000000 + SZ_1M))) - mtype = MT_DEVICE_NONSHARED; - } - - return __arm_ioremap(phys_addr, size, mtype); -} -#endif +#define __arch_ioremap(a, s, f) __mxc_ioremap(a, s, f) +#define __arch_iounmap __iounmap /* io address mapping macro */ #define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) +/*! + * This function is called to read a CPLD register over CSPI. + * + * @param offset number of the cpld register to be read + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int __weak spi_cpld_read(unsigned int offset); + +/*! + * This function is called to write to a CPLD register over CSPI. + * + * @param offset number of the cpld register to be written + * @param reg_val value to be written + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int __weak spi_cpld_write(unsigned int offset, unsigned int reg_val); #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index cbaed295a2bf..39f9854bcbab 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> * * This program is free software; you can redistribute it and/or @@ -554,6 +554,7 @@ enum iomux_pins { #define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) #define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) +#define MX31_PIN_BATT_LINE__GPIO2_17 IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_GPIO) #define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) @@ -696,6 +697,7 @@ enum iomux_pins { #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_2__GPIO1_2 IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO) #define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) #define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) #define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) @@ -735,7 +737,7 @@ enum iomux_pins { #define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) - +#define MX31_PIN_SRST0__GPIO3_2 IOMUX_MODE(MX31_PIN_SRST0, IOMUX_CONFIG_GPIO) /* * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h index 2a24bae1b878..03996854bbf5 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -20,6 +20,7 @@ #define __MACH_IOMUX_MX35_H__ #include <mach/iomux-v3.h> +#include <mach/irqs.h> /* * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> @@ -1263,5 +1264,10 @@ #define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_GPIO1_1 (0 * 32 + 1) +#define MX35_GPIO1_4 (0 * 32 + 4) +#define MX35_GPIO2_0 (1 * 32 + 0) + +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_IRQ_START + pin) #endif /* __MACH_IOMUX_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 000000000000..fd4a2e2f4ecc --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -0,0 +1,596 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include <mach/iomux-v3.h> + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_WVGA_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_SD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST) + +#define MX50_SD3_PAD_DAT (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SD3_PAD_CMD (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SD3_PAD_CLK (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) +#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + +#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) + +/* HP detect */ +#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC \ + IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, PAD_CTL_PKE) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, 0) + +/* SD1 */ +#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) + +/* SD2 */ +#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) + +/* SD3 */ +#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, \ + MX50_SD3_PAD_CMD) +#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, \ + MX50_SD3_PAD_CLK) +#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) + +/* OWIRE */ +#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, \ + MX50_OWIRE_PAD_CTRL) + +/* SSI */ +#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, \ + NO_PAD_CTRL) + +/* UART1 and UART2 */ +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, \ + MX50_UART_PAD_CTRL) + +/* I2C1, I2C2, I2C3 */ +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) + +/* EPDC */ +#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, \ + 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) + +/* USB */ +#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, \ + MX50_USB_PAD_CTRL) +#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, \ + MX50_USB_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, \ + MX50_USB_PAD_CTRL) + + +/* FEC */ +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, \ + MX50_FEC_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x0, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, \ + PAD_CTL_DSE_HIGH) + +/* WVGA */ +#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, \ + MX50_WVGA_PAD_CTRL) + +/* CSPI */ +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, \ + NO_PAD_CTRL) + +/* NAND */ +#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, \ + PAD_CTL_PKE | \ + PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP) +#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) + +/* Keypad */ +#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, \ + MX50_KEYPAD_CTRL) +#endif /* __MACH_IOMUX_MX53_H__ */ + diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index ab0f95d953d0..7d5be77f8bbf 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -31,6 +31,8 @@ typedef enum iomux_config { IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ } iomux_pin_cfg_t; +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + /* Pad control groupings */ #define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_DSE_HIGH) @@ -38,36 +40,80 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_HYS) #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +#define MX51_PAD_CTRL_6 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS) +#define MX51_PAD_CTRL_7 MX51_UART2_PAD_CTRL +#define MX51_PAD_CTRL_8 (PAD_CTL_HYS | PAD_CTL_PKE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) +#define MX51_PAD_CTRL_9 (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_10 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_11 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_12 (PAD_CTL_PKE | PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define MX51_PAD_CTRL_13 (PAD_CTL_PKE | PAD_CTL_PUE) + +#define MX51_SDHC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) + + + /* * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> * If <padname> or <padmode> refers to a GPIO, it is named * GPIO_<unit>_<num> see also iomux-v3.h */ -/* - * FIXME: This was converted using scripts from existing Freescale code to - * this form used upstream. Need to verify the name format. - */ - /* PAD MUX ALT INPSE PATH PADCTRL */ +/* EIM */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \ + 0x9b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \ + 0x9b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, MX51_PAD_CTRL_7) -#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART3 */ +/* UART3 */ #define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) @@ -78,80 +124,96 @@ typedef enum iomux_config { #define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, PAD_CTL_PKE) +#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) -/* REVISIT: Not sure of these values - - #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -*/ -#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, MX51_PAD_CTRL_3) + +#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12C, 1, 0x0, 0, MX51_PAD_CTRL_2) + +#define MX51_PAD_NANDF_RB5__GPIO_3_13 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) + +/* FEC */ +#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) +#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) + +#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) @@ -162,37 +224,54 @@ typedef enum iomux_config { #define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, PAD_CTL_SRE_SLOW) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, PAD_CTL_SRE_SLOW) #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART1 */ +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, MX51_PAD_CTRL_12) +#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_PAD_CTRL_8) +#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, \ + IOMUX_CONFIG_SION, \ + 0x0, 0, MX51_PAD_CTRL_8) + +/* Audio */ +#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, MX51_PAD_CTRL_10) + +/* CSPI */ +#define MX51_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_PAD_CTRL_11) +#define MX51_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_PAD_CTRL_11) + +#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) + +/* UART1 */ #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) #define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) @@ -202,19 +281,29 @@ typedef enum iomux_config { #define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) #define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) -#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, MX51_PAD_CTRL_1) +#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT1 IOMUX_PAD(0x638, 0x248, 6, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, MX51_I2C_PAD_CTRL | MX51_PAD_CTRL_13) #define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) + +/* I2C2 */ +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \ + 0x09b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \ + 0x9bc, 1, MX51_I2C_PAD_CTRL) + #define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) @@ -228,25 +317,25 @@ typedef enum iomux_config { #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, MX51_PAD_CTRL_7) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) @@ -259,76 +348,69 @@ typedef enum iomux_config { #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0, 0, NO_PAD_CTRL) + #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33C, 3, 0x9a0, 1, MX51_PAD_CTRL_7) #define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ - (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) -#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) -/* EIM */ -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) +/* SD1 */ +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +/* SD2 */ +#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1 | IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) + +#define MX51_PAD_GPIO_1_2__PWM_PWMO IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, 2 | IOMUX_CONFIG_SION, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, IOMUX_CONFIG_SION, 0x0 , 1, MX51_PAD_CTRL_6) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 000000000000..0fe881351579 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,763 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include <mach/iomux-v3.h> + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX53_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_DSE_HIGH) +#define MX53_ESAI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE |\ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX53_WEIM_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_HIGH) +#define PAD_CTRL_1 (PAD_CTL_HYS | PAD_CTL_DSE_HIGH) +#define PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) +#define PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS) +#define PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +#define PAD_CTRL_5 (PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define PAD_CTRL_6 (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define PAD_CTRL_7 (PAD_CTL_DSE_HIGH | PAD_CTL_SRE_SLOW) +#define PAD_CTRL_8 (PAD_CTL_HYS | PAD_CTL_PKE) + +#define PAD_CTRL_9 (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) + +#define PAD_CTRL_10 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define PAD_CTRL_11 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define PAD_CTRL_12 (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) +#define PAD_CTRL_13 (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | PAD_CTL_PUE |\ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) + +#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_CSI0_DATA_EN__CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D4__AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D6__AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24_UART3_TXD IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, \ + PAD_CTRL_9 | PAD_CTRL_2) +#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) + +/* NAND */ +#define MX53_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, PAD_CTRL_11) +#define MX53_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, PAD_CTRL_11) +#define MX53_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, PAD_CTRL_10) + +/* SPI */ +#define MX53_PAD_EIM_EB2__CSPI_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D19__CSPI_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 3, PAD_CTRL_1) + +/* PWM */ +#define MX53_PAD_GPIO_1__PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, NO_PAD_CTRL) + +/* Camera */ +#define MX53_PAD_CSI0_VSYNC__CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) + +/* IPU */ +#define MX53_PAD_CSI0_D12__CSI0_D12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__CSI0_D13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__CSI0_D14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__CSI0_D15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__CSI0_D16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__CSI0_D17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__CSI0_D18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__CSI0_D19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_EIM_RW__DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_EIM_DA10__DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__CSI0_D4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__CSI0_D5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D6__CSI0_D6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__CSI0_D7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D8__CSI0_D8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__CSI0_D9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__CSI0_D10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__CSI0_D11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, \ + 0, NO_PAD_CTRL) + +/* Display */ +#define MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, PAD_CTRL_5) +#define MX53_PAD_DI0_PIN15__DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, PAD_CTRL_5) +#define MX53_PAD_DI0_PIN2__DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DI0_PIN3__DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT0__DISP0_DAT0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT1__DISP0_DAT1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT2__DISP0_DAT2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT3__DISP0_DAT3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT4__DISP0_DAT4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT5__DISP0_DAT5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT6__DISP0_DAT6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT7__DISP0_DAT7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT8__DISP0_DAT8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT9__DISP0_DAT9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT10__DISP0_DAT10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT11__DISP0_DAT11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT12__DISP0_DAT12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT13__DISP0_DAT13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT14__DISP0_DAT14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT15__DISP0_DAT15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT16__DISP0_DAT16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT17__DISP0_DAT17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT18__DISP0_DAT18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT19__DISP0_DAT19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT20__DISP0_DAT20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT21__DISP0_DAT21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT22__DISP0_DAT22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT23__DISP0_DAT23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, PAD_CTRL_7) + +#define MX53_PAD_DI0_PIN15__AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, \ + 0, PAD_CTRL_6) +#define MX53_PAD_DI0_PIN3__AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DI0_PIN4__AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DI0_DISP_CLK__USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, \ + 0, PAD_CTRL_5) +#define MX53_PAD_DISP0_DAT0__USBH2_DAT0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT1__USBH2_DAT1 IOMUX_PAD(0x390, 0x64, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT2__USBH2_DAT2 IOMUX_PAD(0x394, 0x68, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT3__USBH2_DAT3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT4__USBH2_DAT4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT5__USBH2_DAT5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT6__USBH2_DAT6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT7__USBH2_DAT7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT8__PWM1 IOMUX_PAD(0x3AC, 0x80, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT9__PWM2 IOMUX_PAD(0x3B0, 0x84, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT10__USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT11__USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT12__USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT20__AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT21__AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT22__AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT23__AUD4_SSI_RXD IOMUX_PAD(0x3E8, 0xBC, 3, \ + 0x0, 0, PAD_CTRL_7) + +/* CAN*/ +#define MX53_PAD_KEY_COL2__TXCAN1 IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_KEY_ROW2__RXCAN1 IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, PAD_CTRL_3) +#define MX53_PAD_KEY_COL4__TXCAN2 IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_KEY_ROW4__RXCAN2 IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, PAD_CTRL_3) +#define MX53_PAD_ATA_RESET_B__TXCAN2 IOMUX_PAD(0x608, 0x288, 4, \ + 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_ATA_IORDY__RXCAN2 IOMUX_PAD(0x60C, 0x28C, 4, \ + 0x764, 1, PAD_CTRL_3) + +/* AUD5 */ +#define MX53_PAD_KEY_COL0__AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x0, 0, NO_PAD_CTRL) + +/* I2C1 */ +#define MX53_PAD_CSI0_D8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, PAD_CTRL_13) +#define MX53_PAD_CSI0_D9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, PAD_CTRL_13) + +/* I2C2 */ +#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, PAD_CTRL_9) +#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, PAD_CTRL_9) +#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, \ + 5 | IOMUX_CONFIG_SION, \ + 0x81C, 1, PAD_CTRL_9) + +/* I2C3 */ +#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, \ + 2 | IOMUX_CONFIG_SION, \ + 0x824, 1, PAD_CTRL_9) +#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6b4, 0x324, \ + 2 | IOMUX_CONFIG_SION, \ + 0x828, 1, PAD_CTRL_9) +#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, \ + 6 | IOMUX_CONFIG_SION, \ + 0x828, 2, PAD_CTRL_9) + +/* UART1 */ +#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, \ + 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, \ + 3, MX53_UART_PAD_CTRL) + +/* UART2 */ +#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, \ + 0x0, 0, MX53_UART_PAD_CTRL) + +/* UART3 */ +#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, \ + 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, \ + 0x884, 5, MX53_UART_PAD_CTRL) +/* CSPI */ +#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, PAD_CTRL_1) + +/* LVDS0 */ +#define MX53_PAD_LVDS0_TX3_P__LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, NO_PAD_CTRL) + +/* LVDS1 */ +#define MX53_PAD_LVDS1_TX3_P__LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) + +/* SD1 */ +#define MX53_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x674, 0x2EC, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x67C, 0x2F4, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX53_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX53_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__SD1_DATA4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__SD1_DATA5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__SD1_DATA6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__SD1_DATA7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +/* SD2 */ +#define MX53_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x688, 0x2FC, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x68C, 0x300, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__SD2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__SD2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__SD2_DAT2 IOMUX_PAD(0x694, 0x308, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__SD2_DAT3 IOMUX_PAD(0x690, 0x304, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__SD2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__SD2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__SD2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__SD2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) + +/* SD3 */ +#define MX53_PAD_ATA_DATA8__SD3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__SD3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__SD3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__SD3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__SD3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__SD3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__SD3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__SD3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__SD3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__SD3_CLK IOMUX_PAD(0x60C, 0x28C, 2, \ + 0x0, 0, MX53_SDHC_PAD_CTRL | PAD_CTL_HYS) + +/* USB */ +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) + +/* FEC */ +#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, MX53_FEC_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__FEC_REF_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_CRS_DV__FEC_CRS_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RXD1__FEC_RXD1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RXD0__FEC_RXD0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_TXD1__FEC_TXD1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_TXD0__FEC_TXD0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX53_PAD_GPIO_0__SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CLKO IOMUX_PAD(0x6A4, 0x314, 0, \ + 0x0, 0, NO_PAD_CTRL) + +/* MLB */ +#define MX53_PAD_GPIO_2__MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_GPIO_3__MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_GPIO_6__MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_FEC_MDC__MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, \ + 1, PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_FEC_TXD1__MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, \ + 1, PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) + +/* SPDIF */ +#define MX53_PAD_GPIO_19__SPDIF_TX1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, \ + PAD_CTRL_3 | PAD_CTL_PUS_100K_UP) +#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, \ + NO_PAD_CTRL) + +/* ESAI */ +#define MX53_PAD_FEC_MDIO__ESAI_SCKR IOMUX_PAD(0x5C4, 0x248, 2, \ + 0x7DC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__ESAI_FSR IOMUX_PAD(0x5C8, 0x24C, 2, \ + 0x7CC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__ESAI_HCKR IOMUX_PAD(0x5CC, 0x250, 2, \ + 0x7D4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__ESAI_SCKT IOMUX_PAD(0x5D0, 0x254, 2, \ + 0x7E0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__ESAI_FST IOMUX_PAD(0x5D4, 0x258, 2, \ + 0x7D0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__ESAI_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, \ + 0x7D8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, \ + 0x7F0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__ESAI_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, \ + 0x7EC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__ESAI_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, \ + 0x7F4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_MDC__ESAI_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, \ + 0x7F8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__ESAI_TX0 IOMUX_PAD(0x5B8, 0x240, 3, \ + 0x7E4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__ESAI_TX1 IOMUX_PAD(0x5BC, 0x244, 3, \ + 0x7E8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_GPIO_5__ESAI_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, \ + 0x7EC, 1, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_GPIO_8__ESAI_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, \ + 0x7F8, 1, MX53_ESAI_PAD_CTRL) + +/* WEIM */ +#define MX53_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x460, 0x118, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x464, 0x11C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x468, 0x120, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x46C, 0x124, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x470, 0x128, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x474, 0x12C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x478, 0x130, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x47C, 0x134, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x484, 0x13C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x488, 0x140, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x48C, 0x144, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x490, 0x148, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x494, 0x14C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x498, 0x150, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x49C, 0x154, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x4A0, 0x158, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) + +#define MX53_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__EIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x4D0, 0x184, 0, 0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x4AC, 0x160, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index f2f73d31d5ba..02e06dd7205b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -1,4 +1,5 @@ /* + * Copyright (C) 2011 Freescale Semiconductor, Inc. * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, * <armlinux@phytec.de> * @@ -54,6 +55,11 @@ struct pad_desc { unsigned select_input:3; }; +struct pad_cfg { + struct pad_desc pd; + int pad_ctrl; +}; + #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ _select_input, _pad_ctrl) \ { \ @@ -75,7 +81,9 @@ struct pad_desc { #define PAD_CTL_PKE (1 << 7) #define PAD_CTL_PUE (1 << 6) #define PAD_CTL_PUS_100K_DOWN (0 << 4) +#define PAD_CTL_PUS_360K_DOWN (0 << 4) #define PAD_CTL_PUS_47K_UP (1 << 4) +#define PAD_CTL_PUS_75K_UP (1 << 4) #define PAD_CTL_PUS_100K_UP (2 << 4) #define PAD_CTL_PUS_22K_UP (3 << 4) @@ -90,15 +98,20 @@ struct pad_desc { #define PAD_CTL_SRE_SLOW (0 << 0) /* - * setups a single pad in the iomuxer + * read/write a single pad in the iomuxer */ +int mxc_iomux_v3_get_pad(struct pad_desc *pad); int mxc_iomux_v3_setup_pad(struct pad_desc *pad); +int mxc_iomux_v3_setup_pad_ext(struct pad_cfg *pad); /* - * setups mutliple pads + * read/write mutliple pads * convenient way to call the above function with tables */ +int mxc_iomux_v3_get_multiple_pads(struct pad_desc *pad_list, unsigned count); int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads_ext(struct pad_cfg *pad_list, + unsigned count); /* * Initialise the iomux controller diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 86781f7b0c0c..1f00af566f4d 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -23,7 +23,9 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS /* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_ARCH_MX2 +#if defined CONFIG_ARCH_MX53 +#define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX1 #define MXC_GPIO_IRQS (32 * 4) @@ -35,6 +37,8 @@ #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX3 #define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX37 +#define MXC_GPIO_IRQS (32 * 3) #endif /* @@ -47,10 +51,17 @@ #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 #define MXC_BOARD_IRQS 80 +#elif defined CONFIG_MACH_MX35_3DS +#define MXC_BOARD_IRQS 32 #else #define MXC_BOARD_IRQS 16 #endif +#ifdef CONFIG_MACH_MX35_3DS +#define MXC_PSEUDO_IO_BASE (MXC_BOARD_IRQ_START + 16) +#endif + + #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) #ifdef CONFIG_MX3_IPU_IRQS @@ -69,4 +80,10 @@ extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); /* switch betwean IRQ and FIQ */ extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); +/* + * This function is used to get the AVIC Lo and Hi interrupts + * that are enabled as wake up sources to wake up the core from suspend + */ +void mxc_get_wake_irq(u32 *wake_src[]); + #endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index c4b40c35a6a1..83532f6f7c71 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -11,12 +11,18 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ +#include <asm/sizes.h> +#include <asm/page.h> + #define MX1_PHYS_OFFSET UL(0x08000000) #define MX21_PHYS_OFFSET UL(0xc0000000) #define MX25_PHYS_OFFSET UL(0x80000000) #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX37_PHYS_OFFSET UL(0x40000000) +#define MX50_PHYS_OFFSET UL(0x70000000) #define MX51_PHYS_OFFSET UL(0x90000000) +#define MX53_PHYS_OFFSET UL(0x70000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) @@ -32,8 +38,12 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET -# elif defined CONFIG_ARCH_MX5 +# elif defined CONFIG_ARCH_MX51 # define PHYS_OFFSET MX51_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX53 +# define PHYS_OFFSET MX53_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX50 +# define PHYS_OFFSET MX50_PHYS_OFFSET # endif #endif @@ -50,6 +60,39 @@ * This is required for i.MX camera driver to capture at least four VGA frames. */ #define CONSISTENT_DMA_SIZE SZ_4M +#else + +#ifdef CONFIG_ARCH_MX5 +#define CONSISTENT_DMA_SIZE (96 * SZ_1M) +#else +#define CONSISTENT_DMA_SIZE (32 * SZ_1M) +#endif + #endif /* CONFIG_MX1_VIDEO */ +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_DMA_ZONE_SIZE +#define MXC_DMA_ZONE_SIZE ((CONFIG_DMA_ZONE_SIZE * SZ_1M) >> PAGE_SHIFT) +#else +#define MXC_DMA_ZONE_SIZE ((12 * SZ_1M) >> PAGE_SHIFT) +#endif + +static inline void __arch_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + if (node != 0) + return; + /* Create separate zone to reserve memory for DMA */ + zone_size[1] = zone_size[0] - MXC_DMA_ZONE_SIZE; + zone_size[0] = MXC_DMA_ZONE_SIZE; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +#define arch_adjust_zones(node, size, holes) \ + __arch_adjust_zones(node, size, holes) + +#endif + #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h index de2128dada5c..c56268f80ff6 100644 --- a/arch/arm/plat-mxc/include/mach/mmc.h +++ b/arch/arm/plat-mxc/include/mach/mmc.h @@ -33,4 +33,24 @@ struct imxmmc_platform_data { void (*setpower)(struct device *, unsigned int vdd); }; +struct mxc_mmc_platform_data { + unsigned int ocr_mask; /* available voltages */ + unsigned int vendor_ver; + unsigned int caps; + unsigned int min_clk; + unsigned int max_clk; + unsigned int clk_flg; /* 1 clock enable, 0 not */ + unsigned int clk_always_on; /* Needed by SDIO cards and etc */ + unsigned int dll_override_en; /* Enable dll override delay line */ + unsigned int dll_delay_cells; /* The number of delay cells (0-0x3f) */ + unsigned int reserved:16; + unsigned int card_fixed:1; + unsigned int card_inserted_state:1; +/* u32 (*translate_vdd)(struct device *, unsigned int);*/ + unsigned int (*status) (struct device *); + int (*wp_status) (struct device *); + char *power_mmc; + char *clock_mmc; +}; + #endif diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 4eb6e334bda5..f66d461f2749 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -1,6 +1,26 @@ #ifndef __MACH_MX25_H__ #define __MACH_MX25_H__ +/* + * IRAM + */ +#define MX25_IRAM_BASE_ADDR 0x78000000 /* internal ram */ +#define MX25_IRAM_SIZE SZ_128K +#define IRAM_SIZE MX25_IRAM_SIZE + +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define SND_RAM_SIZE 0x10000 +#else +#define SND_RAM_SIZE 0 +#endif + +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) +#define USB_IRAM_SIZE SZ_8K +#else +#define USB_IRAM_SIZE 0 +#endif + #define MX25_AIPS1_BASE_ADDR 0x43f00000 #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX25_AIPS1_SIZE SZ_1M @@ -11,11 +31,54 @@ #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M +#define MX25_MAX_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x04000) +#define MX25_CLKCTL_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x08000) +#define MX25_ETB_SLOT4_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x0c000) +#define MX25_ETB_SLOT5_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x10000) +#define MX25_AAPE_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x14000) +#define MX25_I2C_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) +#define MX25_CAN3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_OWIRE_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x9c000) +#define MX25_ATA_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa0000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) +#define MX25_KPP_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa8000) #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) +#define MX25_AUDMUX_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xb0000) +#define MX25_ECT_A_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xb8000) +#define MX25_ECT_B_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xbc000) +#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000) +#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000) +#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_EPIT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x94000) +#define MX25_EPIT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x98000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_SCC_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xac000) +#define MX25_RNGB_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xb0000) +#define MX25_MMC_SDHC1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xb4000) +#define MX25_MMC_SDHC2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xb8000) +#define MX25_SLCDC_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc0000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) +#define MX25_SDMA_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd4000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) +#define MX25_RTIC_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xec000) +#define MX25_IIM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xf0000) +#define MX25_USBOTG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xf4000) +#define OTG_BASE_ADDR MX25_USBOTG_BASE_ADDR +#define MX25_CSI_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xf8000) +#define MX25_SRTC_BASE_ADDR (DRYICE_BASE_ADDR) #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) @@ -27,6 +90,8 @@ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ IMX_IO_ADDRESS(x, MX25_AVIC)) +#define IO_ADDRESS MX25_IO_ADDRESS + #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 @@ -34,15 +99,210 @@ #define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 #define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define LCDC_BASE_ADDR MX25_LCDC_BASE_ADDR + +#define MX25_SPBA0_BASE_ADDR 0x50000000 +#define MX25_SPBA0_BASE_ADDR_VIRT 0xfc100000 +#define MX25_SPBA0_SIZE SZ_1M + +#define MX25_CSPI3_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x04000) +#define MX25_UART4_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x08000) +#define MX25_UART3_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x0c000) +#define MX25_CSPI2_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x10000) +#define MX25_SSI2_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x14000) +#define MX25_ESAI_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x18000) +#define MX25_ATA_DMA_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x20000) +#define MX25_SIM1_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x24000) +#define MX25_SIM2_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x28000) +#define MX25_UART5_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x2c000) +#define MX25_TSC_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x30000) +#define MX25_SSI1_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x34000) +#define MX25_SPBA_CTRL_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x3c000) + +/* + * Interrupt numbers + */ +#define MX25_INT_CSPI3 0 +#define MX25_INT_GPT4 1 +#define MX25_INT_OWIRE 2 +#define MX25_INT_I2C 3 +#define MX25_INT_I2C2 4 +#define MX25_INT_UART4 5 +#define MX25_INT_RTIC 6 +#define MX25_INT_ESAI 7 +#define MX25_INT_SDHC2 8 +#define MX25_INT_SDHC1 9 +#define MX25_INT_I2C3 10 +#define MX25_INT_SSI2 11 +#define MX25_INT_SSI1 12 +#define MX25_INT_CSPI2 13 +#define MX25_INT_CSPI1 14 +#define MX25_INT_ATA 15 +#define MX25_INT_GPIO3 16 +#define MX25_INT_CSI 17 +#define MX25_INT_UART3 18 +#define MX25_INT_IIM 19 +#define MX25_INT_SIM1 20 +#define MX25_INT_SIM2 21 +#define MX25_INT_RNG 22 +#define MX25_INT_GPIO4 23 +#define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 -#define MX25_INT_FEC 57 +#define MX25_INT_PWM 26 +#define MX25_INT_EPIT2 27 +#define MX25_INT_EPIT1 28 +#define MX25_INT_GPT3 29 +#define MX25_INT_POWER_FAIL 30 +#define MX25_INT_CRM 31 +#define MX25_INT_UART2 32 #define MX25_INT_NANDFC 33 +#define MX25_INT_SDMA 34 +#define MX25_INT_USB_HTG 35 +#define MX25_INT_PWM2 36 +#define MX25_INT_USB_OTG 37 +#define MX25_INT_SLCDC 38 #define MX25_INT_LCDC 39 +#define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 +#define MX25_INT_CAN1 43 +#define MX25_INT_CAN2 44 +#define MX25_INT_UART1 45 +#define MX25_INT_TSC 46 +#define MX25_INT_ECT 48 +#define MX25_INT_SCC_SCM 49 +#define MX25_INT_SCC_SMN 50 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 +#define MX25_INT_GPT2 53 +#define MX25_INT_GPT1 54 +#define MX25_INT_WDOG 55 +#define MX25_INT_DRYICE_SEC 56 +#define MX25_INT_FEC 57 +#define MX25_INT_EXT_INT5 58 +#define MX25_INT_EXT_INT4 59 +#define MX25_INT_EXT_INT3 60 +#define MX25_INT_EXT_INT2 61 +#define MX25_INT_EXT_INT1 62 +#define MX25_INT_EXT_INT0 63 + +#define MXC_INT_LCDC MX25_INT_LCDC +#define MXC_INT_GPT MX25_INT_GPT1 +#define MXC_INT_CSI MX25_INT_CSI + +/*! + * Defines for modules using static and dynamic DMA channels + */ +#define MXC_DMA_CHANNEL_IRAM 30 +#define MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MXC_DMA_CHANNEL_SSI1_TX (MXC_DMA_CHANNEL_IRAM + 1) +#else +#define MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#endif +#define MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_TX MXC_DMA_DYNAMIC_CHANNEL + +/* + * DMA request assignments + */ +#define DMA_REQ_EXTREQ0 0 +#define DMA_REQ_CCM 1 +#define DMA_REQ_ATA_TX_END 2 +#define DMA_REQ_ATA_TX 3 +#define DMA_REQ_ATA_RX 4 +#define DMA_REQ_CSPI2_RX 6 +#define DMA_REQ_CSPI2_TX 7 +#define DMA_REQ_CSPI1_RX 8 +#define DMA_REQ_CSPI1_TX 9 +#define DMA_REQ_UART3_RX 10 +#define DMA_REQ_UART3_TX 11 +#define DMA_REQ_UART4_RX 12 +#define DMA_REQ_UART4_TX 13 +#define DMA_REQ_EXTREQ1 14 +#define DMA_REQ_EXTREQ2 15 +#define DMA_REQ_UART2_RX 16 +#define DMA_REQ_UART2_TX 17 +#define DMA_REQ_UART1_RX 18 +#define DMA_REQ_UART1_TX 19 +#define DMA_REQ_SSI2_RX1 22 +#define DMA_REQ_SSI2_TX1 23 +#define DMA_REQ_SSI2_RX0 24 +#define DMA_REQ_SSI2_TX0 25 +#define DMA_REQ_SSI1_RX1 26 +#define DMA_REQ_SSI1_TX1 27 +#define DMA_REQ_SSI1_RX0 28 +#define DMA_REQ_SSI1_TX0 29 +#define DMA_REQ_NFC 30 +#define DMA_REQ_ECT 31 +#define DMA_REQ_ESAI_RX 32 +#define DMA_REQ_ESAI_TX 33 +#define DMA_REQ_CSPI3_RX 34 +#define DMA_REQ_CSPI3_TX 35 +#define DMA_REQ_SIM2_RX 36 +#define DMA_REQ_SIM2_TX 37 +#define DMA_REQ_SIM1_RX 38 +#define DMA_REQ_SIM1_TX 39 +#define DMA_REQ_TSC_GCQ 44 +#define DMA_REQ_TSC_TCQ 45 +#define DMA_REQ_UART5_RX 46 +#define DMA_REQ_UART5_TX 47 + +#define IS_MEM_DEVICE_NONSHARED(x) 0 + +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)IO_ADDRESS(MX25_CCM_BASE_ADDR + 0x28))) +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) #define UART1_BASE_ADDR MX25_UART1_BASE_ADDR #define UART2_BASE_ADDR MX25_UART2_BASE_ADDR #endif +#define CSI_BASE_ADDR MX25_CSI_BASE_ADDR +#define AUDMUX_BASE_ADDR MX25_AUDMUX_BASE_ADDR +#define MXC_INT_ESAI MX25_INT_ESAI +#define SDMA_BASE_ADDR MX25_SDMA_BASE_ADDR +#define SCC_BASE_ADDR MX25_SCC_BASE_ADDR +#define MXC_INT_SCC_SCM MX25_INT_SCC_SCM +#define MXC_INT_SCC_SMN MX25_INT_SCC_SMN +#define DRYICE_BASE_ADDR MX25_DRYICE_BASE_ADDR +#define MXC_INT_DRYICE_NORM MX25_INT_DRYICE +#define MXC_INT_DRYICE_SEC MX25_INT_DRYICE_SEC +#define RNGB_BASE_ADDR MX25_RNGB_BASE_ADDR +#define MXC_INT_RNG MX25_INT_RNG +#define MXC_INT_USB_OTG MX25_INT_USB_OTG + +/*! + * IIM Bank info + **/ +#define MXC_IIM_BANK_START_ADDR 0x0000 +#define MXC_IIM_BANK_END_ADDR 0x007c + #endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index fb90e119c2b5..352eec09e5be 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -138,6 +138,23 @@ static inline void mx31_setup_weimcs(size_t cs, } #endif +/* + * DMA request assignments + */ +#define MX31_DMA_REQ_SDHC2 21 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_FIRI_TX 17 +#define MX31_DMA_REQ_FIRI_RX 16 +#define MX31_DMA_REQ_UART4_TX 13 +#define MX31_DMA_REQ_UART4_RX 12 +#define MX31_DMA_REQ_CSPI3_TX 11 +#define MX31_DMA_REQ_CSPI3_RX 10 +#define MX31_DMA_REQ_UART5_TX 11 +#define MX31_DMA_REQ_UART5_RX 10 +#define MX31_DMA_REQ_UART3_TX 9 +#define MX31_DMA_REQ_UART3_RX 8 +#define MX31_DMA_REQ_SIM 5 + #define MX31_INT_I2C3 3 #define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 @@ -197,6 +214,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define ARM11_PMU_IRQ MXC_INT_EVTMON + #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 526a55842ae5..9dbe06d097c8 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -1,11 +1,25 @@ #ifndef __MACH_MX35_H__ #define __MACH_MX35_H__ + +/*! + * Define this option to specify we are using the newer SDMA module. + */ +#define MXC_SDMA_V2 + /* * IRAM */ #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ #define MX35_IRAM_SIZE SZ_128K +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define SND_RAM_SIZE 0x10000 +#else +#define SND_RAM_SIZE 0 +#endif + +#define VPU_IRAM_SIZE 0 + #define MX35_L2CC_BASE_ADDR 0x30000000 #define MX35_L2CC_SIZE SZ_1M @@ -18,7 +32,7 @@ #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) @@ -39,6 +53,10 @@ #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) #define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) +#define MX35_SPDIF_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x28000) +#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) +#define MX35_ASRC_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x2C000) +#define MX35_ESAI_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x34000) #define MX35_FEC_BASE_ADDR 0x50038000 #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) @@ -52,6 +70,14 @@ #define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) #define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) #define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) +#define MX35_MMC_SDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xB4000) +#define MX35_MMC_SDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xB8000) +#define MX35_MMC_SDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xBC000) +#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xE4000) +#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xE8000) +#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xF0000) +#define MX35_OTG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xF4000) +#define MX35_MLB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xF8000) #define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) #define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) #define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) @@ -61,7 +87,6 @@ #define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) #define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_OTG_BASE_ADDR 0x53ff4000 #define MX35_ROMP_BASE_ADDR 0x60000000 #define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 @@ -123,7 +148,7 @@ #define MX35_INT_MMC_SDHC1 7 #define MX35_INT_MMC_SDHC2 8 #define MX35_INT_MMC_SDHC3 9 -#define MX35_INT_I2C 10 +#define MX35_INT_I2C1 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 #define MX35_INT_CSPI2 13 @@ -189,6 +214,35 @@ #define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 +#define MX35_DMA_REQ_ASRC_DMA6 41 +#define MX35_DMA_REQ_ASRC_DMA5 40 +#define MX35_DMA_REQ_ASRC_DMA4 39 +#define MX35_DMA_REQ_ASRC_DMA3 38 +#define MX35_DMA_REQ_ASRC_DMA2 37 +#define MX35_DMA_REQ_ASRC_DMA1 36 +#define MX35_DMA_REQ_RSVD3 35 +#define MX35_DMA_REQ_RSVD2 34 +#define MX35_DMA_REQ_ESAI_TX 33 +#define MX35_DMA_REQ_ESAI_RX 32 +#define MX35_DMA_REQ_IPU 21 +#define MX35_DMA_REQ_RSVD1 20 +#define MX35_DMA_REQ_SPDIF_TX 13 +#define MX35_DMA_REQ_SPDIF_RX 12 +#define MX35_DMA_REQ_UART3_TX 11 +#define MX35_DMA_REQ_UART3_RX 10 +#define MX35_DMA_REQ_MSHC 5 +#define MX35_DMA_REQ_DPTC 1 +#define MX35_DMA_REQ_DVFS 1 + +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS \ + (*((volatile u32 *)MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR+0x18))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR @@ -207,4 +261,10 @@ #define MXC_INT_FEC MX35_INT_FEC #endif +/*! + * IIM bank info + */ +#define MXC_IIM_BANK_START_ADDR 0x0000 +#define MXC_IIM_BANK_END_ADDR 0x007c + #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 7a356de385f5..d5953f1b074a 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -152,16 +152,7 @@ * and returning the virtual address. If the physical address is not mapped, * it returns 0xDEADBEEF */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ - ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ - ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ - ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ - ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ - ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ - 0xDEADBEEF) +#define IO_ADDRESS MX31_IO_ADDRESS /* * define the address mapping macros: in physical address order @@ -197,6 +188,35 @@ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) /* + * DMA request assignments + */ +#define MX3x_DMA_REQ_ECT 31 +#define MX3x_DMA_REQ_NFC 30 +#define MX3x_DMA_REQ_SSI1_TX1 29 +#define MX3x_DMA_REQ_SSI1_RX1 28 +#define MX3x_DMA_REQ_SSI1_TX2 27 +#define MX3x_DMA_REQ_SSI1_RX2 26 +#define MX3x_DMA_REQ_SSI2_TX1 25 +#define MX3x_DMA_REQ_SSI2_RX1 24 +#define MX3x_DMA_REQ_SSI2_TX2 23 +#define MX3x_DMA_REQ_SSI2_RX2 22 +#define MX3x_DMA_REQ_UART1_TX 19 +#define MX3x_DMA_REQ_UART1_RX 18 +#define MX3x_DMA_REQ_UART2_TX 17 +#define MX3x_DMA_REQ_UART2_RX 16 +#define MX3x_DMA_REQ_EXTREQ1 15 +#define MX3x_DMA_REQ_EXTREQ2 14 +#define MX3x_DMA_REQ_CSPI1_TX 9 +#define MX3x_DMA_REQ_CSPI1_RX 8 +#define MX3x_DMA_REQ_CSPI2_TX 7 +#define MX3x_DMA_REQ_CSPI2_RX 6 +#define MX3x_DMA_REQ_ATA_RX 4 +#define MX3x_DMA_REQ_ATA_TX 3 +#define MX3x_DMA_REQ_ATA_TX_END 2 +#define MX3x_DMA_REQ_CCM 1 +#define MX3x_DMA_REQ_EXTREQ0 0 + +/* * Interrupt numbers */ #define MX3x_INT_I2C3 3 @@ -217,6 +237,7 @@ #define MX3x_INT_EPIT1 28 #define MX3x_INT_GPT 29 #define MX3x_INT_POWER_FAIL 30 +#define MX3x_INT_DVFS 31 #define MX3x_INT_UART2 32 #define MX3x_INT_NANDFC 33 #define MX3x_INT_SDMA 34 @@ -389,17 +410,6 @@ static inline int mx31_revision(void) #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG #define MXC_INT_EXT_TV MX3x_INT_EXT_TV #define PROD_SIGNATURE MX3x_PROD_SIGNATURE -#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0 -#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1 -#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2 -#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3 -#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0 -#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1 -#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2 -#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3 -#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0 -#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1 -#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM #endif diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 5aad344d5651..45ff0c7c4afb 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -349,9 +349,9 @@ #define MX51_MXC_INT_SLIM_B 28 #define MX51_MXC_INT_SSI1 29 #define MX51_MXC_INT_SSI2 30 -#define MX51_MXC_INT_UART1 31 -#define MX51_MXC_INT_UART2 32 -#define MX51_MXC_INT_UART3 33 +#define MX51_INT_UART1 31 +#define MX51_INT_UART2 32 +#define MX51_INT_UART3 33 #define MX51_MXC_INT_RESV34 34 #define MX51_MXC_INT_RESV35 35 #define MX51_MXC_INT_CSPI1 36 diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h new file mode 100644 index 000000000000..0f5cf5426ffd --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx5x.h @@ -0,0 +1,683 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_MX5X_H__ +#define __ASM_ARCH_MXC_MX5X_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +/*! + * @file arch-mxc/mx5x.h + * @brief This file contains register definitions. + * + * @ingroup MSL_MX5 + */ + +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0x0004 + +/*! + * This option is used to set or clear the dspdma bit in the SDMA config + * register. + */ +#define MXC_SDMA_DSPDMA 0 + +/*! + * Define this option to specify we are using the newer SDMA module. + */ +#define MXC_SDMA_V2 + +/*! + * The maximum frequency that the pixel clock can be at so as to + * activate DVFS-PER. + */ +#define DVFS_MAX_PIX_CLK 54000000 + + +/* IROM + */ +#define IROM_BASE_ADDR 0x0 +#define IROM_SIZE SZ_64K + + /* + * IRAM + */ +#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define IRAM_PARTITIONS 16 +#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */ + +#if defined(CONFIG_MXC_SECURITY_SCC2) \ + || defined(CONFIG_MXC_SECURITY_SCC2_MODULE) +#define SCC_RAM_SIZE SZ_16K +#else +#define SCC_RAM_SIZE 0 +#endif + +/* + * SCC RAM BASE: last 2 partitions of IRAM on MX51, separate from IRAM on MX53 + */ +#define MX51_SCC_RAM_BASE_ADDR MX51_IRAM_BASE_ADDR +#define MX53_SCC_RAM_BASE_ADDR 0x07000000 + +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define SND_RAM_SIZE 0x6000 +#else +#define SND_RAM_SIZE 0 +#endif + +#ifdef CONFIG_MXC_VPU_IRAM +#define VPU_IRAM_SIZE 0x14000 +#else +#define VPU_IRAM_SIZE 0 +#endif + +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) +#define USB_IRAM_SIZE SZ_8K +#else +#define USB_IRAM_SIZE 0 +#endif + +/* + * NFC + */ +#define MX53_NFC_BASE_ADDR_AXI 0xF7FF0000 /* NAND flash AXI */ +#define MX51_NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ +#define NFC_BASE_ADDR_AXI_VIRT 0xF9000000 +#define NFC_AXI_SIZE SZ_64K + +/* + * Graphics Memory of GPU + */ +#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 +#define MX51_GPU_GMEM_BASE_ADDR 0x20000000 +#define GPU_BASE_ADDR 0x30000000 +#define MX53_GPU2D_BASE_ADDR 0x20000000 +#define MX51_GPU2D_BASE_ADDR 0xD0000000 + +#define MX53_TZIC_BASE_ADDR 0x0FFFC000 +#define MX51_TZIC_BASE_ADDR_T01 0x8FFFC000 +#define MX51_TZIC_BASE_ADDR 0xE0000000 +#define TZIC_SIZE SZ_16K + +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * Databahn MX50 + */ +#define MX50_DATABAHN_BASE_ADDR 0x14000000 +#define DATABAHN_CTL_REG19 0x4c +#define DATABAHN_CTL_REG20 0x50 +#define DATABAHN_CTL_REG21 0x54 +#define DATABAHN_CTL_REG22 0x58 +#define DATABAHN_CTL_REG23 0x5c +#define DATABAHN_CTL_REG42 0xa8 +#define DATABAHN_CTL_REG43 0xac +#define DATABAHN_CTL_REG55 0xdc +#define DATABAHN_CTL_REG63 0xFC +#define DATABAHN_CTL_REG73 0x124 +#define DATABAHN_CTL_REG74 0x128 +#define DATABAHN_CTL_REG75 0x12C +#define DATABAHN_CTL_REG83 0x14C +#define LOWPOWER_CONTROL_MASK 0x1F +#define LOWPOWER_AUTOENABLE_MASK 0x1F +#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16) +#define LOWPOWER_EXTERNAL_CNT_OFFSET 16 +#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8) +#define LOWPOWER_INTERNAL_CNT_OFFSET 8 +#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16) +#define LOWPOWER_REFRESH_ENABLE_OFFSET 16 +#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF +#define LOWPOWER_REFRESH_HOLD_OFFSET 0 + + +#define DEBUG_BASE_ADDR 0x40000000 +/*MX53 + 0x2000000 */ +#define DEBUG_SIZE SZ_1M +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) +#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000) +#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000) +#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000) +#define ELCDIF_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100A000) +#define EPXP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100C000) +#define DCP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100E000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) +#define QOSC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01012000) +#define PERFMON_BASE_ADDR (DEBUG_BASE_ADDR + 0x01014000) +#define SSP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01016000) +#define ANATOP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01018000) + +#define MX50_NIC_BASE_ADDR (DEBUG_BASE_ADDR + 0x08000000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x70000000 +#define SPBA0_BASE_ADDR_VIRT 0xFB100000 +#define SPBA0_SIZE SZ_1M + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define ESAI_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/*! + * defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI1 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_ESAI 0x18 +#define SPBA_SDHC3 0x20 +#define SPBA_SDHC4 0x24 +#define SPBA_SPDIF 0x28 +#define SPBA_ASRC 0x2C +#define SPBA_ATA 0x30 +#define SPBA_SLIM 0x34 +#define SPBA_HSI2C 0x38 +#define SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x73F00000 +#define AIPS1_BASE_ADDR_VIRT 0xF7E00000 +#define AIPS1_SIZE SZ_1M + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define CAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C8000) +#define CAN2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000CC000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) +#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */ + +#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) +#define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4) +/*! + * Defines for modules using static and dynamic DMA channels + */ +#define MXC_DMA_CHANNEL_IRAM 30 +#define MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SPDIF_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MXC_DMA_CHANNEL_SSI2_TX (MXC_DMA_CHANNEL_IRAM + 1) +#else /*CONFIG_SDMA_IRAM */ +#define MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#endif /*CONFIG_SDMA_IRAM */ +#define MXC_DMA_CHANNEL_SSI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCC_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCC_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_ESAI MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_ESAI MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCC_ESAI MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI1_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI1_TX1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI2_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI2_TX1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI1_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI1_TX1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI2_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI2_TX1 MXC_DMA_DYNAMIC_CHANNEL + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x83F00000 +#define AIPS2_BASE_ADDR_VIRT 0xF7D00000 +#define AIPS2_SIZE SZ_1M + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define MLB_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) /* MX51 */ +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) /* MX51 */ +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) +#define PTP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define GPU_CTRL_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 +#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define CS0_BASE_ADDR 0xB0000000 +#define CS1_BASE_ADDR 0xB8000000 +#define MX53_CS1_BASE_ADDR 0xF4000000 +#define CS2_BASE_ADDR 0xC0000000 +#define CS3_BASE_ADDR 0xC8000000 +#define CS4_BASE_ADDR 0xCC000000 +#define CS5_BASE_ADDR 0xCE000000 + +/*! + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + ((((x) >= (unsigned long)SPBA0_BASE_ADDR) && \ + ((x) < (unsigned long)SPBA0_BASE_ADDR + SPBA0_SIZE)) ? \ + SPBA0_IO_ADDRESS(x) : \ + (((x) >= (unsigned long)AIPS1_BASE_ADDR) && \ + ((x) < (unsigned long)AIPS1_BASE_ADDR + AIPS1_SIZE)) ? \ + AIPS1_IO_ADDRESS(x) : \ + (((x) >= (unsigned long)AIPS2_BASE_ADDR) && \ + ((x) < (unsigned long)AIPS2_BASE_ADDR + AIPS2_SIZE)) ? \ + AIPS2_IO_ADDRESS(x) : \ + 0xDEADBEEF) + +/* + * define the address mapping macros: in physical address order + */ +#define SPBA0_IO_ADDRESS(x) \ + (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) + +#define AIPS1_IO_ADDRESS(x) \ + (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) + +#define AIPS2_IO_ADDRESS(x) \ + (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) + +#define MX53_BASE_ADDR(x) (cpu_is_mx53() || cpu_is_mx50() ? (x) - 0x20000000 : (x)) + +#define IS_MEM_DEVICE_NONSHARED(x) 0 + +/* + * DMA request assignments + */ +#define DMA_REQ_SSI3_TX1 47 +#define DMA_REQ_SSI3_RX1 46 +#define DMA_REQ_SSI3_TX2 DMA_REQ_SSI3_TX2_MX51 +#define DMA_REQ_SSI3_TX2_MX53 45 +#define DMA_REQ_SPDIF_MX51 45 +#define DMA_REQ_SSI3_RX2 44 +#define DMA_REQ_UART3_TX_MX53 43 +#define DMA_REQ_UART3_RX_MX53 42 +#define DMA_REQ_SLIM_B_TX 42 /* MX51 */ +#define DMA_REQ_UART3_TX_MX51 44 +#define DMA_REQ_UART3_RX_MX51 43 +#define DMA_REQ_UART3_TX_MX50 43 +#define DMA_REQ_UART3_RX_MX50 42 +#define DMA_REQ_ESAI_TX 41 +#define DMA_REQ_SDHC4_MX51 41 +#define DMA_REQ_ESAI_RX 40 +#define DMA_REQ_SDHC3 40 /* MX51 */ +#define DMA_REQ_CSPI_TX 39 +#define DMA_REQ_CSPI_RX 38 +#define DMA_REQ_ASRC_DMA6 37 +#define DMA_REQ_SSI3_TX2_MX51 37 /* MX51 */ +#define DMA_REQ_ASRC_DMA5 36 +#define DMA_REQ_IPU_MX51 36 +#define DMA_REQ_ASRC_DMA4 35 +#define DMA_REQ_ASRC_DMA3 34 + +#define DMA_REQ_EPIT2 34 /* MX51 */ +#define DMA_REQ_CTI2_1 33 /* MX51 */ +#define DMA_REQ_EMI_WR_MX51 32 +#define DMA_REQ_EMI_WR_MX53 31 +#define DMA_REQ_CTI2_0 31 + +#define DMA_REQ_ASRC_DMA2 33 +#define DMA_REQ_ASRC_DMA1 32 +#define DMA_REQ_EMI_RD 30 +#define DMA_REQ_SSI1_TX1 29 +#define DMA_REQ_SSI1_RX1 28 +#define DMA_REQ_SSI1_TX2 27 +#define DMA_REQ_SSI1_RX2 26 +#define DMA_REQ_SSI2_TX1 25 +#define DMA_REQ_SSI2_RX1 24 +#define DMA_REQ_SSI2_TX2 23 +#define DMA_REQ_SSI2_RX2 22 +/* I2C2 is shared w/SDHC2 on MX53 */ +#define DMA_REQ_SDHC2 21 +/* I2C1 is shared w/SDHC1 on MX53 */ +#define DMA_REQ_SDHC1 20 +#define DMA_REQ_UART1_TX 19 +#define DMA_REQ_UART1_RX 18 + +#define DMA_REQ_UART2_TX 17 /* MX51 */ +#define DMA_REQ_UART2_RX 16 /* MX51 */ +#define DMA_REQ_GPU 15 /* MX51 */ +#define DMA_REQ_EXTREQ1 14 /* MX51 */ + +#define DMA_REQ_UART5_TX 17 +#define DMA_REQ_UART5_RX 16 +#define DMA_REQ_SPDIF_TX 15 +#define DMA_REQ_SPDIF_RX 14 +#define DMA_REQ_EXTREQ0_MX50 14 +#define DMA_REQ_EXTREQ1_MX50 15 +/* UART2 is shared w/FIRI on MX53 */ +#define DMA_REQ_FIRI_TX 13 +#define DMA_REQ_FIRI_RX 12 +#define DMA_REQ_UART2_TX_MX50 13 +#define DMA_REQ_UART2_RX_MX50 12 +#define DMA_REQ_SDHC4_MX53 11 + +#define DMA_REQ_HS_I2C_RX 11 /* MX51 */ +#define DMA_REQ_HS_I2C_TX 10 /* MX51 */ +/* SDHC3 is shared w/I2C3 on MX53 */ +#define DMA_REQ_I2C3 10 +#define DMA_REQ_HS_I2C_RX 11 /* MX51 */ +#define DMA_REQ_HS_I2C_TX 10 /* MX51 */ +#define DMA_REQ_CSPI2_TX 9 +#define DMA_REQ_CSPI2_RX 8 +#define DMA_REQ_CSPI1_TX 7 +#define DMA_REQ_CSPI1_RX 6 +#define DMA_REQ_IPU_MX53 5 +#define DMA_REQ_SLIM_B 5 /* MX51 */ +#define DMA_REQ_ATA_TX_END 4 +#define DMA_REQ_ATA_TX 3 +#define DMA_REQ_UART4_TX_MX50 3 +#define DMA_REQ_ATA_RX 2 +#define DMA_REQ_UART4_RX_MX50 2 +#define DMA_REQ_GPC 1 +#define DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MXC_INT_BASE 0 +#define MXC_INT_RESV0 0 +#define MXC_INT_MMC_SDHC1 1 +#define MXC_INT_MMC_SDHC2 2 +#define MXC_INT_MMC_SDHC3 3 +#define MXC_INT_MMC_SDHC4 4 +#define MXC_INT_DAP 5 +#define MXC_INT_SDMA 6 +#define MXC_INT_IOMUX 7 +#define MXC_INT_NFC 8 +#define MXC_INT_VPU 9 +#define MXC_INT_IPU_ERR 10 +#define MXC_INT_IPU_SYN 11 +#define MXC_INT_GPU 12 +#define MXC_INT_UART4 13 +#define MXC_INT_USB_H1 14 +#define MXC_INT_EMI 15 +#define MXC_INT_USB_H2 16 +#define MXC_INT_USB_H3 17 +#define MXC_INT_USB_OTG 18 +#define MXC_INT_SAHARA_H0 19 +#define MXC_INT_DATABAHN 19 /* MX50 */ +#define MXC_INT_SAHARA_H1 20 +#define MXC_INT_ELCDIF 20 /* MX50 */ +#define MXC_INT_SCC_SMN 21 +#define MXC_INT_EPXP 21 /* MX50 */ +#define MXC_INT_SCC_STZ 22 +#define MXC_INT_SCC_SCM 23 +#define MXC_INT_SRTC_NTZ 24 +#define MXC_INT_SRTC_TZ 25 +#define MXC_INT_RTIC 26 +#define MXC_INT_CSU 27 +#define MXC_INT_EPDC 27 /* MX50 */ +#define MXC_INT_SATA 28 +#define MXC_INT_SLIM_B 28 /* MX51 */ +#define MXC_INT_NIC 28 /* MX50 Perfmon IRQ */ +#define MXC_INT_SSI1 29 +#define MXC_INT_SSI2 30 +#define MXC_INT_UART1 31 +#define MXC_INT_UART2 32 +#define MXC_INT_UART3 33 +#define MXC_INT_RTC 34 +#define MXC_INT_PTP 35 +#define MXC_INT_CSPI1 36 +#define MXC_INT_CSPI2 37 +#define MXC_INT_CSPI 38 +#define MXC_INT_GPT 39 +#define MXC_INT_EPIT1 40 +#define MXC_INT_EPIT2 41 +#define MXC_INT_GPIO1_INT7 42 +#define MXC_INT_GPIO1_INT6 43 +#define MXC_INT_GPIO1_INT5 44 +#define MXC_INT_GPIO1_INT4 45 +#define MXC_INT_GPIO1_INT3 46 +#define MXC_INT_GPIO1_INT2 47 +#define MXC_INT_GPIO1_INT1 48 +#define MXC_INT_GPIO1_INT0 49 +#define MXC_INT_GPIO1_LOW 50 +#define MXC_INT_GPIO1_HIGH 51 +#define MXC_INT_GPIO2_LOW 52 +#define MXC_INT_GPIO2_HIGH 53 +#define MXC_INT_GPIO3_LOW 54 +#define MXC_INT_GPIO3_HIGH 55 +#define MXC_INT_GPIO4_LOW 56 +#define MXC_INT_GPIO4_HIGH 57 +#define MXC_INT_WDOG1 58 +#define MXC_INT_WDOG2 59 +#define MXC_INT_KPP 60 +#define MXC_INT_PWM1 61 +#define MXC_INT_I2C1 62 +#define MXC_INT_I2C2 63 +#define MXC_INT_I2C3 64 +#define MXC_INT_HS_I2C 64 /* MX51 */ +#define MXC_INT_MLB 65 +#define MXC_INT_ASRC 66 +#define MXC_INT_SPDIF_MX53 67 +#define MXC_INT_SIM_IPB 67 +#define MXC_INT_SIM_DAT 68 +#define MXC_INT_IIM 69 +#define MXC_INT_ANATOP1 66 /* MX50 what's it? */ +#define MXC_INT_ANATOP2 67 +#define MXC_INT_ANATOP3 68 +#define MXC_INT_ANATOP4 69 +#define MXC_INT_ATA 70 +#define MXC_INT_CCM1 71 +#define MXC_INT_CCM2 72 +#define MXC_INT_GPC1 73 +#define MXC_INT_GPC2 74 +#define MXC_INT_SRC 75 +#define MXC_INT_NM 76 +#define MXC_INT_PMU 77 +#define MXC_INT_CTI_IRQ 78 +#define MXC_INT_CTI1_TG0 79 +#define MXC_INT_CTI1_TG1 80 +#define MXC_INT_ESAI 81 +#define MXC_INT_CAN1 82 +#define MXC_INT_CAN2 83 +#define MXC_INT_MCG_ERR 81 /* MX51 */ +#define MXC_INT_MCG_TMR 82 /* MX51 */ +#define MXC_INT_MCG_FUNC 83 /* MX51 */ +#define MXC_INT_GPU2_IRQ 84 +#define MXC_INT_GPU2_BUSY 85 +#define MXC_INT_UART5 86 +#define MXC_INT_FEC 87 +#define MXC_INT_OWIRE 88 +#define MXC_INT_CTI1_TG2 89 +#define MXC_INT_SJC 90 +#define MXC_INT_SPDIF_MX51 91 +#define MXC_INT_DCP_CHAN1_3 91 /* MX50 */ +#define MXC_INT_TVE 92 +#define MXC_INT_DCP_CHAN0 92 /* MX50 */ +#define MXC_INT_FIRI 93 +#define MXC_INT_DCP_CHAN0_3_SEC 93 /* MX50 */ +#define MXC_INT_PWM2 94 +#define MXC_INT_SLIM_EXP 95 +#define MXC_INT_SSI3 96 +#define MXC_INT_EMI_BOOT 97 +#define MXC_INT_RNGB_BLOCK 97 /* MX50 */ +#define MXC_INT_CTI1_TG3 98 +#define MXC_INT_SMC_RX 99 +#define MXC_INT_VPU_IDLE 100 +#define MXC_INT_RAWNAND_BCH 100 /* MX50 */ +#define MXC_INT_EMI_NFC 101 +#define MXC_INT_GPU_IDLE 102 +#define MXC_INT_RAWNAND_GPMI 102 /* MX50 */ +#define MXC_INT_GPIO5_LOW 103 +#define MXC_INT_GPIO5_HIGH 104 +#define MXC_INT_GPIO6_LOW 105 +#define MXC_INT_GPIO6_HIGH 106 +#define MXC_INT_GPIO7_LOW 107 +#define MXC_INT_GPIO7_HIGH 108 +#define MXC_INT_MSHC 109 /* MX50 */ +#define MXC_INT_APBHDMA_CHAN0 110 +#define MXC_INT_APBHDMA_CHAN1 111 +#define MXC_INT_APBHDMA_CHAN2 112 +#define MXC_INT_APBHDMA_CHAN3 113 +#define MXC_INT_APBHDMA_CHAN4 114 +#define MXC_INT_APBHDMA_CHAN5 115 +#define MXC_INT_APBHDMA_CHAN6 116 +#define MXC_INT_APBHDMA_CHAN7 117 +#define MXC_INT_APBHDMA_CHAN8 118 +#define MXC_INT_APBHDMA_CHAN9 119 +#define MXC_INT_APBHDMA_CHAN10 120 +#define MXC_INT_APBHDMA_CHAN11 121 +#define MXC_INT_APBHDMA_CHAN12 122 +#define MXC_INT_APBHDMA_CHAN13 123 +#define MXC_INT_APBHDMA_CHAN14 124 +#define MXC_INT_APBHDMA_CHAN15 125 + +/*! + * IIM bank info + */ +#define MXC_IIM_MX51_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX51_BANK_END_ADDR 0x147c +#define MXC_IIM_MX53_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX53_BANK_END_ADDR 0x183c +#define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00 +#define MXC_IIM_MX53_MAC_ADDR_OFFSET 0x24 + +#endif /* __ASM_ARCH_MXC_MX5X_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a790bf212972..39cc8a4617e4 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * * This program is free software; you can redistribute it and/or @@ -29,8 +29,12 @@ #define MXC_CPU_MX25 25 #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 +#define MXC_CPU_MX32 32 #define MXC_CPU_MX35 35 +#define MXC_CPU_MX37 37 +#define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 #ifndef __ASSEMBLY__ @@ -109,7 +113,19 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_ARCH_MX5 +#ifdef CONFIG_ARCH_MX37 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX37 +# endif +# define cpu_is_mx37() (mxc_cpu_type == MXC_CPU_MX37) +#else +# define cpu_is_mx37() (0) +#endif + +#ifdef CONFIG_ARCH_MX51 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -121,6 +137,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx51() (0) #endif +#ifdef CONFIG_ARCH_MX53 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX53 +# endif +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) +#else +# define cpu_is_mx53() (0) +#endif + #ifdef CONFIG_ARCH_MXC91231 # ifdef mxc_cpu_type # undef mxc_cpu_type @@ -133,6 +161,137 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mxc91231() (0) #endif +#ifdef CONFIG_ARCH_MX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + +#define cpu_is_mx32() (0) + +/* + * Create inline functions to test for cpu revision + * Function name is cpu_is_<cpu name>_rev(rev) + * + * Returns: + * 0 - not the cpu queried + * 1 - cpu and revision match + * 2 - cpu matches, but cpu revision is greater than queried rev + * -1 - cpu matches, but cpu revision is less than queried rev + */ +#ifndef __ASSEMBLY__ +extern unsigned int system_rev; +#define mxc_set_system_rev(part, rev) ({ \ + system_rev = (part << 12) | rev; \ +}) +#define mxc_cpu() (system_rev >> 12) +#define mxc_cpu_rev() (system_rev & 0xFF) +#define mxc_cpu_rev_major() ((system_rev >> 4) & 0xF) +#define mxc_cpu_rev_minor() (system_rev & 0xF) +#define mxc_cpu_is_rev(rev) \ + ((mxc_cpu_rev() == rev) ? 1 : ((mxc_cpu_rev() < rev) ? -1 : 2)) +#define cpu_rev(type, rev) (cpu_is_##type() ? mxc_cpu_is_rev(rev) : 0) + +#define cpu_is_mx21_rev(rev) cpu_rev(mx21, rev) +#define cpu_is_mx25_rev(rev) cpu_rev(mx25, rev) +#define cpu_is_mx27_rev(rev) cpu_rev(mx27, rev) +#define cpu_is_mx31_rev(rev) cpu_rev(mx31, rev) +#define cpu_is_mx35_rev(rev) cpu_rev(mx35, rev) +#define cpu_is_mx37_rev(rev) cpu_rev(mx37, rev) +#define cpu_is_mx50_rev(rev) cpu_rev(mx50, rev) +#define cpu_is_mx51_rev(rev) cpu_rev(mx51, rev) +#define cpu_is_mx53_rev(rev) cpu_rev(mx53, rev) + + +#include <linux/types.h> + +extern void mxc_wd_reset(void); + +int mxc_snoop_set_config(u32 num, unsigned long base, int size); +int mxc_snoop_get_status(u32 num, u32 *statl, u32 *stath); + +struct platform_device; +void mxc_pg_enable(struct platform_device *pdev); +void mxc_pg_disable(struct platform_device *pdev); + +struct mxc_unifi_platform_data *get_unifi_plat_data(void); + +struct fsl_otp_data { + char **fuse_name; + char *regulator_name; + unsigned int fuse_num; +}; + +struct mxs_dma_plat_data { + unsigned int burst8:1; + unsigned int burst:1; + unsigned int chan_base; + unsigned int chan_num; +}; +#endif /* __ASSEMBLY__ */ + +/* DMA driver defines */ +#define MXC_IDE_DMA_WATERMARK 32 /* DMA watermark level in bytes */ +#define MXC_IDE_DMA_BD_NR (512/3/4) /* Number of BDs per channel */ + +/*! + * DPTC GP and LP ID + */ +#define DPTC_GP_ID 0 +#define DPTC_LP_ID 1 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 + +#if defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX25) +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * 32) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_IRQ_START + IOMUX_TO_GPIO(pin)) +#endif + +#ifndef __ASSEMBLY__ + +struct cpu_wp { + u32 pll_reg; + u32 pll_rate; + u32 cpu_rate; + u32 pdr0_reg; + u32 pdf; + u32 mfi; + u32 mfd; + u32 mfn; + u32 cpu_voltage; + u32 cpu_podf; +}; + +#ifndef CONFIG_ARCH_MX5 +struct cpu_wp *get_cpu_wp(int *wp); +#endif + +enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ + WAIT_UNCLOCKED, /* WAIT */ + WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ + STOP_POWER_ON, /* just STOP */ + STOP_POWER_OFF, /* STOP + SRPG */ +}; + +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode); +int tzic_enable_wake(int is_idle); +void gpio_activate_audio_ports(void); +void gpio_inactivate_audio_ports(void); +void gpio_activate_bt_audio_port(void); +void gpio_inactivate_bt_audio_port(void); +void gpio_activate_esai_ports(void); +void gpio_deactivate_esai_ports(void); + +#endif + #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) /* These are deprecated, use mx[23][157]_setup_weimcs instead. */ #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) @@ -140,6 +299,7 @@ extern unsigned int __mxc_cpu_type; #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) #endif +#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) diff --git a/arch/arm/plat-mxc/include/mach/mxc_dptc.h b/arch/arm/plat-mxc/include/mach/mxc_dptc.h new file mode 100644 index 000000000000..4eeff5d8ba72 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_dptc.h @@ -0,0 +1,111 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DPTC Dynamic Process and Temperatur Compensation (DPTC) Driver + */ + +/*! + * @file arch-mxc/mxc_dptc.h + * + * @brief This file contains the DPTC configuration structure definition. + * + * + * @ingroup DPTC + */ + +#ifndef __ASM_ARCH_MXC_DPTC_H__ +#define __ASM_ARCH_MXC_DPTC_H__ + +#ifdef __KERNEL__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/workqueue.h> +#include <linux/device.h> + +#define DPTC_WP_SUPPORTED 17 +#define DPTC_GP_WP_SUPPORTED 7 +#define DPTC_LP_WP_SUPPORTED 9 + +struct dptc_wp { + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; + u32 voltage; +}; + +/*! + * This structure is used to define the dptc controller's platform + * data. It includes the regulator name string and DPTC clock name string. + */ +struct mxc_dptc_data { + /** Regulator name string */ + char *reg_id; + /* DPTC clock name string */ + char *clk_id; + /* Control reg address */ + unsigned int dptccr_reg_addr; + /* Comparator value reg 0 address */ + unsigned int dcvr0_reg_addr; + /* GPC control reg address */ + unsigned int gpc_cntr_reg_addr; + /* DPTC interrupt status bit */ + unsigned int dptccr; + /* The number of DPTC working points */ + unsigned int dptc_wp_supported; + /* Maximum value of DPTC clock rate */ + unsigned long clk_max_val; + /* DPTC working points */ + struct dptc_wp *dptc_wp_allfreq; + /* DPTC enable bit */ + u32 dptc_enable_bit; + /* DPTC ADU bit */ + int gpc_adu; + /* VAI mask */ + u32 vai_mask; + /* VAI offset */ + int vai_offset; + /* Mask DPTC interrupt */ + u32 irq_mask; + /* DPTC no voltage change request bit */ + u32 dptc_nvcr_bit; + /* ARM interrrupt bit */ + u32 gpc_irq_bit; + /* dptc init config */ + u32 init_config; + /* dptc enable config */ + u32 enable_config; + /* dptc counting range mask */ + u32 dcr_mask; +}; + +/*! + * This function is called to put the DPTC in a low power state. + * + * @param id The DPTC device id. DPTC_GP_ID is for DPTC GP; + * DPTC_LP_ID is for DPTC LP + */ +void dptc_suspend(int id); +/*! + * This function is called to resume the DPTC from a low power state. + * + * @param id The DPTC device id. DPTC_GP_ID is for DPTC GP; + * DPTC_LP_ID is for DPTC LP + */ +void dptc_resume(int id); + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_DPTC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h new file mode 100644 index 000000000000..35aefaa87966 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver + */ + +/*! + * @file arch-mxc/mxc_dvfs.h + * + * @brief This file contains the DVFS configuration structure definition. + * + * + * @ingroup DVFS + */ + +#ifndef __ASM_ARCH_MXC_DVFS_H__ +#define __ASM_ARCH_MXC_DVFS_H__ + +#ifdef __KERNEL__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/workqueue.h> +#include <linux/device.h> + +extern void __iomem *gpc_base; +extern void __iomem *ccm_base; + +#define MXC_GPCCNTR_GPCIRQ2M (1 << 25) +#define MXC_GPCCNTR_GPCIRQ2 (1 << 24) +#define MXC_GPCCNTR_GPCIRQM (1 << 21) +#define MXC_GPCCNTR_GPCIRQ_ARM (1 << 20) +#define MXC_GPCCNTR_GPCIRQ_SDMA (0 << 20) +#define MXC_GPCCNTR_DVFS0CR (1 << 16) +#define MXC_GPCCNTR_DVFS1CR (1 << 17) +#define MXC_GPCCNTR_ADU_MASK 0x8000 +#define MXC_GPCCNTR_ADU (1 << 15) +#define MXC_GPCCNTR_STRT (1 << 14) +#define MXC_GPCCNTR_FUPD_MASK 0x2000 +#define MXC_GPCCNTR_FUPD (1 << 13) +#define MXC_GPCCNTR_HTRI_MASK 0x0000000F +#define MXC_GPCCNTR_HTRI_OFFSET 0 + +#define MXC_GPCVCR_VINC_MASK 0x00020000 +#define MXC_GPCVCR_VINC_OFFSET 17 +#define MXC_GPCVCR_VCNTU_MASK 0x00010000 +#define MXC_GPCVCR_VCNTU_OFFSET 16 +#define MXC_GPCVCR_VCNT_MASK 0x00007FFF +#define MXC_GPCVCR_VCNT_OFFSET 0 + +/* DVFS-PER */ +#define MXC_DVFSPER_PMCR0_UDCS (1 << 27) +#define MXC_DVFSPER_PMCR0_UDCS_MASK 0x8000000 +#define MXC_DVFSPER_PMCR0_ENABLE_MASK 0x10 +#define MXC_DVFSPER_PMCR0_ENABLE (1 << 4) + +#define MXC_DVFSLTR0_UPTHR_MASK 0x0FC00000 +#define MXC_DVFSLTR0_UPTHR_OFFSET 22 +#define MXC_DVFSLTR0_DNTHR_MASK 0x003F0000 +#define MXC_DVFSLTR0_DNTHR_OFFSET 16 + +#define MXC_DVFSLTR1_PNCTHR_MASK 0x0000003F +#define MXC_DVFSLTR1_PNCTHR_OFFSET 0 +#define MXC_DVFSLTR1_DNCNT_MASK 0x003FC000 +#define MXC_DVFSLTR1_DNCNT_OFFSET 14 +#define MXC_DVFSLTR1_UPCNT_MASK 0x00003FC0 +#define MXC_DVFSLTR1_UPCNT_OFFSET 6 +#define MXC_DVFSLTR1_LTBRSR 0x800000 +#define MXC_DVFSLTR1_LTBRSH 0x400000 + +#define MXC_DVFSLTR2_EMAC_MASK 0x000001FF +#define MXC_DVFSLTR2_EMAC_OFFSET 0 + +#define MXC_DVFSPMCR0_UDCS 0x8000000 +#define MXC_DVFSPMCR0_DVFEV 0x800000 +#define MXC_DVFSPMCR0_DVFIS 0x400000 +#define MXC_DVFSPMCR0_LBMI 0x200000 +#define MXC_DVFSPMCR0_LBFL 0x100000 +#define MXC_DVFSPMCR0_LBFC_MASK 0xC0000 +#define MXC_DVFSPMCR0_LBFC_OFFSET 18 +#define MXC_DVFSPMCR0_FSVAIM 0x00008000 +#define MXC_DVFSPMCR0_FSVAI_MASK 0x00006000 +#define MXC_DVFSPMCR0_FSVAI_OFFSET 13 +#define MXC_DVFSPMCR0_WFIM 0x00000400 +#define MXC_DVFSPMCR0_WFIM_OFFSET 10 +#define MXC_DVFSPMCR0_DVFEN 0x00000010 + +#define MXC_DVFSPMCR1_P1INM 0x00100000 +#define MXC_DVFSPMCR1_P1ISM 0x00080000 +#define MXC_DVFSPMCR1_P1IFM 0x00040000 +#define MXC_DVFSPMCR1_P4PM 0x00020000 +#define MXC_DVFSPMCR1_P2PM 0x00010000 + +/* DVFS CORE register offsets*/ +#define MXC_DVFSCORE_THRS 0x00 +#define MXC_DVFSCORE_COUN 0x04 +#define MXC_DVFSCORE_SIG1 0x08 +#define MXC_DVFSCORE_SIG0 0x0C +#define MXC_DVFSCORE_GPC0 0x10 +#define MXC_DVFSCORE_GPC1 0x14 +#define MXC_DVFSCORE_GPBT 0x18 +#define MXC_DVFSCORE_EMAC 0x1C +#define MXC_DVFSCORE_CNTR 0x20 +#define MXC_DVFSCORE_LTR0_0 0x24 +#define MXC_DVFSCORE_LTR0_1 0x28 +#define MXC_DVFSCORE_LTR1_0 0x2C +#define MXC_DVFSCORE_LTR1_1 0x30 +#define MXC_DVFSCORE_PT0 0x34 +#define MXC_DVFSCORE_PT1 0x38 +#define MXC_DVFSCORE_PT2 0x3C +#define MXC_DVFSCORE_PT3 0x40 + +/* + * DVFS structure + */ +struct dvfs_wp { + int upthr; + int downthr; + int panicthr; + int upcnt; + int downcnt; + int emac; +}; + +struct mxc_dvfs_platform_data { + /** Supply voltage regulator name string */ + char *reg_id; + /* CPU clock name string */ + char *clk1_id; + /* DVFS clock name string */ + char *clk2_id; + /* The base address of the DVFS core */ + void __iomem *membase; + /* The interrupt number used by the DVFS core */ + int irq; + /* GPC control reg offset */ + int gpc_cntr_offset; + /* GPC voltage counter reg offset */ + int gpc_vcr_offset; + /* CCM DVFS control reg offset */ + int ccm_cdcr_offset; + /* CCM ARM clock root reg offset */ + int ccm_cacrr_offset; + /* CCM divider handshake in-progress reg offset */ + int ccm_cdhipr_offset; + /* PREDIV mask */ + u32 prediv_mask; + /* PREDIV offset */ + int prediv_offset; + /* PREDIV value */ + int prediv_val; + /* DIV3CK mask */ + u32 div3ck_mask; + /* DIV3CK offset */ + int div3ck_offset; + /* DIV3CK value */ + int div3ck_val; + /* EMAC value */ + int emac_val; + /* Frequency increase threshold. Increase frequency change request + will be sent if DVFS counter value will be more than this value */ + int upthr_val; + /* Frequency decrease threshold. Decrease frequency change request + will be sent if DVFS counter value will be less than this value */ + int dnthr_val; + /* Panic threshold. Panic frequency change request + will be sent if DVFS counter value will be more than this value */ + int pncthr_val; + /* The amount of times the up threshold should be exceeded + before DVFS will trigger frequency increase request */ + int upcnt_val; + /* The amount of times the down threshold should be exceeded + before DVFS will trigger frequency decrease request */ + int dncnt_val; + /* Delay time in us */ + int delay_time; + /* Number of woking points supported */ + int num_wp; +}; + +/*! + * This structure is used to define the dvfs controller's platform + * data. It includes the regulator name string and DVFS clock name string. + */ +struct mxc_dvfsper_data { + /** Regulator name string */ + char *reg_id; + /* DVFS clock name string */ + char *clk_id; + /* The base address of the DVFS per */ + void __iomem *membase; + /* GPC control reg address */ + void __iomem *gpc_cntr_reg_addr; + /* GPC VCR reg address */ + void __iomem *gpc_vcr_reg_addr; + /* DVFS enable bit */ + u32 dvfs_enable_bit; + /* DVFS ADU bit */ + int gpc_adu; + /* VAI mask */ + u32 vai_mask; + /* VAI offset */ + int vai_offset; + /* Mask DVFS interrupt */ + u32 irq_mask; + /* Div3 clock offset. */ + u32 div3_offset; + /*div3 clock mask. */ + u32 div3_mask; + /*div3 clock divider */ + u32 div3_div; + /* LP voltage - high setpoint*/ + u32 lp_high; + /* LP voltage - low setpoint*/ + u32 lp_low; +}; + +/*! + * This structure is used to define the platform data of bus freq + * driver. It includes the regulator name strings. + */ + +struct mxc_bus_freq_platform_data { + /* VDDGP regulator name */ + char *gp_reg_id; + /* VCC regulator name */ + char *lp_reg_id; +}; + +#if defined(CONFIG_MXC_DVFS_PER) +extern int start_dvfs_per(void); +extern void stop_dvfs_per(void); +extern int dvfs_per_active(void); +extern int dvfs_per_divider_active(void); +extern int dvfs_per_pixel_clk_limit(void); +#else +static inline int start_dvfs_per(void) +{ + return 0; +} + +static inline void stop_dvfs_per(void) +{ +} + +static inline int dvfs_per_active(void) +{ + return 0; +} + +static inline int dvfs_per_divider_active(void) +{ + return 0; +} + +static inline int dvfs_per_pixel_clk_limit(void) +{ + return 0; +} + +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_DVFS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h new file mode 100644 index 000000000000..f36a1d27d158 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h @@ -0,0 +1,40 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxc_edid.h + * + * @brief MXC EDID tools + * + * @ingroup Framebuffer + */ + +#ifndef MXC_EDID_H +#define MXC_EDID_H + +struct mxc_edid_cfg { + bool cea_underscan; + bool cea_basicaudio; + bool cea_ycbcr444; + bool cea_ycbcr422; + bool hdmi_cap; +}; + +int mxc_edid_read(struct i2c_adapter *adp, unsigned char *edid, + struct mxc_edid_cfg *cfg, struct fb_info *fbi); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpc.h b/arch/arm/plat-mxc/include/mach/mxc_gpc.h new file mode 100644 index 000000000000..8581fcc0da28 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_gpc.h @@ -0,0 +1,74 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup LPMD Low-Level Power Management Driver + */ + +/*! + * @file arch-mxc/mxc_gpc.h + * + * @brief This file contains the chip level configuration details and + * public API declarations for GPC module + * + * @ingroup LPMD + */ + +#ifndef __ASM_ARCH_MXC_GPC_H__ +#define __ASM_ARCH_MXC_GPC_H__ + +/* AP Power Gating modules */ +typedef enum { + POWER_GATING_MODULE_AP_EMBEDDED_MEM_DEEPSLEEP, + POWER_GATING_MODULE_DISPLAY_BUFFER, + POWER_GATING_MODULE_EMI_DEEPSLEEP, + POWER_GATING_MODULE_IPU_STOP, + POWER_GATING_MODULE_L2_MEM_STOP, + POWER_GATING_MODULE_ARM_PLATFORM_STOP, +} mxc_pm_ap_power_gating_modules_t; + +/* AP Power Gating pull-down config of modules */ +typedef enum { + POWER_GATING_PULL_DOWN_DISPLAY_BUFFER, + POWER_GATING_PULL_DOWN_EMI, + POWER_GATING_PULL_DOWN_IPU, + POWER_GATING_PULL_DOWN_L2_MEM, + POWER_GATING_PULL_DOWN_ARMPLATFORM, +} mxc_pm_ap_power_gating_pulldown_t; + +/*! + * This function enables/disables the AP power gating by writing the APPCR + * register of the GPC module. + * + * @param enable Enable/Disable module power down + * 0 - disable; 1 - enable + * @param modules The desired module to be power gated + * + */ +void mxc_gpc_powergate_module(int enable, + mxc_pm_ap_power_gating_modules_t module); + +/*! + * This function enables/disables the AP power gating pull down selection of a + * module by writing the APPCR register of the GPC module. + * + * @param enable Enable/Disable module pull down + * 0 - disable; 1 - enable + * @param modules The desired module to be pulled down + * + */ +void mxc_gpc_powergate_pulldown(int enable, + mxc_pm_ap_power_gating_pulldown_t pulldown); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_iim.h b/arch/arm/plat-mxc/include/mach/mxc_iim.h new file mode 100644 index 000000000000..de98687e2565 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_iim.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX_IIM_H__ +#define __IMX_IIM_H__ + +#include <linux/mutex.h> +#include <linux/cdev.h> + +/* IIM Control Registers */ +struct iim_regs { + u32 stat; + u32 statm; + u32 err; + u32 emask; + u32 fctl; + u32 ua; + u32 la; + u32 sdat; + u32 prev; + u32 srev; + u32 preg_p; + u32 scs0; + u32 scs1; + u32 scs2; + u32 scs3; +}; + +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) + +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) + +#define IIM_PROD_REV_SH 3 +#define IIM_PROD_REV_LEN 5 +#define IIM_SREV_REV_SH 4 +#define IIM_SREV_REV_LEN 4 +#define PROD_SIGNATURE_MX51 0x1 + +#define IIM_ERR_SHIFT 8 +#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT)) +#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT)) + +struct mxc_iim_data { + const s8 *name; + u32 virt_base; + u32 reg_base; + u32 reg_end; + u32 reg_size; + u32 bank_start; + u32 bank_end; + u32 irq; + u32 action; + struct mutex mutex; + struct completion completion; + spinlock_t lock; + struct clk *clk; + struct device *dev; + void (*enable_fuse)(void); + void (*disable_fuse)(void); +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_pm.h b/arch/arm/plat-mxc/include/mach/mxc_pm.h new file mode 100644 index 000000000000..5265ba033416 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_pm.h @@ -0,0 +1,252 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup LPMD Low-Level Power Management Driver + */ + +/*! + * @file arch-mxc/mxc_pm.h + * + * @brief This file contains the chip level configuration details and + * public API declarations for CRM_AP module + * + * @ingroup LPMD + */ + +#ifndef __ASM_ARCH_MXC_PM_H__ +#define __ASM_ARCH_MXC_PM_H__ + +#define WAIT_MODE 111 +#define DOZE_MODE 112 +#define STOP_MODE 113 +#define DSM_MODE 114 +/* + * MXC91231 Break-Point Frequency below which is low frequency and + * above which is high frequency + */ +#define BREAKPT_FREQ ((long)(400000000)) + +#define GATE_STOP_WAIT 9 +#define GATE_STOP 10 + +/* + * Used for MHz conversion + */ +#define MEGA_HERTZ 1000000 + +/* + * If invalid frequency value other than the following + * CORE_133 - ARM desired to run @133MHz, LoV (1.2V) + * CORE_266 - ARM desired to run @266MHz, LoV (1.2V) + * CORE_399 - ARM desired to run @399MHz, LoV (1.2V) + * CORE_532 - ARM desired to run @133MHz, HiV (1.6V) + * are passed then this error is returned, + */ +#define ERR_FREQ_INVALID 1 + +/* + * For MXC91231 Pass1, Integer DVFS greater than 133MHz is not allowed + * due to the hardware issue + */ +#define INTEGER_DVFS_NOT_ALLOW 1 + +/* + * If PLL freq is less than desired ARM frequency during Integer + * DVFS, then return this error + */ +#define PLL_LESS_ARM_ERR 2 + +/* + * Frequency change within the same-lo voltage is not approved. + * Inorder to do Integer DFS, move to the high voltage range and + * then set LFDF and move to the low voltage range + */ +#define INT_DFS_LOW_NOT_ALLOW 3 + +/* + * If the desired AHB or IPG exceeds 133MHz or 66.5MHz respectively, + * then return this error + */ +#define AHB_IPG_EXCEED_LIMIT 4 + +/* + * If the desired ARM frequency is too low to get by PLL scaling + * and the mxc_pm_pllscale API is called, return this error: + */ +#define PLL_DVFS_FREQ_TOO_LOW 5 + +/* + * Invalid frequencies requested + */ +#define MXC_PM_INVALID_PARAM 6 + +/* + * If AHB and/or IPG frequencies are greater than maximum allowed + */ +#define FREQ_OUT_OF_RANGE 2 + +/* + * If AHB and/or IPG frequencies are other than 100 or 50Mhz + */ +#define BUS_FREQ_INVALID 2 + +/* + * If MAX_PDF is greater than max value (8) then return this error + */ +#define AHB_MAX_DIV_ERR 3 + +/* + * If IPG_PDF is greater than max value (2) then return this error + */ +#define IPG_MAX_DIV_ERR 4 + +/* + * If ARM freq is out of range i.e., less than 133 or greater than + * 399 then return this error + */ +#define INVALID_ARM_FREQ 5 + +/* + * This file includes all platform APIs. Some of the APIs are not + * appicable to some platforms. So, this error is used to indicate + * that a particular API is not available + */ +#define MXC_PM_API_NOT_SUPPORTED 6 + +/* + * Error when frequency scaling is attempted while switch between MPLL and + * TPLL is in progress on MXC91321 + */ +#define ERR_DFSP_SWITCH 2 + +/*! + * Additional define for stop mode + */ +#define PM_SUSPEND_STOP ((__force suspend_state_t) 2) + +/*! + * CKOH pins configuration + */ +#define CKOH_AP_SEL 1 +#define CKOH_AHB_SEL 2 +#define CKOH_IP_SEL 3 + +/*! + * Defines for Stop and DSM mode acknowledgements + */ +#define MXC_PM_LOWPWR_ACK_SDMA 0x01 +#define MXC_PM_LOWPWR_ACK_IPU 0x02 +#define MXC_PM_LOWPWR_ACK_MAX 0x04 +#define MXC_PM_LOWPWR_ACK_MQSPI 0x08 +#define MXC_PM_LOWPWR_ACK_USB 0x10 +#define MXC_PM_LOWPWR_ACK_RTIC 0x20 + +/* + * PMIC configuration + */ +#define MXC_PMIC_1_2_VOLT 0xC +#define MXC_PMIC_1_6_VOLT 0x1C +#define MXC_PMIC_1_0_VOLT 0x4 +#if defined(CONFIG_ARCH_MXC91321) || defined(CONFIG_ARCH_MXC91231) +#define MXC_PMIC_DVS_SPEED 0x1 +#else +#define MXC_PMIC_DVS_SPEED 0x3 +#endif + +/*! + * Implementing Level 1 CRM Gate Control. Level 2 gate control + * is provided at module level using LPMD registers + * + * @param group The desired clock gate control register bits. + * Possible values are 0 through 6 + * @param opt The desired option requesting clock to run during stop + * and wait modes or just during the stop mode. Possible + * values are GATE_STOP_WAIT and GATE_STOP. + * + */ +void mxc_pm_clockgate(int group, int opt); + +/*! + * Implementing steps required to transition to low-power modes + * + * @param mode The desired low-power mode. Possible values are, + * WAIT_MODE, STOP_MODE or DSM_MODE + * + */ +void mxc_pm_lowpower(int mode); + +/*! + * Enables acknowledgement from module when entering stop or DSM mode. + * + * @param ack The desired module acknowledgement to enable. + * + */ +void mxc_pm_lp_ack_enable(int ack); + +/*! + * Disables acknowledgement from module when entering stop or DSM mode. + * + * @param ack The desired module acknowledgement to disable. + * + */ +void mxc_pm_lp_ack_disable(int ack); + +/*! + * Implementing steps required to set Integer Scaling + * + * @param armfreq The desired ARM frequency. AHB and IP + * frequency are changed depending on ARM + * frequency and the divider values. + * @param ahbfreq The desired AHB frequency + * @param ipfreq The desired IP frequency + * + * @return Returns 0 on success or + * Returns -PLL_LESS_ARM_ERR if pllfreq is less than + * desired core freq + */ +int mxc_pm_intscale(long armfreq, long ahbfreq, long ipfreq); + +/*! + * To calculate MFI, MFN, MFD values. Using this the output frequency + * whose value is calculated using, + * 2 * REF_FREQ * (MF / PDF), where + * REF_FREQ is 26 Mhz + * MF = MFI + (MFN + MFD) + * PDF is assumed to be 1 + * + * @param armfreq The desired ARM frequency + * @param ahbfreq The desired AHB frequency + * @param ipfreq The desired IP frequency + * + * @return Returns 0 on success or + * Returns -1 on error + */ +int mxc_pm_pllscale(long armfreq, long ahbfreq, long ipfreq); + +/*! + * To change AP core frequency and/or voltage suitably + * + * @param armfreq The desired ARM frequency + * @param ahbfreq The desired AHB frequency + * @param ipfreq The desired IP frequency + * + * @return Returns -ERR_FREQ_INVALID on failure + * Returns 0 on success + */ +int mxc_pm_dvfs(unsigned long armfreq, long ahbfreq, long ipfreq); + +extern void mxc_pm_arch_entry(void *entry, u32 size); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/mxc_rfkill.h index 383f1c04df06..3a3d41496e15 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ b/arch/arm/plat-mxc/include/mach/mxc_rfkill.h @@ -1,22 +1,28 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved - * + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * + * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ -#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ +#ifndef MXC_RFKILL_H +#define MXC_RFKILL_H + +struct mxc_bt_rfkill_platform_data { + int (*power_change) (int status); +}; -#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_scc.h b/arch/arm/plat-mxc/include/mach/mxc_scc.h new file mode 100644 index 000000000000..b803d1683fb4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_scc.h @@ -0,0 +1,45 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file arch-mxc/mxc_scc.h + * + * @brief This is intended to be the file which contains all of code or changes + * needed to port the driver. + * + * @ingroup MXCSCC + */ + +#ifndef __ASM_ARCH_MXC_SCC_H__ +#define __ASM_ARCH_MXC_SCC_H__ + +#include <mach/hardware.h> + +/*! + * Expected to come from platform header files. + * This symbol must be the address of the SCC + */ +#define SCC_BASE SCC_BASE_ADDR + +/*! + * This must be the interrupt line number of the SCM interrupt. + */ +#define INT_SCC_SCM MXC_INT_SCC_SCM + +/*! + * if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of + * the SMN interrupt. + */ +#define INT_SCC_SMN MXC_INT_SCC_SMN + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h new file mode 100644 index 000000000000..a26eeed628d1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h @@ -0,0 +1,158 @@ +/* + * mxc_timer.h + * + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#ifndef __PLAT_MXC_TIMER_H +#define __PLAT_MXC_TIMER_H + +#include <linux/clk.h> +#include <mach/hardware.h> + +#ifdef CONFIG_ARCH_IMX +#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) +#define TIMER_INTERRUPT TIM1_INT + +#define TCTL_VAL TCTL_CLK_PCLK1 +#define TCTL_IRQEN (1<<4) +#define TCTL_FRR (1<<8) +#define TCTL_CLK_PCLK1 (1<<1) +#define TCTL_CLK_PCLK1_4 (2<<1) +#define TCTL_CLK_TIN (3<<1) +#define TCTL_CLK_32 (4<<1) + +#define MXC_TCTL 0x00 +#define MXC_TPRER 0x04 +#define MXC_TCMP 0x08 +#define MXC_TCR 0x0c +#define MXC_TCN 0x10 +#define MXC_TSTAT 0x14 +#define TSTAT_CAPT (1<<1) +#define TSTAT_COMP (1<<0) + +static inline void gpt_irq_disable(void) +{ + unsigned int tmp; + + tmp = __raw_readl(TIMER_BASE + MXC_TCTL); + __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); +} + +static inline void gpt_irq_enable(void) +{ + __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, + TIMER_BASE + MXC_TCTL); +} + +static void gpt_irq_acknowledge(void) +{ + __raw_writel(0, TIMER_BASE + MXC_TSTAT); +} + +#elif defined(CONFIG_ARCH_MX2) +#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) +#define TIMER_INTERRUPT MXC_INT_GPT1 + +#define MXC_TCTL 0x00 +#define TCTL_VAL TCTL_CLK_PCLK1 +#define TCTL_CLK_PCLK1 (1<<1) +#define TCTL_CLK_PCLK1_4 (2<<1) +#define TCTL_IRQEN (1<<4) +#define TCTL_FRR (1<<8) +#define MXC_TPRER 0x04 +#define MXC_TCMP 0x08 +#define MXC_TCR 0x0c +#define MXC_TCN 0x10 +#define MXC_TSTAT 0x14 +#define TSTAT_CAPT (1<<1) +#define TSTAT_COMP (1<<0) + +static inline void gpt_irq_disable(void) +{ + unsigned int tmp; + + tmp = __raw_readl(TIMER_BASE + MXC_TCTL); + __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); +} + +static inline void gpt_irq_enable(void) +{ + __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, + TIMER_BASE + MXC_TCTL); +} + +static void gpt_irq_acknowledge(void) +{ + __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT); +} + +#else +#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) +#define TIMER_INTERRUPT MXC_INT_GPT + +#define MXC_TCTL 0x00 +#define TCTL_VAL (TCTL_CLK_HIGH_FREQ | TCTL_WAITEN) +#define TCTL_CLK_IPG (1<<6) +#define TCTL_CLK_HIGH_FREQ (2<<6) +#define TCTL_FRR (1<<9) +#define TCTL_WAITEN (1<<3) + +#define MXC_TPRER 0x04 +#define MXC_TSTAT 0x08 +#define TSTAT_OF1 (1<<0) +#define TSTAT_OF2 (1<<1) +#define TSTAT_OF3 (1<<2) +#define TSTAT_IF1 (1<<3) +#define TSTAT_IF2 (1<<4) +#define TSTAT_ROV (1<<5) +#define MXC_IR 0x0c +#define MXC_TCMP 0x10 +#define MXC_TCMP2 0x14 +#define MXC_TCMP3 0x18 +#define MXC_TCR 0x1c +#define MXC_TCN 0x24 + +static inline void gpt_irq_disable(void) +{ + __raw_writel(0, TIMER_BASE + MXC_IR); +} + +static inline void gpt_irq_enable(void) +{ + __raw_writel(1<<0, TIMER_BASE + MXC_IR); +} + +static inline void gpt_irq_acknowledge(void) +{ + __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT); +} +#endif /* CONFIG_ARCH_MX3 */ + +#define TCTL_SWR (1<<15) +#define TCTL_CC (1<<10) +#define TCTL_OM (1<<9) +#define TCTL_CAP_RIS (1<<6) +#define TCTL_CAP_FAL (2<<6) +#define TCTL_CAP_RIS_FAL (3<<6) +#define TCTL_CAP_ENA (1<<5) +#define TCTL_TEN (1<<0) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_uart.h b/arch/arm/plat-mxc/include/mach/mxc_uart.h new file mode 100644 index 000000000000..a2669ecd542a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_uart.h @@ -0,0 +1,275 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup UART Universal Asynchronous Receiver Transmitter (UART) Driver + */ + +/*! + * @file arch-mxc/mxc_uart.h + * + * @brief This file contains the UART configuration structure definition. + * + * + * @ingroup UART + */ + +#ifndef __ASM_ARCH_MXC_UART_H__ +#define __ASM_ARCH_MXC_UART_H__ + +#ifdef __KERNEL__ + +#include <linux/serial_core.h> +#include <mach/dma.h> + +/* + * The modes of the UART ports + */ +#define MODE_DTE 0 +#define MODE_DCE 1 +/* + * Is the UART configured to be a IR port + */ +#define IRDA 0 +#define NO_IRDA 1 + +/*! + * This structure is used to store the the physical and virtual + * addresses of the UART DMA receive buffer. + */ +typedef struct { + /*! + * DMA Receive buffer virtual address + */ + char *rx_buf; + /*! + * DMA Receive buffer physical address + */ + dma_addr_t rx_handle; +} mxc_uart_rxdmamap; + +/*! + * This structure is a way for the low level driver to define their own + * \b uart_port structure. This structure includes the core \b uart_port + * structure that is provided by Linux as an element and has other + * elements that are specifically required by this low-level driver. + */ +typedef struct { + /*! + * The port structure holds all the information about the UART + * port like base address, and so on. + */ + struct uart_port port; + /*! + * Flag to determine if the interrupts are muxed. + */ + int ints_muxed; + /*! + * Array that holds the receive and master interrupt numbers + * when the interrupts are not muxed. + */ + int irqs[2]; + /*! + * Flag to determine the DTE/DCE mode. + */ + int mode; + /*! + * Flag to hold the IR mode of the port. + */ + int ir_mode; + /*! + * Flag to enable/disable the UART port. + */ + int enabled; + /*! + * Flag to indicate if we wish to use hardware-driven hardware + * flow control. + */ + int hardware_flow; + /*! + * Holds the threshold value at which the CTS line is deasserted in + * case we use hardware-driven hardware flow control. + */ + unsigned int cts_threshold; + /*! + * Flag to enable/disable DMA data transfer. + */ + int dma_enabled; + /*! + * Holds the DMA receive buffer size. + */ + int dma_rxbuf_size; + /*! + * DMA Receive buffers information + */ + mxc_uart_rxdmamap *rx_dmamap; + /*! + * DMA RX buffer id + */ + int dma_rxbuf_id; + /*! + * DMA Transmit buffer virtual address + */ + char *tx_buf; + /*! + * DMA Transmit buffer physical address + */ + dma_addr_t tx_handle; + /*! + * Holds the RxFIFO threshold value. + */ + unsigned int rx_threshold; + /*! + * Holds the TxFIFO threshold value. + */ + unsigned int tx_threshold; + /*! + * Information whether this is a shared UART + */ + unsigned int shared; + /*! + * Clock id for UART clock + */ + struct clk *clk; + /*! + * Information whether RXDMUXSEL must be set or not for IR port + */ + int rxd_mux; + int ir_tx_inv; + int ir_rx_inv; + /*! + * DMA ID for transmit + */ + mxc_dma_device_t dma_tx_id; + /*! + * DMA ID for receive + */ + mxc_dma_device_t dma_rx_id; +} uart_mxc_port; + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ + +/* Bit definations of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definations of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definations of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definations of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definations of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definations of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definations of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definations of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 +#define MXC_UARTUSR2_BRCD 0x0004 + +/* Bit definations of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_UART_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h new file mode 100644 index 000000000000..36165f4268b6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h @@ -0,0 +1,94 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file arch-mxc/mxc_vpu.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __ASM_ARCH_MXC_VPU_H__ +#define __ASM_ARCH_MXC_VPU_H__ + +#include <linux/fs.h> + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + u32 cpu_addr; /* cpu address to free the dma mem */ + u32 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_VL2CC_FLUSH _IO(VPU_IOC_MAGIC, 5) +#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7) +#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8) +#define VPU_IOC_GET_PIC_PARA_ADDR _IO(VPU_IOC_MAGIC, 9) +#define VPU_IOC_GET_USER_DATA_ADDR _IO(VPU_IOC_MAGIC, 10) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) + +#define BIT_CODE_RUN 0x000 +#define BIT_CODE_DOWN 0x004 +#define BIT_INT_CLEAR 0x00C +#define BIT_INT_STATUS 0x010 + +#define BIT_WORK_CTRL_BUF_BASE 0x100 +#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) +#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0) +#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1) +#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2) +#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3) +#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) +#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) + +#define BIT_RESET_CTRL 0x11C + +/* i could be 0, 1, 2, 3 */ +#define BIT_RD_PTR_BASE 0x120 +#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8) +#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4) + +/* i could be 0, 1, 2, 3 */ +#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140) +#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4) + +#define BIT_BUSY_FLAG 0x160 +#define BIT_RUN_COMMAND 0x164 +#define BIT_INT_ENABLE 0x170 + +#define BITVAL_PIC_RUN 8 + +#define VPU_SLEEP_REG_VALUE 10 +#define VPU_WAKE_REG_VALUE 11 + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/pcmcia.h b/arch/arm/plat-mxc/include/mach/pcmcia.h new file mode 100644 index 000000000000..8426f15031d9 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pcmcia.h @@ -0,0 +1,218 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PCMCIA_H__ +#define __ASM_ARCH_MXC_PCMCIA_H__ + +#include <mach/hardware.h> + +#define WINDOW_SIZE 0x1000000 /* The size of a window: 16M */ +#define PCMCIA_WINDOWS 5 /* How many windows / socket */ +#define SOCKET_NO 1 /* How many sockets */ + +#define ATTRIBUTE_MEMORY_WINDOW 0 +#define IO_WINDOW 1 +#define COMMON_MEMORY_WINDOW 2 + +/* + * PCMCIA socket + */ +#define PCMCIAPrtSp WINDOW_SIZE /* PCMCIA window size */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (PCMCIA_MEM_BASE_ADDR + (Nb) * PCMCIASp) + +#define _PCMCIAAttr(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ + +#define _PCMCIAIO(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + (IO_WINDOW) * PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + (COMMON_MEMORY_WINDOW) * PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +/* + * Module: PCMCIA, Addr Range: 0xB8004000 - 0xB8004FFF, Size: 4 Kbyte + */ +#define PCMCIA_BASE_ADDR (PCMCIA_CTL_BASE_ADDR) /* PCMCIA Base Address */ +#define PCMCIA_IO_ADDR(x) (*(volatile u32 *)PCMCIA_IO_ADDRESS(x)) + +#define _reg_PCMCIA_PIPR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x00) /* PCMCIA input pins register */ +#define _reg_PCMCIA_PSCR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x04) /* PCMCIA Status Changed Register */ +#define _reg_PCMCIA_PER PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x08) /* PCMCIA Enable Register */ + +/* win: 0-4 */ +#define _reg_PCMCIA_PBR(win) PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x0C + 4 * (win)) /* PCMCIA Base Register x */ +#define _reg_PCMCIA_POR(win) PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x28 + 4 * (win)) /* PCMCIA Option Register x */ +#define _reg_PCMCIA_POFR(win) PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x44 + 4 * (win)) /* PCMCIA Offset Register x */ + +#define _reg_PCMCIA_PGCR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x60) /* PCMCIA General Control Register */ +#define _reg_PCMCIA_PGSR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x64) /* PCMCIA General Status Register */ + +/* PCMCIA_PIPR - PCMCIA Input Pins Register - fields */ +#define PCMCIA_PIPR_POWERON (1 << 8) /* card indicates "power on" */ +#define PCMCIA_PIPR_RDY (1 << 7) /* card is ready */ +#define PCMCIA_PIPR_BVD2 (1 << 6) /* battery voltage 2/SPKR in */ +#define PCMCIA_PIPR_BVD1 (1 << 5) /* battery voltage 1/STSCHG */ +#define PCMCIA_PIPR_CD (3 << 3) /* card detect 1 and 2 */ +#define PCMCIA_PIPR_WP (1 << 2) /* write protect switch enabled */ +#define PCMCIA_PIPR_VS (3 << 0) /* voltage sense bits */ +#define PCMCIA_PIPR_VS_5V (1 << 0) /* 5v */ + +/* PCMCIA_PSCR - PCMCIA Status Change Register - fields */ +#define PCMCIA_PSCR_POWC (1 << 11) /* */ +#define PCMCIA_PSCR_RDYR (1 << 10) /* */ +#define PCMCIA_PSCR_RDYF (1 << 9) /* */ +#define PCMCIA_PSCR_RDYH (1 << 8) /* */ +#define PCMCIA_PSCR_RDYL (1 << 7) /* */ +#define PCMCIA_PSCR_BVDC2 (1 << 6) /* */ +#define PCMCIA_PSCR_BVDC1 (1 << 5) /* */ +#define PCMCIA_PSCR_CDC2 (1 << 4) /* */ +#define PCMCIA_PSCR_CDC1 (1 << 3) /* */ +#define PCMCIA_PSCR_WPC (1 << 2) /* */ +#define PCMCIA_PSCR_VSC2 (1 << 1) /* */ +#define PCMCIA_PSCR_VSC1 (1 << 0) /* */ + +/* PCMCIA_PER - PCMCIA Enable Register - fields */ +#define PCMCIA_PER_ERRINTEN (1 << 12) /* error interrupt enable */ +#define PCMCIA_PER_POWERONEN (1 << 11) /* power on interrupt enable */ +#define PCMCIA_PER_RDYRE (1 << 10) /* RDY/nIREQ pin rising edge */ +#define PCMCIA_PER_RDYFE (1 << 9) /* RDY/nIREQ pin falling edge */ +#define PCMCIA_PER_RDYHE (1 << 8) /* RDY/nIREQ pin high */ +#define PCMCIA_PER_RDYLE (1 << 7) /* RDY/nIREQ pin low */ +#define PCMCIA_PER_BVDE2 (1 << 6) /* battery voltage 2/SPKR in */ +#define PCMCIA_PER_BVDE1 (1 << 5) /* battery voltage 1/STSCHG */ +#define PCMCIA_PER_CDE2 (1 << 4) /* card detect 2 */ +#define PCMCIA_PER_CDE1 (1 << 3) /* card detect 1 */ +#define PCMCIA_PER_WPE (1 << 2) /* write protect */ +#define PCMCIA_PER_VSE2 (1 << 1) /* voltage sense 2 */ +#define PCMCIA_PER_VSE1 (1 << 0) /* voltage sense 1 */ + +/* PCMCIA_POR[0-4] - PCMCIA Option Registers 0-4 - fields */ +#define PCMCIA_POR_PV (1 << 29) /* set iff bank is valid */ +#define PCMCIA_POR_WPEN (1 << 28) /* write protect (WP) input signal is enabled */ +#define PCMCIA_POR_WP (1 << 27) /* write protected */ + +#define PCMCIA_POR_PRS_SHIFT (25) +#define PCMCIA_POR_PRS(x) (((x) & 0x3) << PCMCIA_POR_PRS_SHIFT) +#define PCMCIA_POR_PRS_MASK PCMCIA_POR_PRS(3) /* PCMCIA region select */ +#define PCMCIA_POR_PRS_COMMON (0) /* values of POR_PRS field */ +#define PCMCIA_POR_PRS_TRUE_IDE (1) +#define PCMCIA_POR_PRS_ATTRIBUTE (2) +#define PCMCIA_POR_PRS_IO (3) + +#define PCMCIA_POR_PPS_8 (1 << 24) /* PCMCIA Port size = 8bits */ +#define PCMCIA_POR_PPS_16 (0 << 24) /* PCMCIA Port size = 16bits */ + +#define PCMCIA_POR_PSL_SHIFT (17) /* strobe length */ +#define PCMCIA_POR_PSL(x) (((x) & 0x7F) << PCMCIA_POR_PSL_SHIFT) +#define PCMCIA_POR_PSL_MASK PCMCIA_POR_PSL(0x7f) + +#define PCMCIA_POR_PSST_SHIFT (11) /* strobe setup time */ +#define PCMCIA_POR_PSST(x) (((x) & 0x3F) << PCMCIA_POR_PSST_SHIFT) +#define PCMCIA_POR_PSST_MASK PCMCIA_POR_PSST(0x3f) + +#define PCMCIA_POR_PSHT_SHIFT (5) /* strobe hold time */ +#define PCMCIA_POR_PSHT(x) (((x) & 0x3F) << PCMCIA_POR_PSHT_SHIFT) +#define PCMCIA_POR_PSHT_MASK PCMCIA_POR_PSHT(0x3f) + +#define PCMCIA_POR_BSIZE_SHIFT (0) /* bank size */ +#define PCMCIA_POR_BSIZE(x) (((x) & 0x1F) << PCMCIA_POR_BSIZE_SHIFT) +#define PCMCIA_POR_BSIZE_MASK PCMCIA_POR_BSIZE(0x1F) + +/* some handy BSIZE values */ +#define POR_BSIZE_1 PCMCIA_POR_BSIZE(0x00) +#define POR_BSIZE_2 PCMCIA_POR_BSIZE(0x01) +#define POR_BSIZE_4 PCMCIA_POR_BSIZE(0x03) +#define POR_BSIZE_8 PCMCIA_POR_BSIZE(0x02) +#define POR_BSIZE_16 PCMCIA_POR_BSIZE(0x06) +#define POR_BSIZE_32 PCMCIA_POR_BSIZE(0x07) +#define POR_BSIZE_64 PCMCIA_POR_BSIZE(0x05) +#define POR_BSIZE_128 PCMCIA_POR_BSIZE(0x04) +#define POR_BSIZE_256 PCMCIA_POR_BSIZE(0x0C) +#define POR_BSIZE_512 PCMCIA_POR_BSIZE(0x0D) +#define POR_BSIZE_1K PCMCIA_POR_BSIZE(0x0F) +#define POR_BSIZE_2K PCMCIA_POR_BSIZE(0x0E) + +#define POR_BSIZE_4K PCMCIA_POR_BSIZE(0x0A) +#define POR_BSIZE_8K PCMCIA_POR_BSIZE(0x0B) +#define POR_BSIZE_16K PCMCIA_POR_BSIZE(0x09) +#define POR_BSIZE_32K PCMCIA_POR_BSIZE(0x08) +#define POR_BSIZE_64K PCMCIA_POR_BSIZE(0x18) +#define POR_BSIZE_128K PCMCIA_POR_BSIZE(0x19) +#define POR_BSIZE_256K PCMCIA_POR_BSIZE(0x1B) +#define POR_BSIZE_512K PCMCIA_POR_BSIZE(0x1A) +#define POR_BSIZE_1M PCMCIA_POR_BSIZE(0x1E) +#define POR_BSIZE_2M PCMCIA_POR_BSIZE(0x1F) +#define POR_BSIZE_4M PCMCIA_POR_BSIZE(0x1D) +#define POR_BSIZE_8M PCMCIA_POR_BSIZE(0x1C) +#define POR_BSIZE_16M PCMCIA_POR_BSIZE(0x14) +#define POR_BSIZE_32M PCMCIA_POR_BSIZE(0x15) +#define POR_BSIZE_64M PCMCIA_POR_BSIZE(0x17) + +/* Window size */ +#define POR_1 0x1 +#define POR_2 0x2 +#define POR_4 0x4 +#define POR_8 0x8 +#define POR_16 0x10 +#define POR_32 0x20 +#define POR_64 0x40 +#define POR_128 0x80 +#define POR_256 0x100 +#define POR_512 0x200 + +#define POR_1K 0x400 +#define POR_2K 0x800 +#define POR_4K 0x1000 +#define POR_8K 0x2000 +#define POR_16K 0x4000 +#define POR_32K 0x8000 +#define POR_64K 0x10000 +#define POR_128K 0x20000 +#define POR_256K 0x40000 +#define POR_512K 0x80000 + +#define POR_1M 0x100000 +#define POR_2M 0x200000 +#define POR_4M 0x400000 +#define POR_8M 0x800000 +#define POR_16M 0x1000000 +#define POR_32M 0x2000000 +#define POR_64M 0x4000000 + +/* PCMCIA_PGCR - PCMCIA General Control Register - fields */ +#define PCMCIA_PGCR_LPMEN (1 << 3) /* Low power Mode Enable */ +#define PCMCIA_PGCR_SPKREN (1 << 2) /* SPKROUT routing enable */ +#define PCMCIA_PGCR_POE (1 << 1) /* Controller out enable */ +#define PCMCIA_PGCR_RESET (1 << 0) /* Card reset */ + +/* PCMCIA_PGSR - PCMCIA General Status Register - fields */ +#define PCMCIA_PGSR_NWINE (1 << 4) /* No Window error */ +#define PCMCIA_PGSR_LPE (1 << 3) /* Low Power error */ +#define PCMCIA_PGSR_SE (1 << 2) /* Size error */ +#define PCMCIA_PGSR_CDE (1 << 1) /* Card Detect error */ +#define PCMCIA_PGSR_WPE (1 << 0) /* Write Protect error */ + +#endif /* __ASM_ARCH_MXC_PCMCIA_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pmic_audio.h b/arch/arm/plat-mxc/include/mach/pmic_audio.h new file mode 100644 index 000000000000..6754d5a6d04e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pmic_audio.h @@ -0,0 +1,2315 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_AUDIO_H__ +#define __ASM_ARCH_MXC_PMIC_AUDIO_H__ + +/*! + * @defgroup PMIC_AUDIO PMIC Audio Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_audio.h + * @brief External definitions for the PMIC Audio Client driver. + * + * The PMIC Audio driver and this API were developed to support the + * audio playback, recording, and mixing capabilities of the power + * management ICs that are available from Freescale Semiconductor, Inc. + * + * The following table shows which audio-related capabilities are supported + * by each power management IC: + * + * @ingroup PMIC_AUDIO + */ + +#include <linux/pmic_status.h> +#include <linux/pmic_external.h> + +/*************************************************************************** + * TYPEDEFS AND ENUMERATIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Audio Device Access Typedefs and Enumerations + * Typedefs and enumerations that are used for initial access to the + * PMIC Audio hardware. + */ +/*@{*/ + +/*! + * @typedef PMIC_AUDIO_HANDLE + * @brief Define typedef for a handle to the PMIC Audio hardware. + * + * Define a "handle" that is returned when the PMIC Audio hardware + * is opened. This handle grants exclusive access to the PMIC Audio + * hardware and must be used in all subsequent function calls. When access + * to the PMIC Audio hardware is no longer required, then a close + * operation must be done with this handle. The handle is no longer valid + * if the close operation was successful. + */ +typedef long *PMIC_AUDIO_HANDLE; + +/*! + * @enum PMIC_AUDIO_EVENTS + * @brief Identify the audio events that have been detected and should be + * handled. + * + * This enumeration defines all of the possible PMIC Audio events. Multiple + * events may be selected when defining a mask and multiple events may be + * signalled together. + * + * Note that the MICROPHONE_DETECT and MICROPHONE_REMOVED events may also be + * used to signal the operation of a serial or parallel microphone switch + * when used with a combined headset+microphone device. In that case the + * HEADSET_DETECT state must also be checked to determine if it's only the + * microphone switch being operated or whether the microphone has truly been + * inserted/removed (along with the headset). + */ +typedef enum { + HEADSET_DETECTED = 1, /*!< Detected headset insertion. */ + HEADSET_STEREO = 2, /*!< Detected stereo headset device. */ + HEADSET_MONO = 4, /*!< Detected mono headset device. */ + HEADSET_THERMAL_SHUTDOWN = 8, /*!< Detected output amplifier + shutdown due to thermal + limits . */ + HEADSET_SHORT_CIRCUIT = 16, /*!< Detected output amplifier + short circuit condition + . */ + HEADSET_REMOVED = 32, /*!< Detected headset removal. */ + MICROPHONE_DETECTED = 64, /*!< Detected microphone insertion. */ + MICROPHONE_REMOVED = 128, /*!< Detected microphone removal. */ + PTT_BUTTON_PRESS = 256, /*!< Detected PTT button down + . */ + PTT_BUTTON_RANGE = 512, /*!< Detected PTT button within + voltage range + . */ + PTT_SHORT_OR_INVALID = 1024 /*!< Detected PTT button outside + of voltage range or invalid + device . */ +} PMIC_AUDIO_EVENTS; + +/*! + * @typedef PMIC_AUDIO_CALLBACK + * @brief Typedef for PMIC Audio event notification callback function. + * + * Define a typedef for the PMIC Audio event notification callback + * function. The signalled events are passed to the function as the first + * argument. The callback function should then process whatever events it + * can and then return the set of unhandled events (if any). + */ +typedef PMIC_AUDIO_EVENTS(*PMIC_AUDIO_CALLBACK) (const PMIC_AUDIO_EVENTS event); + +typedef struct { + int hs_state; + int event_type; +} PMIC_HS_STATE; + +/*! + * @enum PMIC_AUDIO_SOURCE + * @brief Select an audio signal processing component. + * + * This enumeration defines all of the possible PMIC audio signal handling + * components which can be acquired by calling pmic_audio_open(). + * + * Note that the EXTERNAL_STEREO_IN selection is used to simply gain access + * to the stereo input pins. The stereo input signal can then be routed + * directly to the output amplifiers. In this case, no signal processing is + * done by either the Voice CODEC or the Stereo DAC. + */ +typedef enum { + STEREO_DAC, /*!< Open connection to Stereo DAC. */ + VOICE_CODEC, /*!< Open connection to Voice CODEC. */ + EXTERNAL_STEREO_IN /*!< Open connection to external stereo inputs. */ +} PMIC_AUDIO_SOURCE; + +/*@}*/ + +/*! + * @name Data Bus Setup and Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used to define and configure + * the data bus protocol in order to communicate with the Stereo DAC + * or the Voice CODEC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_DATA_BUS + * @brief Select the data bus used to transfer data between the host and + * Voice CODEC and/or the Stereo DAC. + * + * This enumeration defines all of the possible PMIC audio data buses that + * can be used to transfer data between the host and the Voice CODEC and/or + * the Stereo DAC on the PMIC. + * + * Note that the same data bus may be used to transfer audio data to/from + * the Voice CODEC and the Stereo DAC. However, in this case, the data bus + * must be configured for network mode with different timeslots assigned to + * the Voice CODEC and the Stereo DAC. Also, the sampling rates must be + * identical for both the Voice CODEC and the Stereo DAC in order to avoid + * a data bus timing conflict and audio signal distortion. + */ +typedef enum { + AUDIO_DATA_BUS_1, /*!< Use data bus 1 for audio data. */ + AUDIO_DATA_BUS_2 /*!< Use data bus 2 for audio data. */ +} PMIC_AUDIO_DATA_BUS; + +/*! + * @enum PMIC_AUDIO_BUS_PROTOCOL + * @brief Select the data bus protocol to be used. + * + * This enumeration defines all of the possible PMIC audio data bus protocols + * that may be selected. + */ +typedef enum { + NORMAL_MSB_JUSTIFIED_MODE, /*!< Transmit and receive audio data + in normal MSB-justified mode. */ + NETWORK_MODE, /*!< Transmit and receive audio data + in network mode. */ + I2S_MODE, /*!< Transmit and receive audio data + in I2S mode. */ + SPD_IF_MODE /*!< Transmit and receive audio data + in SPD/IF mode . */ +} PMIC_AUDIO_BUS_PROTOCOL; + +/*! + * @enum PMIC_AUDIO_BUS_MODE + * @brief Select the data bus mode to be used. + * + * This enumeration defines all of the possible PMIC audio data bus modes + * that may be selected. When configured in BUS_MASTER_MODE, the PMIC is + * responsible for supplying the data bus clock signals. Alternatively, + * when configured in BUS_SLAVE_MODE, the PMIC will use the data bus clock + * signals that are supplied by the bus master. + */ +typedef enum { + BUS_MASTER_MODE = 0, /*!< Operate as bus master. */ + BUS_SLAVE_MODE = 1 /*!< Operate as bus slave. */ +} PMIC_AUDIO_BUS_MODE; + +/*! + * @enum PMIC_AUDIO_CLOCK_IN_SOURCE + * @brief Select the clock signal source when in bus master mode. + * + * This enumeration defines all of the possible PMIC audio clock signal + * sources that may be selected. One of these clock signal sources must + * be selected in order to use either the Voice CODEC or the Stereo DAC. + * + * When configured in BUS_MASTER_MODE, the PMIC's onboard PLL circuits + * will also be driven by the selected clock input signal. + */ +typedef enum { + CLOCK_IN_DEFAULT, /*!< Just use default (power-up) clock input. */ + CLOCK_IN_CLIA, /*!< Use the CLIA clock source (Stereo DAC + default) . */ + CLOCK_IN_CLIB, /*!< Use the CLIB clock source (Voice CODEC + default) . */ + CLOCK_IN_CLKIN, /*!< Use the CLKIN clock source + . */ + CLOCK_IN_MCLK, /*!< Disable the internal PLL and use the MCLK + clock source (Stereo DAC only) + . */ + CLOCK_IN_FSYNC, /*!< Internal PLL input from external framesync + (Stereo DAC only) . */ + CLOCK_IN_BITCLK /*!< Internal PLL input from external bitclock + (Stereo DAC only) */ +} PMIC_AUDIO_CLOCK_IN_SOURCE; + +/*! + * @enum PMIC_AUDIO_CLOCK_INVERT + * @brief Select whether to invert the frame sync or bit clock signals. + * + * This enumeration enables or disables the inversion of the incoming + * frame sync or bit clock signals. + */ +typedef enum { + NO_INVERT = 0, /*!< Do not invert the clock signals. */ + INVERT_BITCLOCK = 1, /*!< Invert the BCLK input signal. */ + INVERT_FRAMESYNC = 2 /*!< Invert the FSYNC input signal. */ +} PMIC_AUDIO_CLOCK_INVERT; + +/*! + * @enum PMIC_AUDIO_NUMSLOTS + * @brief Select whether to invert the frame sync or bit clock signals. + * + * This enumeration defines all of the possible number of timeslots that may + * be selected when the PMIC is configured as the data bus master. One of these + * options must be selected if the Stereo DAC is to provide the data bus + * clock signals. + * + * Note that the Voice CODEC currently only allows USE_4_TIMESLOTS when + * operating in data bus master mode. + */ +typedef enum { + USE_2_TIMESLOTS, /*!< Configure for 2 timeslots. */ + USE_4_TIMESLOTS, /*!< Configure for 4 timeslots. */ + USE_8_STAR_TIMESLOTS, /*!< Configure for 8 (Left, Right, 6 other) timeslots. */ + USE_8_TIMESLOTS /*!< Configure for 8 timeslots. */ +} PMIC_AUDIO_NUMSLOTS; + +/*! + * @enum PMIC_AUDIO_STDAC_SAMPLING_RATE + * @brief Select the audio data sampling rate for the Stereo DAC. + * + * This enumeration defines all of the possible sampling rates currently + * supported by the Stereo DAC. One of these sampling rates must be selected + * and it must match that of the audio stream or else signal distortion will + * occur. + */ +typedef enum { + STDAC_RATE_8_KHZ, /*!< Use 8 kHz sampling rate. */ + STDAC_RATE_11_025_KHZ, /*!< Use 11.025 kHz sampling rate. */ + STDAC_RATE_12_KHZ, /*!< Use 12 kHz sampling rate. */ + STDAC_RATE_16_KHZ, /*!< Use 16 kHz sampling rate. */ + STDAC_RATE_22_050_KHZ, /*!< Use 22.050 kHz sampling rate. */ + STDAC_RATE_24_KHZ, /*!< Use 24 kHz sampling rate. */ + STDAC_RATE_32_KHZ, /*!< Use 32 kHz sampling rate. */ + STDAC_RATE_44_1_KHZ, /*!< Use 44.1 kHz sampling rate. */ + STDAC_RATE_48_KHZ, /*!< Use 48 kHz sampling rate. */ + STDAC_RATE_64_KHZ, /*!< Use 64 kHz sampling rate + . */ + STDAC_RATE_96_KHZ /*!< Use 96 kHz sampling rate. + . */ +} PMIC_AUDIO_STDAC_SAMPLING_RATE; + +/*! + * @enum PMIC_AUDIO_VCODEC_SAMPLING_RATE + * @brief Select the audio data sampling rate for the Voice CODEC. + * + * This enumeration defines all of the possible sampling rates currently + * supported by the Voice CODEC. One of these sampling rates must be selected + * and it must match that of the audio stream or else signal distortion will + * occur. + */ +typedef enum { + VCODEC_RATE_8_KHZ, /*!< Use 8 kHz sampling rate. */ + VCODEC_RATE_16_KHZ, /*!< Use 16 kHz sampling rate. */ +} PMIC_AUDIO_VCODEC_SAMPLING_RATE; + +/*! + * @enum PMIC_AUDIO_ANTI_POP_RAMP_SPEED + * @brief Select the anti-pop circuitry's ramp up speed. + * + * This enumeration defines all of the possible ramp up speeds for the + * anti-pop circuitry. A slow ramp up speed may be required in order to + * avoid the popping noise that is typically generated during the insertion + * or removal of a headset or microphone. + */ +typedef enum { + ANTI_POP_RAMP_FAST, /*!< Select fast ramp up. */ + ANTI_POP_RAMP_SLOW /*!< Select slow ramp up. */ +} PMIC_AUDIO_ANTI_POP_RAMP_SPEED; + +/*@}*/ + +/*! + * @name General Voice CODEC Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used to define and configure + * the basic operating options for the Voice CODEC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ + * @brief Select the Voice CODEC input clock frequency. + * + * This enumeration defines all of the supported Voice CODEC input clock + * frequencies. One of these frequencies must be selected in order to + * properly configure the Voice CODEC to operate at the required sampling + * rate. + */ +typedef enum { + VCODEC_CLI_13MHZ, /*!< Clock frequency is 13MHz. */ + VCODEC_CLI_15_36MHZ, /*!< Clock frequency is 15.36MHz. */ + VCODEC_CLI_16_8MHZ, /*!< Clock frequency is 16.8MHz + . */ + VCODEC_CLI_26MHZ, /*!< Clock frequency is 26MHz. */ + VCODEC_CLI_33_6MHZ, /*!< Clock frequency is 33.6MHz. */ +} PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ; + +/*! + * @enum PMIC_AUDIO_VCODEC_CONFIG + * @brief Select the Voice CODEC configuration options. + * + * This enumeration is used to enable/disable each of the Voice CODEC options. + * This includes the use of highpass digital filters and audio signal + * loopback modes. + * + * Note that resetting the digital filters is now handled by the + * pmic_audio_digital_filter_reset() API. + */ +typedef enum { + DITHERING = 1, /*!< Enable/disable dithering. */ + INPUT_HIGHPASS_FILTER = 2, /*!< Enable/disable the input high + pass digital filter. */ + OUTPUT_HIGHPASS_FILTER = 4, /*!< Enable/disable the output high + pass digital filter. */ + ANALOG_LOOPBACK = 8, /*!< Enable/disable the analog + loopback path + . */ + DIGITAL_LOOPBACK = 16, /*!< Enable/disable the digital + loopback path. */ + VCODEC_MASTER_CLOCK_OUTPUTS = 32, /*!< Enable/disable the bus master + clock outputs. */ + TRISTATE_TS = 64 /*!< Enable/disable FSYNC, BITCLK, + and TX tristate. */ +} PMIC_AUDIO_VCODEC_CONFIG; + +/*@}*/ + +/*! + * @name General Stereo DAC Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used to define and configure + * the basic operating options for the Stereo DAC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_STDAC_CLOCK_IN_FREQ + * @brief Select the Stereo DAC input clock frequency. + * + * This enumeration defines all of the supported Stereo DAC input clock + * frequencies. One of these frequencies must be selected in order to + * properly configure the Stereo DAC to operate at the required sampling + * rate. + */ +typedef enum { + STDAC_CLI_3_36864MHZ, /*!< Clock frequency is 3.36864MHz + . */ + STDAC_CLI_12MHZ, /*!< Clock frequency is 12MHz. + . */ + STDAC_CLI_13MHZ, /*!< Clock frequency is 13MHz. */ + STDAC_CLI_15_36MHZ, /*!< Clock frequency is 15.36MHz. */ + STDAC_CLI_16_8MHZ, /*!< Clock frequency is 16.8MHz + . */ + STDAC_CLI_26MHZ, /*!< Clock frequency is 26MHz. */ + STDAC_CLI_33_6MHZ, /*!< Clock frequency is 33.6MHz. */ + STDAC_MCLK_PLL_DISABLED, /*!< Use MCLK and disable internal PLL. */ + STDAC_FSYNC_IN_PLL, /*!< Use FSYNC as internal PLL input. */ + STDAC_BCLK_IN_PLL /*!< Use BCLK as internal PLL input. */ +} PMIC_AUDIO_STDAC_CLOCK_IN_FREQ; + +/*! + * @enum PMIC_AUDIO_STDAC_CONFIG + * @brief Select the Stereo DAC configuration options. + * + * This enumeration is used to enable/disable each of the Stereo DAC options. + */ +typedef enum { + STDAC_MASTER_CLOCK_OUTPUTS = 1 /*!< Enable/disable the bus master clock + outputs. */ +} PMIC_AUDIO_STDAC_CONFIG; + +/*@}*/ + +/*! + * @name Voice CODEC Audio Port Mixing Typedefs and Enumerations + * Typedefs and enumerations that are used for setting up the audio mixer + * within the Voice CODEC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_VCODEC_TIMESLOT + * @brief Select the Stereo DAC configuration options. + * + * This enumeration is used to select the timeslot for both the primary and + * secondary (for mc13783-only) audio channels to the Voice CODEC. + */ +typedef enum { + USE_TS0, /*!< Use timeslot 0 for audio signal source + . */ + USE_TS1, /*!< Use timeslot 1 for audio signal source + . */ + USE_TS2, /*!< Use timeslot 2 for audio signal source + . */ + USE_TS3 /*!< Use timeslot 3 for audio signal source + . */ +} PMIC_AUDIO_VCODEC_TIMESLOT; + +/*! + * @enum PMIC_AUDIO_VCODEC_MIX_IN_GAIN + * @brief Select the secondary channel input gain for the Voice CODEC mixer. + * + * This enumeration selects the secondary channel input gain for the Voice + * CODEC mixer. + */ +typedef enum { + VCODEC_NO_MIX, /*!< No audio mixing . */ + VCODEC_MIX_IN_0DB, /*!< Mix with 0dB secondary channel gain + . */ + VCODEC_MIX_IN_MINUS_6DB, /*!< Mix with -6dB secondary channel gain + . */ + VCODEC_MIX_IN_MINUS_12DB, /*!< Mix with -12dB secondary channel gain + . */ +} PMIC_AUDIO_VCODEC_MIX_IN_GAIN; + +/*! + * @enum PMIC_AUDIO_VCODEC_MIX_OUT_GAIN + * @brief Select the output gain for the Voice CODEC mixer. + * + * This enumeration selects the output gain for the Voice CODEC mixer. + */ +typedef enum { + VCODEC_MIX_OUT_0DB, /*!< Select 0dB mixer output gain + . */ + VCODEC_MIX_OUT_MINUS_6DB, /*!< Select -6dB mixer output gain + . */ +} PMIC_AUDIO_VCODEC_MIX_OUT_GAIN; + +/*@}*/ + +/*! + * @name Stereo DAC Audio Port Mixing Typedefs and Enumerations + * Typedefs and enumerations that are used for setting up the audio mixer + * within the Stereo DAC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_STDAC_TIMESLOTS + * @brief Select the timeslots used to transmit the left and right audio + * channels to the Stereo DAC. + * + * This enumeration is used to select the timeslots used to transmit the + * data corresponding to the left and right audio channels to the Stereo + * DAC. + */ +typedef enum { + USE_TS0_TS1, /*!< Use timeslots 0 and 1 for left and + right channels, respectively. */ + USE_TS2_TS3, /*!< Use timeslots 2 and 3 for left and + right channels, respectively + . */ + USE_TS4_TS5, /*!< Use timeslots 4 and 5 for left and + right channels, respectively + . */ + USE_TS6_TS7 /*!< Use timeslots 6 and 7 for left and + right channels, respectively + . */ +} PMIC_AUDIO_STDAC_TIMESLOTS; + +/*! + * @enum PMIC_AUDIO_STDAC_MIX_IN_GAIN + * @brief Select the secondary channel input gain for the Stereo DAC mixer. + * + * This enumeration is used to select the secondary channel input gain for + * the Stereo DAC mixer. + */ +typedef enum { + STDAC_NO_MIX, /*!< No mixing, keep separate left + and right audio channels. */ + STDAC_MIX_IN_0DB, /*!< Mix left and right audio channels + together with 0dB secondary + channel gain. */ + STDAC_MIX_IN_MINUS_6DB, /*!< Mix left and right audio channels + together with -6dB secondary + channel gain. */ + STDAC_MIX_IN_MINUS_12DB /*!< Mix left and right audio channels + together with -12dB secondary + channel gain . */ +} PMIC_AUDIO_STDAC_MIX_IN_GAIN; + +/*! + * @enum PMIC_AUDIO_STDAC_MIX_OUT_GAIN + * @brief Select the output gain for the Stereo DAC mixer. + * + * This enumeration is used to select the output gain for the Stereo DAC + * mixer. + */ +typedef enum { + STDAC_MIX_OUT_0DB, /*!< Select 0dB mixer output gain. */ + STDAC_MIX_OUT_MINUS_6DB, /*!< Select -6dB mixer output gain + . */ +} PMIC_AUDIO_STDAC_MIX_OUT_GAIN; + +/*@}*/ + +/*! + * @name Microphone Input Typedefs and Enumerations + * Typedefs and enumerations that are used for selecting and setting up + * one or more or microphone inputs for recording. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_MIC_BIAS + * @brief Select the microphone bias circuit to be enabled/disabled. + * + * This enumeration lists all of the available microphone bias circuits that + * may be enabled or disabled. + */ +typedef enum { + NO_BIAS = 0, /*!< No microphone bias circuit selected. */ + MIC_BIAS1 = 1, /*!< Enable/disable microphone bias 1 circuit. */ + MIC_BIAS2 = 2, /*!< Enable/disable microphone bias 2 circuit. */ +} PMIC_AUDIO_MIC_BIAS; + +/*! + * @enum PMIC_AUDIO_INPUT_PORT + * @brief Select an audio input port for recording. + * + * This enumeration lists all of the available audio input ports that may + * be selected for a recording operation. + */ +typedef enum { + NO_MIC, /*!< No microphone input selected. */ + MIC1_LEFT, /*!< Enable left/mono channel microphone input + . */ + MIC1_RIGHT_MIC_MONO, /*!< Enable right channel microphone input. */ + MIC2_AUX, /*!< Enable auxiliary microphone input. */ + TXIN_EXT /*!< Enable external mono input. */ +} PMIC_AUDIO_INPUT_PORT; + +/*! + * @enum PMIC_AUDIO_INPUT_MIC_STATE + * @brief Control whether the input microphone is on/off. + * + * This enumeration allows the currently selected input microphone amplifier + * to be turned on/off. + */ +typedef enum { + MICROPHONE_ON, /*!< Turn microphone input on for recording. */ + MICROPHONE_OFF /*!< Turn microphone input off (mute). */ +} PMIC_AUDIO_INPUT_MIC_STATE; + +/*! + * @enum PMIC_AUDIO_INPUT_CONFIG + * @brief Enable/disable the audio input options. + * + * This enumeration allows for enabling/disabling any of the audio input + * section options. + */ +typedef enum { + MIC_AMP_AUTO_DISABLE = 1 /*!< Enable/disable automatic disabling of + microphone input amplifiers following + headset insertion/removal */ +} PMIC_AUDIO_INPUT_CONFIG; + +/*! + * @enum PMIC_AUDIO_MIC_AMP_MODE + * @brief Select the operating mode for the microphone amplifiers. + * + * This enumeration is used to select the operating mode for the microphone + * amplifier. + */ +typedef enum { + AMP_OFF, /*!< Disable input amplifier. */ + VOLTAGE_TO_VOLTAGE, /*!< Operate input amplifier in + voltage-to-voltage mode + . */ + CURRENT_TO_VOLTAGE /*!< Operate input amplifier in + current-to-voltage mode */ +} PMIC_AUDIO_MIC_AMP_MODE; + +/*! + * @enum PMIC_AUDIO_MIC_GAIN + * @brief Select the microphone amplifier gain level. + * + * This enumeration lists all of the available microphone amplifier gain + * levels. + */ +typedef enum { + MIC_GAIN_MINUS_8DB, /*!< Select -8dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_7DB, /*!< Select -7dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_6DB, /*!< Select -6dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_5DB, /*!< Select -5dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_4DB, /*!< Select -4dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_3DB, /*!< Select -3dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_2DB, /*!< Select -2dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_1DB, /*!< Select -1dB microphone amplifier gain + . */ + MIC_GAIN_0DB, /*!< Select 0dB microphone amplifier gain. */ + MIC_GAIN_PLUS_1DB, /*!< Select 1dB microphone amplifier gain. */ + MIC_GAIN_PLUS_2DB, /*!< Select 2dB microphone amplifier gain. */ + MIC_GAIN_PLUS_3DB, /*!< Select 3dB microphone amplifier gain. */ + MIC_GAIN_PLUS_4DB, /*!< Select 4dB microphone amplifier gain. */ + MIC_GAIN_PLUS_5DB, /*!< Select 5dB microphone amplifier gain. */ + MIC_GAIN_PLUS_6DB, /*!< Select 6dB microphone amplifier gain. */ + MIC_GAIN_PLUS_7DB, /*!< Select 7dB microphone amplifier gain. */ + MIC_GAIN_PLUS_8DB, /*!< Select 8dB microphone amplifier gain. */ + MIC_GAIN_PLUS_9DB, /*!< Select 9dB microphone amplifier gain. */ + MIC_GAIN_PLUS_10DB, /*!< Select 10dB microphone amplifier gain. */ + MIC_GAIN_PLUS_11DB, /*!< Select 11dB microphone amplifier gain. */ + MIC_GAIN_PLUS_12DB, /*!< Select 12dB microphone amplifier gain. */ + MIC_GAIN_PLUS_13DB, /*!< Select 13dB microphone amplifier gain. */ + MIC_GAIN_PLUS_14DB, /*!< Select 14dB microphone amplifier gain. */ + MIC_GAIN_PLUS_15DB, /*!< Select 15dB microphone amplifier gain. */ + MIC_GAIN_PLUS_16DB, /*!< Select 16dB microphone amplifier gain. */ + MIC_GAIN_PLUS_17DB, /*!< Select 17dB microphone amplifier gain. */ + MIC_GAIN_PLUS_18DB, /*!< Select 18dB microphone amplifier gain. */ + MIC_GAIN_PLUS_19DB, /*!< Select 19dB microphone amplifier gain. */ + MIC_GAIN_PLUS_20DB, /*!< Select 20dB microphone amplifier gain. */ + MIC_GAIN_PLUS_21DB, /*!< Select 21dB microphone amplifier gain. */ + MIC_GAIN_PLUS_22DB, /*!< Select 22dB microphone amplifier gain. */ + MIC_GAIN_PLUS_23DB, /*!< Select 23dB microphone amplifier gain. */ + MIC_GAIN_PLUS_24DB, /*!< Select 24dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_25DB, /*!< Select 25dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_26DB, /*!< Select 26dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_27DB, /*!< Select 27dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_28DB, /*!< Select 28dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_29DB, /*!< Select 29dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_30DB, /*!< Select 30dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_31DB /*!< Select 31dB microphone amplifier gain + . */ +} PMIC_AUDIO_MIC_GAIN; + +/*@}*/ + +/*! + * @name Audio Output Section Typedefs and Enumerations + * Typedefs and enumerations that are used for selecting and setting up + * one or more or audio output ports for playback. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_OUTPUT_PORT + * @brief Select the audio output port. + * + * This enumeration lists all of the available audio output ports. One or + * more may be selected as desired to handle the output audio stream from + * either the Voice CODEC or the Stereo DAC. + */ +typedef enum { + MONO_SPEAKER = 1, /*!< Select mono output speaker. */ + MONO_LOUDSPEAKER = 2, /*!< Select mono loudspeaker + . */ + MONO_ALERT = 4, /*!< Select mono alert output */ + MONO_EXTOUT = 8, /*!< Select mono external output */ + MONO_CDCOUT = 16, /*!< Select dedicated Voice CODEC output + . */ + STEREO_LEFT_LOW_POWER = 32, /*!< Select stereo left channel low power + output . */ + STEREO_HEADSET_LEFT = 64, /*!< Select stereo headset left channel. */ + STEREO_HEADSET_RIGHT = 128, /*!< Select stereo headset right channel. */ + STEREO_OUT_LEFT = 256, /*!< Select stereo external left channel + output . */ + STEREO_OUT_RIGHT = 512 /*!< Select stereo external right channel + output . */ +} PMIC_AUDIO_OUTPUT_PORT; + +/*! + * @enum PMIC_AUDIO_OUTPUT_CONFIG + * @brief Enable/disable the audio output section options. + * + * This enumeration is used to enable/disable any of the audio output section + * options. + */ +typedef enum { + MONO_SPEAKER_INVERT_OUT_ONLY = 1, /*!< Enable/disable the non-inverted + mono speaker output */ + MONO_LOUDSPEAKER_COMMON_BIAS = 2, /*!< Enable/disable the loudspeaker + output amplifier common bias + . */ + HEADSET_DETECT_ENABLE = 4, /*!< Enable/disable headset + insertion/removal detection + . */ + STEREO_HEADSET_AMP_AUTO_DISABLE = 8 /*!< Enable/disable automatic + disabling of the stereo headset + output amplifiers following + headset insertion/removal. */ +} PMIC_AUDIO_OUTPUT_CONFIG; + +/*! + * @enum PMIC_AUDIO_STEREO_IN_GAIN + * @brief Select the amplifier gain for the external stereo inputs. + * + * This enumeration is used to select the amplifier gain level to be used for + * the external stereo inputs. + */ +typedef enum { + STEREO_IN_GAIN_0DB, /*!< Select 0dB external stereo signal + input gain. */ + STEREO_IN_GAIN_PLUS_18DB /*!< Select 18dB external stereo signal + input gain . */ +} PMIC_AUDIO_STEREO_IN_GAIN; + +/*! + * @enum PMIC_AUDIO_OUTPUT_PGA_GAIN + * @brief Select the output PGA amplifier gain level. + * + * This enumeration is used to select the output PGA amplifier gain level. + */ +typedef enum { + OUTPGA_GAIN_MINUS_33DB, /*!< Select -33dB output PGA gain + . */ + OUTPGA_GAIN_MINUS_30DB, /*!< Select -30dB output PGA gain + . */ + OUTPGA_GAIN_MINUS_27DB, /*!< Select -27dB output PGA gain + . */ + OUTPGA_GAIN_MINUS_24DB, /*!< Select -24dB output PGA gain. */ + OUTPGA_GAIN_MINUS_21DB, /*!< Select -21dB output PGA gain. */ + OUTPGA_GAIN_MINUS_18DB, /*!< Select -18dB output PGA gain. */ + OUTPGA_GAIN_MINUS_15DB, /*!< Select -15dB output PGA gain. */ + OUTPGA_GAIN_MINUS_12DB, /*!< Select -12dB output PGA gain. */ + OUTPGA_GAIN_MINUS_9DB, /*!< Select -9dB output PGA gain. */ + OUTPGA_GAIN_MINUS_6DB, /*!< Select -6dB output PGA gain. */ + OUTPGA_GAIN_MINUS_3DB, /*!< Select -3dB output PGA gain. */ + OUTPGA_GAIN_0DB, /*!< Select 0dB output PGA gain. */ + OUTPGA_GAIN_PLUS_3DB, /*!< Select 3dB output PGA gain. */ + OUTPGA_GAIN_PLUS_6DB, /*!< Select 6dB output PGA gain. */ + OUTPGA_GAIN_PLUS_9DB, /*!< Select 9dB output PGA gain. + . */ + OUTPGA_GAIN_PLUS_12DB, /*!< Select 12dB output PGA gain + . */ + OUTPGA_GAIN_PLUS_15DB, /*!< Select 15dB output PGA gain + . */ + OUTPGA_GAIN_PLUS_18DB, /*!< Select 18dB output PGA gain + . */ + OUTPGA_GAIN_PLUS_21DB /*!< Select 21dB output PGA gain + . */ +} PMIC_AUDIO_OUTPUT_PGA_GAIN; + +/*! + * @enum PMIC_AUDIO_OUTPUT_BALANCE_GAIN + * @brief Select the left/right channel balance gain level. + * + * This enumeration is used to select the balance gain level that is to be + * separately applied to the left and right audio channels. + */ +typedef enum { + BAL_GAIN_MINUS_21DB, /*!< Select -21dB channel balance + gain . */ + BAL_GAIN_MINUS_18DB, /*!< Select -18dB channel balance + gain . */ + BAL_GAIN_MINUS_15DB, /*!< Select -15dB channel balance + gain . */ + BAL_GAIN_MINUS_12DB, /*!< Select -12dB channel balance + gain . */ + BAL_GAIN_MINUS_9DB, /*!< Select -9dB channel balance + gain . */ + BAL_GAIN_MINUS_6DB, /*!< Select -6dB channel balance + gain . */ + BAL_GAIN_MINUS_3DB, /*!< Select -3dB channel balance + gain . */ + BAL_GAIN_0DB /*!< Select 0dB channel balance gain. */ +} PMIC_AUDIO_OUTPUT_BALANCE_GAIN; + +/*! + * @enum PMIC_AUDIO_MONO_ADDER_MODE + * @brief Select the output mono adder operating mode. + * + * This enumeration is used to select the operating mode for the mono adder + * in the audio output section. + */ +typedef enum { + MONO_ADDER_OFF, /*!< Disable mono adder (keep separate + left and right channels). */ + MONO_ADD_LEFT_RIGHT, /*!< Add left and right channels. */ + MONO_ADD_OPPOSITE_PHASE, /*!< Add left and right channels but + with outputs in opposite phase + . */ + STEREO_OPPOSITE_PHASE /*!< Keep separate left and right + channels but invert phase of + left channel . */ +} PMIC_AUDIO_MONO_ADDER_MODE; + +/*! + * @enum PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + * @brief Select the mono adder output amplifier gain level. + * + * This enumeration is used to select the output amplifier gain level for + * the mono adder. + */ +typedef enum { + MONOADD_GAIN_MINUS_6DB, /*!< Select -6dB mono adder output gain + . */ + MONOADD_GAIN_MINUS_3DB, /*!< Select -3dB mono adder output gain + . */ + MONOADD_GAIN_0DB /*!< Select 0dB mono adder output gain. */ +} PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN; + +/*@}*/ + +/*************************************************************************** + * PMIC-SPECIFIC DEFINITIONS * + ***************************************************************************/ + +/*! + * @name Definition of PMIC-specific Capabilities + * Constants that are used to define PMIC-specific capabilities. + */ +/*@{*/ + +/*! + * Define the minimum Stereo DAC sampling rate (Hz). + */ +extern const unsigned MIN_STDAC_SAMPLING_RATE_HZ; +/*! + * Define the maximum Stereo DAC sampling rate (Hz). + */ +extern const unsigned MAX_STDAC_SAMPLING_RATE_HZ; + +/*@}*/ + +#define DEBUG_AUDIO + +#ifdef __KERNEL__ + +/*************************************************************************** + * PMIC API DEFINITIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Audio + * hardware. + */ +/*@{*/ + +/*! + * This function enables the Headset detection mechanism in hardware + */ +PMIC_STATUS pmic_audio_set_autodetect(int val); + +/*! + * @brief Request exclusive access to the PMIC Audio hardware. + * + * Attempt to open and gain exclusive access to a key PMIC audio hardware + * component (e.g., the Stereo DAC or the Voice CODEC). Depending upon the + * type of audio operation that is desired and the nature of the audio data + * stream, the Stereo DAC and/or the Voice CODEC will be a required hardware + * component and needs to be acquired by calling this function. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls to complete + * the configuration of either the Stereo DAC or the Voice CODEC and along + * with any other associated audio hardware components that will be needed. + * + * The same handle must also be used in the close call when use of the PMIC + * audio hardware is no longer required. + * + * The open request will fail if the requested audio hardware component has + * already been acquired by a previous open call but not yet closed. + * + * @param[out] handle Device handle to be used for subsequent PMIC + * Connectivity API calls. + * @param[in] device The required PMIC audio hardware component. + * + * @retval PMIC_SUCCESS If the open request was successful + * @retval PMIC_PARAMETER_ERROR If the handle argument is NULL. + * @retval PMIC_ERROR If the audio hardware component is + * unavailable. + */ +PMIC_STATUS pmic_audio_open(PMIC_AUDIO_HANDLE * const handle, + const PMIC_AUDIO_SOURCE device); + +/*! + * @brief Terminate further access to the PMIC audio hardware. + * + * Terminate further access to the PMIC audio hardware that was previously + * acquired by calling pmic_audio_open(). This now allows another thread to + * successfully call pmic_audio_open() to gain access. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_close(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Configure the data bus protocol to be used. + * + * Provide the parameters needed to properly configure the audio data bus + * protocol so that data can be read/written to either the Stereo DAC or + * the Voice CODEC. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] busID Select data bus to be used. + * @param[in] protocol Select the data bus protocol. + * @param[in] masterSlave Select the data bus timing mode. + * @param[in] numSlots Define the number of timeslots (only if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful configured. + * @retval PMIC_PARAMETER_ERROR If the handle or the protocol parameters + * are invalid. + */ +PMIC_STATUS pmic_audio_set_protocol(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_DATA_BUS busID, + const PMIC_AUDIO_BUS_PROTOCOL protocol, + const PMIC_AUDIO_BUS_MODE masterSlave, + const PMIC_AUDIO_NUMSLOTS numSlots); + +/*! + * @brief Retrieve the current data bus protocol configuration. + * + * Retrieve the parameters that define the current audio data bus protocol. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] busID The data bus being used. + * @param[out] protocol The data bus protocol being used. + * @param[out] masterSlave The data bus timing mode being used. + * @param[out] numSlots The number of timeslots being used (if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_protocol(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_DATA_BUS * const busID, + PMIC_AUDIO_BUS_PROTOCOL * const protocol, + PMIC_AUDIO_BUS_MODE * const masterSlave, + PMIC_AUDIO_NUMSLOTS * const numSlots); + +/*! + * @brief Enable the Stereo DAC or the Voice CODEC. + * + * Explicitly enable the Stereo DAC or the Voice CODEC to begin audio + * playback or recording as required. This should only be done after + * successfully configuring all of the associated audio components (e.g., + * microphones, amplifiers, etc.). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful enabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be enabled. + */ +PMIC_STATUS pmic_audio_enable(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Disable the Stereo DAC or the Voice CODEC. + * + * Explicitly disable the Stereo DAC or the Voice CODEC to end audio + * playback or recording as required. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful disabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be disabled. + */ +PMIC_STATUS pmic_audio_disable(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Reset the selected audio hardware control registers to their + * power on state. + * + * This resets all of the audio hardware control registers currently + * associated with the device handle back to their power on states. For + * example, if the handle is associated with the Stereo DAC and a + * specific output port and output amplifiers, then this function will + * reset all of those components to their power on state. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Reset all audio hardware control registers to their power on state. + * + * This resets all of the audio hardware control registers back to their + * power on states. Use this function with care since it also invalidates + * (i.e., automatically closes) all currently opened device handles. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset_all(void); + +/*! + * @brief Set the Audio callback function. + * + * Register a callback function that will be used to signal PMIC audio + * events. For example, the OSS audio driver should register a callback + * function in order to be notified of headset connect/disconnect events. + * + * @param[in] func A pointer to the callback function. + * @param[in] eventMask A mask selecting events to be notified. + * @param[in] hs_state To know the headset state. + * + * @retval PMIC_SUCCESS If the callback was successfully + * registered. + * @retval PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid. + */ +PMIC_STATUS pmic_audio_set_callback(void *func, + const PMIC_AUDIO_EVENTS eventMask, + PMIC_HS_STATE *hs_state); + +/*! + * @brief Deregisters the existing audio callback function. + * + * Deregister the callback function that was previously registered by calling + * pmic_audio_set_callback(). + * + * + * @retval PMIC_SUCCESS If the callback was successfully + * deregistered. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_clear_callback(void); + +/*! + * @brief Get the current audio callback function settings. + * + * Get the current callback function and event mask. + * + * @param[out] func The current callback function. + * @param[out] eventMask The current event selection mask. + * + * @retval PMIC_SUCCESS If the callback information was + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_callback(PMIC_AUDIO_CALLBACK * const func, + PMIC_AUDIO_EVENTS * const eventMask); + +/*! + * @brief Enable the anti-pop circuitry to avoid extra noise when inserting + * or removing a external device (e.g., a headset). + * + * Enable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. A slow ramp speed may be needed to avoid extra noise. + * + * @param[in] rampSpeed The desired anti-pop circuitry ramp speed. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * enabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * enabled. + */ +PMIC_STATUS pmic_audio_antipop_enable(const PMIC_AUDIO_ANTI_POP_RAMP_SPEED + rampSpeed); + +/*! + * @brief Disable the anti-pop circuitry. + * + * Disable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * disabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * disabled. + */ +PMIC_STATUS pmic_audio_antipop_disable(void); + +/*! + * @brief Performs a reset of the Voice CODEC/Stereo DAC digital filter. + * + * This function performs a reset of the digital filter using the back-to-back + * SPI write procedure. + * + * @retval PMIC_SUCCESS If the digital filter was successfully + * reset. + * @retval PMIC_ERROR If the digital filter could not be reset. + */ +PMIC_STATUS pmic_audio_digital_filter_reset(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Get the most recent PTT button voltage reading. + * + * This function returns the most recent reading for the PTT button voltage. + * The value may be used during the processing of the PTT_BUTTON_RANGE event + * as part of the headset ID detection process. + * + * @retval PMIC_SUCCESS If the most recent PTT button voltage was + * returned. + * @retval PMIC_PARAMETER_ERROR If a NULL pointer argument was given. + */ +PMIC_STATUS pmic_audio_get_ptt_button_level(unsigned int *const level); + +#ifdef DEBUG_AUDIO + +/*! + * @brief Provide a hexadecimal dump of all PMIC audio registers (DEBUG only). + * + * This function is intended strictly for debugging purposes only (i.e., + * the DEBUG macro must be defined) and will print the current values of the + * following PMIC registers: + * + * - AUD_CODEC (Voice CODEC state) + * - ST_DAC (Stereo DAC state) + * - RX_AUD_AMPS (audio input section state) + * - TX_AUD_AMPS (audio output section state) + * + * The register fields will also be decoded. + */ +void pmic_audio_dump_registers(void); + +#endif /* DEBUG */ + +/*@}*/ + +/*! + * @name General Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice + * CODEC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Voice CODEC clock source and operating characteristics. + * + * Define the Voice CODEC clock source and operating characteristics. This + * must be done before the Voice CODEC is enabled. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] clockIn Select the clock signal source. + * @param[in] clockFreq Select the clock signal frequency. + * @param[in] samplingRate Select the audio data sampling rate. + * @param[in] invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE + clockIn, + const PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_VCODEC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert); + +/*! + * @brief Get the Voice CODEC clock source and operating characteristics. + * + * Get the current Voice CODEC clock source and operating characteristics. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] clockIn The clock signal source. + * @param[out] clockFreq The clock signal frequency. + * @param[out] samplingRate The audio data sampling rate. + * @param[out] invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_VCODEC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_CLOCK_INVERT * const invert); + +/*! + * @brief Set the Voice CODEC primary audio channel timeslot. + * + * Set the Voice CODEC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + timeslot); + +/*! + * @brief Get the current Voice CODEC primary audio channel timeslot. + * + * Get the current Voice CODEC primary audio channel timeslot. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot); + +/*! + * @brief Set the Voice CODEC secondary recording audio channel timeslot. + * + * Set the Voice CODEC secondary audio channel timeslot. This function must be + * used if the default timeslot for the secondary audio channel is to be + * changed. The secondary audio channel timeslot is used to transmit the audio + * data that was recorded by the Voice CODEC from the secondary audio input + * channel. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] timeslot Select the secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_VCODEC_TIMESLOT + timeslot); + +/*! + * @brief Get the Voice CODEC secondary recording audio channel timeslot. + * + * Get the Voice CODEC secondary audio channel timeslot. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] timeslot The secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot); + +/*! + * @brief Set/Enable the Voice CODEC options. + * + * Set or enable various Voice CODEC options. The available options include + * the use of dithering, highpass digital filters, and loopback modes. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Voice CODEC options to enable. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG config); + +/*! + * @brief Clear/Disable the Voice CODEC options. + * + * Clear or disable various Voice CODEC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Voice CODEC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_vcodec_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG + config); + +/*! + * @brief Get the current Voice CODEC options. + * + * Get the current Voice CODEC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of Voice CODEC options. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_CONFIG * + const config); + +/*! + * @brief Enable the Voice CODEC bypass audio pathway. + * + * Enables the Voice CODEC bypass pathway for audio data. This allows direct + * output of the voltages on the TX data bus line to the output amplifiers + * (bypassing the digital-to-analog converters within the Voice CODEC). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_bypass(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Disable the Voice CODEC bypass audio pathway. + * + * Disables the Voice CODEC bypass pathway for audio data. This means that + * the TX data bus line will deliver digital data to the digital-to-analog + * converters within the Voice CODEC. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_bypass(const PMIC_AUDIO_HANDLE handle); + +/*@}*/ + +/*! + * @name General Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo + * DAC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Stereo DAC clock source and operating characteristics. + * + * Define the Stereo DAC clock source and operating characteristics. This + * must be done before the Stereo DAC is enabled. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] clockIn Select the clock signal source. + * @param[in] clockFreq Select the clock signal frequency. + * @param[in] samplingRate Select the audio data sampling rate. + * @param[in] invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE clockIn, + const PMIC_AUDIO_STDAC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_STDAC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert); + +/*! + * @brief Get the Stereo DAC clock source and operating characteristics. + * + * Get the current Stereo DAC clock source and operating characteristics. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] clockIn The clock signal source. + * @param[out] clockFreq The clock signal frequency. + * @param[out] samplingRate The audio data sampling rate. + * @param[out] invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_STDAC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_STDAC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_CLOCK_INVERT * const invert); + +/*! + * @brief Set the Stereo DAC primary audio channel timeslot. + * + * Set the Stereo DAC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + timeslot); + +/*! + * @brief Get the current Stereo DAC primary audio channel timeslot. + * + * Get the current Stereo DAC primary audio channel timeslot. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_TIMESLOTS * + const timeslot); + +/*! + * @brief Set/Enable the Stereo DAC options. + * + * Set or enable various Stereo DAC options. The available options include + * enabling/disabling the bus master clock outputs. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Stereo DAC options to enable. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_stdac_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config); + +/*! + * @brief Clear/Disable the Stereo DAC options. + * + * Clear or disable various Stereo DAC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Stereo DAC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_stdac_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config); + +/*! + * @brief Get the current Stereo DAC options. + * + * Get the current Stereo DAC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of Stereo DAC options. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_CONFIG * const config); + +/*@}*/ + +/*! + * @name Audio Input Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio + * input hardware. + */ +/*@{*/ + +/*! + * @brief Set/Enable the audio input section options. + * + * Set or enable various audio input section options. The only available + * option right now is to enable the automatic disabling of the microphone + * input amplifiers when a microphone/headset is inserted or removed. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The audio input section options to enable. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be successfully set/enabled. + */ +PMIC_STATUS pmic_audio_input_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config); + +/*! + * @brief Clear/Disable the audio input section options. + * + * Clear or disable various audio input section options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The audio input section options to be + * cleared/disabled. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be cleared/disabled. + */ +PMIC_STATUS pmic_audio_input_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config); + +/*! + * @brief Get the current audio input section options. + * + * Get the current audio input section options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of audio input section options. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_input_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_CONFIG * const config); + +/*@}*/ + +/*! + * @name Audio Recording Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio recording. + */ +/*@{*/ + +/*! + * @brief Select the microphone inputs to be used for Voice CODEC recording. + * + * Select left and right microphone inputs for Voice CODEC + * recording. It is possible to disable or not use a particular microphone + * input channel by specifying NO_MIC as a parameter. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftChannel Select the left microphone input channel. + * @param[in] rightChannel Select the right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input ports + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be successfully enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_PORT leftChannel, + const PMIC_AUDIO_INPUT_PORT rightChannel); + +/*! + * @brief Get the current microphone inputs being used for Voice CODEC + * recording. + * + * Get the left and right microphone inputs currently being + * used for Voice CODEC recording. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftChannel The left microphone input channel. + * @param[out] rightChannel The right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_PORT * const leftChannel, + PMIC_AUDIO_INPUT_PORT * + const rightChannel); + +/*! + * @brief Enable/disable the microphone input. + * + * This function enables/disables the current microphone input channel. The + * input amplifier is automatically turned off when the microphone input is + * disabled. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftChannel The left microphone input channel state. + * @param[in] rightChannel the right microphone input channel state. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input states + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic_on_off(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_MIC_STATE + leftChannel, + const PMIC_AUDIO_INPUT_MIC_STATE + rightChannel); + +/*! + * @brief Return the current state of the microphone inputs. + * + * This function returns the current state (on/off) of the microphone + * input channels. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftChannel The current left microphone input channel + * state. + * @param[out] rightChannel the current right microphone input channel + * state. + * + * @retval PMIC_SUCCESS If the microphone input channel states + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channel states + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic_on_off(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_MIC_STATE * + const leftChannel, + PMIC_AUDIO_INPUT_MIC_STATE * + const rightChannel); + +/*! + * @brief Set the microphone input amplifier mode and gain level. + * + * This function sets the current microphone input amplifier operating mode + * and gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftChannelMode The left microphone input amplifier mode. + * @param[in] leftChannelGain The left microphone input amplifier gain level. + * @param[in] rightChannelMode The right microphone input amplifier mode. + * @param[in] rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifiers were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input amplifier + * modes or gain levels were invalid. + * @retval PMIC_ERROR If the microphone input amplifiers could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_record_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_AMP_MODE + leftChannelMode, + const PMIC_AUDIO_MIC_GAIN + leftChannelGain, + const PMIC_AUDIO_MIC_AMP_MODE + rightChannelMode, + const PMIC_AUDIO_MIC_GAIN + rightChannelGain); + +/*! + * @brief Get the current microphone input amplifier mode and gain level. + * + * This function gets the current microphone input amplifier operating mode + * and gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftChannelMode The left microphone input amplifier mode. + * @param[out] leftChannelGain The left microphone input amplifier gain level. + * @param[out] rightChannelMode The right microphone input amplifier mode. + * @param[out] rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifier modes + * and gain levels were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input amplifier modes + * and gain levels could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_record_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_MIC_AMP_MODE * + const leftChannelMode, + PMIC_AUDIO_MIC_GAIN * + const leftChannelGain, + PMIC_AUDIO_MIC_AMP_MODE * + const rightChannelMode, + PMIC_AUDIO_MIC_GAIN * + const rightChannelGain); + +/*! + * @brief Enable a microphone bias circuit. + * + * This function enables one of the available microphone bias circuits. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] biasCircuit The microphone bias circuit to be enabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit); + +/*! + * @brief Disable a microphone bias circuit. + * + * This function disables one of the available microphone bias circuits. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] biasCircuit The microphone bias circuit to be disabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit); + +/*@}*/ + +/*! + * @name Audio Playback Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Voice CODEC mixer. + * + * This function configures and enables the Voice CODEC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param[in] gainIn The secondary audio channel gain level. + * @param[in] gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + rxSecondaryTimeslot, + const PMIC_AUDIO_VCODEC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_VCODEC_MIX_OUT_GAIN + gainOut); + +/*! + * @brief Disable the Voice CODEC mixer. + * + * This function disables the Voice CODEC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*@}*/ + +/*! + * @name Audio Playback Using the Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo DAC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Stereo DAC mixer. + * + * This function configures and enables the Stereo DAC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param[in] gainIn The secondary audio channel gain level. + * @param[in] gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_stdac_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + rxSecondaryTimeslot, + const PMIC_AUDIO_STDAC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_STDAC_MIX_OUT_GAIN + gainOut); + +/*! + * @brief Disable the Stereo DAC mixer. + * + * This function disables the Stereo DAC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_stdac_disable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*@}*/ + +/*! + * @name Audio Output Section Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio output + * section to support playback. + */ +/*@{*/ + +/*! + * @brief Select the audio output ports. + * + * This function selects the audio output ports to be used. This also enables + * the appropriate output amplifiers. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] port The audio output ports to be used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * acquired. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * acquired. + */ +PMIC_STATUS pmic_audio_output_set_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port); + +/*! + * @brief Deselect/disable the audio output ports. + * + * This function disables the audio output ports that were previously enabled + * by calling pmic_audio_output_set_port(). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] port The audio output ports to be disabled. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * disabled. + */ +PMIC_STATUS pmic_audio_output_clear_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port); + +/*! + * @brief Get the current audio output ports. + * + * This function retrieves the audio output ports that are currently being + * used. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] port The audio output ports currently being used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_output_get_port(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PORT * const port); + +/*! + * @brief Set the gain level for the external stereo inputs. + * + * This function sets the gain levels for the external stereo inputs. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] gain The external stereo input gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STEREO_IN_GAIN + gain); + +/*! + * @brief Get the current gain level for the external stereo inputs. + * + * This function retrieves the current gain levels for the external stereo + * inputs. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] gain The current external stereo input gain + * level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STEREO_IN_GAIN * + const gain); + +/*! + * @brief Set the output PGA gain level. + * + * This function sets the audio output PGA gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] gain The output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_pgaGain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PGA_GAIN + gain); + +/*! + * @brief Get the output PGA gain level. + * + * This function retrieves the current audio output PGA gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] gain The current output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_pgaGain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PGA_GAIN * + const gain); + +/*! + * @brief Enable the output mixer. + * + * This function enables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Disable the output mixer. + * + * This function disables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Configure and enable the output balance amplifiers. + * + * This function configures and enables the output balance amplifiers. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftGain The desired left channel gain level. + * @param[in] rightGain The desired right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifiers were + * successfully configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or gain levels were invalid. + * @retval PMIC_ERROR If the output balance amplifiers could not + * be reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_output_set_balance(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + leftGain, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + rightGain); + +/*! + * @brief Get the current output balance amplifier gain levels. + * + * This function retrieves the current output balance amplifier gain levels. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftGain The current left channel gain level. + * @param[out] rightGain The current right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifier gain levels + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the output balance amplifier gain levels + * could be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_balance(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const leftGain, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const rightGain); + +/*! + * @brief Configure and enable the output mono adder. + * + * This function configures and enables the output mono adder. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] mode The desired mono adder operating mode. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mono adder mode was + * invalid. + * @retval PMIC_ERROR If the mono adder could not be reconfigured + * or enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mono_adder(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MONO_ADDER_MODE + mode); + +/*! + * @brief Disable the output mono adder. + * + * This function disables the output mono adder. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mono_adder(const PMIC_AUDIO_HANDLE + handle); + +/*! + * @brief Configure the mono adder output gain level. + * + * This function configures the mono adder output amplifier gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] gain The desired output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be reconfigured. + */ +PMIC_STATUS pmic_audio_output_set_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + gain); + +/*! + * @brief Get the current mono adder output gain level. + * + * This function retrieves the current mono adder output amplifier gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] gain The current output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + * const gain); + +/*! + * @brief Set various audio output section options. + * + * This function sets one or more audio output section configuration + * options. The currently supported options include whether to disable + * the non-inverting mono speaker output, enabling the loudspeaker common + * bias circuit, enabling detection of headset insertion/removal, and + * whether to automatically disable the headset amplifiers when a headset + * insertion/removal has been detected. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The desired audio output section + * configuration options to be set. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be set. + */ +PMIC_STATUS pmic_audio_output_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG config); + +/*! + * @brief Clear various audio output section options. + * + * This function clears one or more audio output section configuration + * options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The desired audio output section + * configuration options to be cleared. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully cleared. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be cleared. + */ +PMIC_STATUS pmic_audio_output_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG + config); + +/*! + * @brief Get the current audio output section options. + * + * This function retrieves the current audio output section configuration + * option settings. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current audio output section + * configuration option settings. + * + * @retval PMIC_SUCCESS If the current configuration options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the current configuration options + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_CONFIG * + const config); + +/*! + * @brief Enable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function enables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_phantom_ground(void); + +/*! + * @brief Disable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function disables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_phantom_ground(void); + +/*! + * @brief Enable/Disable fm output + * + * This function enables/disables the fm output. + * + * @param[in] enable True to enable and false to disable + * + * @retval PMIC_SUCCESS If the fm output was + * successfully enable or disabled + * @retval PMIC_ERROR If the operation fails + */ +PMIC_STATUS pmic_audio_fm_output_enable(bool enable); + +/*@}*/ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_AUDIO_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pmic_convity.h b/arch/arm/plat-mxc/include/mach/pmic_convity.h new file mode 100644 index 000000000000..62b019112839 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pmic_convity.h @@ -0,0 +1,873 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_CONVITY_H__ +#define __ASM_ARCH_MXC_PMIC_CONVITY_H__ + +/*! + * @defgroup PMIC_CONNECTIVITY PMIC Connectivity Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_convity.h + * @brief External definitions for the PMIC Connectivity Client driver. + * + * The PMIC Connectivity driver and this API were developed to support the + * external connectivity capabilities of several power management ICs that + * are available from Freescale Semiconductor, Inc. + * + * The following operating modes, in terms of external connectivity, are + * supported: + * + * + * + * @ingroup PMIC_CONNECTIVITY + */ + +#include <linux/pmic_status.h> +#include <linux/pmic_external.h> + +/*************************************************************************** + * TYPEDEFS AND ENUMERATIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used for initial access to and + * configuration of the PMIC Connectivity hardware. + */ +/*@{*/ + +#define DEBUG_CONVITY + +/*! + * @typedef PMIC_CONVITY_HANDLE + * @brief Define typedef for a handle to the PMIC Connectivity hardware. + * + * Define a "handle" that is returned when the PMIC Connectivity hardware + * is opened. This handle grants exclusive access to the PMIC Connectivity + * hardware and must be used in all subsequent function calls. When access + * to the PMIC Connectivity hardware is no longer required, then a close + * operation must be done with this handle. The handle is no longer valid + * if the close operation was successful. + */ +typedef long PMIC_CONVITY_HANDLE; + +/*! + * @enum PMIC_CONVITY_MODE + * @brief Select the main Connectivity operating mode. + * + * Defines all possible PMIC Connectivity main operating modes. Only one of + * these modes can be active at a time. + */ +typedef enum { + USB, /*!< Select USB mode (this is also the Reset/Default + mode). */ + RS232, /*!< Select RS-232 mode. for SC55112 */ + RS232_1, /*!< Select RS-232_1 mode. */ + RS232_2, /*!< Select RS-232_2 mode. */ + CEA936_MONO, /*!< Select CE-936 Mono mode . */ + CEA936_STEREO, /*!< Select CE-936 Stereo mode . */ + CEA936_TEST_RIGHT, /*!< Select CE-936 Right Channel Test mode + . */ + CEA936_TEST_LEFT /*!< Select CE-936 Left Channel Test mode + . */ +} PMIC_CONVITY_MODE; + +/*! + * @enum PMIC_CONVITY_EVENTS + * @brief Identify the connectivity events that have been detected and should + * be handled. + * + * Defines all possible PMIC Connectivity events. Multiple events may be + * selected when defining a mask. + */ +typedef enum { + USB_DETECT_4V4_RISE = 1, /*!< Detected 4.4V rising edge. */ + USB_DETECT_4V4_FALL = 2, /*!< Detected 4.4V falling edge. */ + USB_DETECT_2V0_RISE = 4, /*!< Detected 2.0V rising edge. */ + USB_DETECT_2V0_FALL = 8, /*!< Detected 2.0V falling edge. */ + USB_DETECT_0V8_RISE = 16, /*!< Detected 0.8V rising edge. */ + USB_DETECT_0V8_FALL = 32, /*!< Detected 0.8V falling edge. */ + USB_DETECT_MINI_A = 64, /*!< Detected USB mini A plug. */ + USB_DETECT_MINI_B = 128, /*!< Detected USB mini B plug. */ + USB_DETECT_NON_USB_ACCESSORY = 256, /*!< Detected a non-USB connection + . */ + USB_DETECT_FACTORY_MODE = 512, /*!< Detected a factory-mode + connection . */ + USB_DP_HI = 1024, + + USB_DM_HI = 2048 +} PMIC_CONVITY_EVENTS; + +/*! + * @typedef PMIC_CONVITY_CALLBACK + * @brief Typedef for PMIC Connectivity event notification callback function. + * + * Define a typedef for the PMIC Connectivity event notification callback + * function. The signalled events are passed to the function as the first + * argument. The callback function should then process whatever events it + * can and then return the set of unhandled events (if any). + */ +typedef void (*PMIC_CONVITY_CALLBACK) (const PMIC_CONVITY_EVENTS event); + +/*@}*/ + +/*! + * @name USB and USB On-The-Go Mode-specific Typedefs and Enumerations + * Typedefs and enumerations that are used only for setting up and controlling + * the USB and USB On-The-Go modes of operation. + */ +/*@{*/ + +/*! + * @enum PMIC_CONVITY_USB_DEVICE_TYPE + * @brief Select the USB device type (either A or B). + * + * Defines all possible USB device types. This must match the physical + * connector being used. + */ +typedef enum { + USB_A_DEVICE, + USB_B_DEVICE +} PMIC_CONVITY_USB_DEVICE_TYPE; + +/*! + * @enum PMIC_CONVITY_USB_SPEED + * @brief Select the USB transceiver operating speed. + * + * Defines all possible USB transceiver operating speeds. Only one + * speed setting may be used at a time. + */ +typedef enum { + USB_LOW_SPEED, /*!< Select 1.5 Mbps. */ + USB_FULL_SPEED, /*!< Select 12 Mbps. */ + USB_HIGH_SPEED /*!< Select 480 Mbps <b>(currently + not supported)</b>. */ +} PMIC_CONVITY_USB_SPEED; + +/*! + * @enum PMIC_CONVITY_USB_MODE + * @brief Select the USB transceiver operating mode. + * + * Defines all possible USB transceiver operating modes. Only one + * mode may be used at a time. The selected mode, in combination with + * the USB bus speed, determines the selection of pull-up and pull-down + * resistors. + */ +typedef enum { + USB_HOST, + USB_PERIPHERAL +} PMIC_CONVITY_USB_MODE; + +/*! + * @enum PMIC_CONVITY_USB_POWER_IN + * @brief Select the USB transceiver's power regulator input source. + * + * Defines all possible input power sources for the USB transceiver power + * regulator. Only one power supply source may be selected at a time. + */ +typedef enum { + + USB_POWER_INTERNAL_BOOST, /*!< Select internal power source + with boost. */ + + USB_POWER_VBUS, /*!< Select VBUS power source. */ + + USB_POWER_INTERNAL /*!< Select internal power source + . */ +} PMIC_CONVITY_USB_POWER_IN; + +/*! + * @enum PMIC_CONVITY_USB_POWER_OUT + * @brief Select the USB transceiver power regulator output voltage. + * + * Defines all possible output voltages for the USB transceiver power + * regulator. Only one power output voltage level may be selected at + * a time. + */ +typedef enum { + USB_POWER_2V775, /*!< Select 2.775V output voltage + . */ + USB_POWER_3V3 /*!< Select 3.3V output voltage. */ +} PMIC_CONVITY_USB_POWER_OUT; + +/*! + * @enum PMIC_CONVITY_USB_TRANSCEIVER_MODE + * @brief Select the USB transceiver operating mode. + * + * Defines all valid USB transceiver operating modes. Only one of the + * following USB transceiver modes may be selected at a time. + */ +typedef enum { + USB_TRANSCEIVER_OFF, /*!< USB transceiver currently off + . */ + USB_SINGLE_ENDED_UNIDIR, /*!< Select Single-ended + unidirectional transmit mode. */ + USB_SINGLE_ENDED_UNIDIR_TX, /*!< Select Single-ended + unidirectional transmit mode. */ + USB_SINGLE_ENDED_UNIDIR_RX, /*!< Select Single-ended + unidirectional receive mode. */ + USB_SINGLE_ENDED_BIDIR, /*!< Select Single-ended + bidirectional transmit mode. */ + USB_SINGLE_ENDED_LOW, /*!< Select USB SE0 mode. */ + USB_DIFFERENTIAL_UNIDIR_TX, /*!< Select Differential + unidirectional transmit mode + . */ + USB_DIFFERENTIAL_UNIDIR, /*!< Select Differential + unidirectional transmit mode + . */ + + USB_DIFFERENTIAL_UNIDIR_RX, /*!< Select Differential + unidirectional receive mode. */ + USB_DIFFERENTIAL_BIDIR, /*!< Select Differential + bidirectional transmit mode + */ + USB_SUSPEND_ON, /*!< Select Suspend mode. */ + USB_SUSPEND_OFF, /*!< Terminate Suspend mode. */ + USB_OTG_SRP_DLP_START, /*!< Start USB On-The-Go Session + Request Protocol using Data + Line Pulsing. */ + USB_OTG_SRP_DLP_STOP /*!< Terminate USB On-The-Go Session + Request Protocol using Data + Line Pulsing. */ +} PMIC_CONVITY_USB_TRANSCEIVER_MODE; + +/*! + * @enum PMIC_CONVITY_USB_OTG_CONFIG + * @brief Select the USB On-The-Go configuration options. + * + * Defines all possible USB On-The-Go configuration options. Multiple + * configuration options may be selected at the same time. However, only one + * VBUS current limit may be selected at a time. Selecting more than one + * VBUS current limit will result in undefined and implementation-dependent + * behavior. + */ +typedef enum { + USB_OTG_SE0CONN = 0x00001, /*!< Enable automatic + connection of a pull-up + resistor to VUSB when the + SE0 condition is detected. */ + USB_OTG_DLP_SRP = 0x00002, /*!< Enable use of the hardware + timer to control the + duration of the data line + pulse during the session + request protocol. */ + USB_PULL_OVERRIDE = 0x00004, /*!< Enable automatic disconnect + of pull-up and pull-down + resistors when transmitter + is enabled. */ + + USB_DP150K_PU = 0x00008, + + USB_VBUS_CURRENT_LIMIT_HIGH = 0x00010, /*!< Select current limit to 200mA + for VBUS regulator. */ + USB_VBUS_CURRENT_LIMIT_LOW = 0x00020, /*!< Select low current limit + for VBUS regulator. */ + USB_VBUS_CURRENT_LIMIT_LOW_10MS = 0x00040, /*!< Select low current limit + for VBUS regulator for + 10 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_20MS = 0x00080, /*!< Select low current limit + for VBUS regulator for + 20 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_30MS = 0x00100, /*!< Select low current limit + for VBUS regulator for + 30 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_40MS = 0x00200, /*!< Select low current limit + for VBUS regulator for + 40 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_50MS = 0x00400, /*!< Select low current limit + for VBUS regulator for + 50 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_60MS = 0x00800, /*!< Select low current limit + for VBUS regulator for + 60 ms . */ + + USB_VBUS_PULLDOWN = 0x01000, /*!< Enable VBUS pull-down. */ + + USB_USBCNTRL = 0x02000, + + USB_UDP_PD = 0x04000, + + USB_UDM_PD = 0x08000, + + USB_PU = 0x10000, + + USBXCVREN = 0x20000 +} PMIC_CONVITY_USB_OTG_CONFIG; +/*@}*/ + +/*! + * @name RS-232 Mode-specific Typedefs and Enumerations + * Typedefs and enumerations that are used only for setting up and controlling + * the RS-232 mode of operation. + */ +/*@{*/ + +/*! + * @enum PMIC_CONVITY_RS232_EXTERNAL + * @brief Select the RS-232 transceiver external connections. + * + * Defines all valid RS-232 transceiver external RX/TX connection options. + * Only one connection mode may be selected at a time. + */ +typedef enum { + RS232_TX_UDM_RX_UDP, /*!< Select RS-232 TX on UDM */ + RS232_TX_UDP_RX_UDM, /*!< Select RS-232 TX on UDP + . */ + RS232_TX_RX_EXTERNAL_DEFAULT /*!< Use power on default. */ +} PMIC_CONVITY_RS232_EXTERNAL; + +/*! + * @enum PMIC_CONVITY_RS232_INTERNAL + * @brief Select the RS-232 transceiver internal connections. + * + * Defines all valid RS-232 transceiver internal RX/TX connection options. + * Only one connection mode can be selected at a time. + */ +typedef enum { + RS232_TX_USE0VM_RX_UDATVP, /*!< Select RS-232 TX from USE0VM + . */ + RS232_TX_UDATVP_RX_URXVM, /*!< Select RS-232 TX from UDATVP + . */ + RS232_TX_UTXDI_RX_URXDO, /*!< Select RS-232 TX from UTXDI + . */ + RS232_TX_RX_INTERNAL_DEFAULT /*!< Use power on default. */ +} PMIC_CONVITY_RS232_INTERNAL; + +/*@}*/ + +/*! + * @name CEA-936 Mode-specific Typedefs and Enumerations + * Typedefs and enumerations that are used only for setting up and controlling + * the CEA-936 mode of operation. + */ +/*@{*/ + +/*! + * @enum PMIC_CONVITY_CEA936_EXIT_SIGNAL + * @brief Select the CEA-936 mode exit signal. + * + * Defines all valid CEA-936 connection termination signals. Only one + * termination signal can be selected at a time. + */ +typedef enum { + CEA936_UID_NO_PULLDOWN, /*!< No UID pull-down . */ + CEA936_UID_PULLDOWN_6MS, /*!< UID pull-down for 6 ms (+/-2 ms) + . */ + CEA936_UID_PULLDOWN, /*!< UID pulled down . */ + CEA936_UDMPULSE /*!< UDM pulsed . */ +} PMIC_CONVITY_CEA936_EXIT_SIGNAL; + +/*@}*/ + +/*************************************************************************** + * PMIC API DEFINITIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Connectivity + * hardware. + */ +/*@{*/ + +/*! + * @brief Request exclusive access to the PMIC Connectivity hardware. + * + * Attempt to open and gain exclusive access to the PMIC Connectivity + * hardware. An initial operating mode (e.g., USB or RS-232) must also + * be specified. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls. The + * same handle must also be used in the close call when use of the PMIC + * connectivity hardware is no longer required. + * + * The open request will fail if another thread has already obtained the + * device handle and has not yet called pmic_convity_close() with it. + * + * @param handle Device handle to be used for subsequent PMIC + * Connectivity API calls. + * @param mode Initial connectivity operating mode. + * + * @retval PMIC_SUCCESS If the open request was successful + * @retval PMIC_ERROR If the connectivity hardware cannot be opened. + */ +PMIC_STATUS pmic_convity_open(PMIC_CONVITY_HANDLE * const handle, + const PMIC_CONVITY_MODE mode); + +/*! + * @brief Terminate further access to the PMIC Connectivity hardware. + * + * Terminate further access to the PMIC Connectivity hardware. This also + * allows another thread to successfully call pmic_convity_open() to gain + * access. + * + * @param handle Device handle from open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_close(const PMIC_CONVITY_HANDLE handle); + +/*! + * @brief Set the PMIC Connectivity main operating mode. + * + * Change the current operating mode of the PMIC Connectivity hardware. + * The available connectivity operating modes are hardware-dependent and + * consists of one or more of the following: USB (including USB On-the-Go), + * RS-232, and CEA-936. Requesting an operating mode that is not supported + * by the PMIC hardware will return PMIC_NOT_SUPPORTED. + * + * @param handle Device handle from open() call. + * @param mode Desired operating mode. + * + * @retval PMIC_SUCCESS If the requested mode was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the PMIC hardware does not support + * the desired operating mode. + */ +PMIC_STATUS pmic_convity_set_mode(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_MODE mode); + +/*! + * @brief Get the current PMIC Connectivity main operating mode. + * + * Get the current operating mode for the PMIC Connectivity hardware. + * + * @param handle Device handle from open() call. + * @param mode The current PMIC Connectivity operating mode. + * + * @retval PMIC_SUCCESS If the requested mode was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_get_mode(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_MODE * const mode); + +/*! + * @brief Reset the Connectivity hardware to it's power on state. + * + * Restore all registers to the initial power-on/reset state. + * + * @param handle Device handle from open() call. + * + * @retval PMIC_SUCCESS If the reset was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_reset(const PMIC_CONVITY_HANDLE handle); + +/*! + * @brief Set the Connectivity callback function. + * + * Register a callback function that will be used to signal PMIC Connectivity + * events. For example, the USB subsystem should register a callback function + * in order to be notified of device connect/disconnect events. Note, however, + * that non-USB events may also be signalled depending upon the PMIC hardware + * capabilities. Therefore, the callback function must be able to properly + * handle all of the possible events if support for non-USB peripherals is + * also to be included. + * + * @param handle Device handle from open() call. + * @param func A pointer to the callback function. + * @param eventMask A mask selecting events to be notified. + * + * @retval PMIC_SUCCESS If the callback was successfully registered. + * @retval PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid. + */ +PMIC_STATUS pmic_convity_set_callback(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_CALLBACK func, + const PMIC_CONVITY_EVENTS eventMask); + +/*! + * @brief Deregisters the existing Connectivity callback function. + * + * Deregister the callback function that was previously registered by calling + * pmic_convity_set_callback(). + * + * @param handle Device handle from open() call. + * + * @retval PMIC_SUCCESS If the callback was successfully deregistered. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_clear_callback(const PMIC_CONVITY_HANDLE handle); + +/*! + * @brief Get the current Connectivity callback function settings. + * + * Get the current callback function and event mask. + * + * @param handle Device handle from open() call. + * @param func The current callback function. + * @param eventMask The current event selection mask. + * + * @retval PMIC_SUCCESS If the callback information was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_get_callback(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_CALLBACK * const func, + PMIC_CONVITY_EVENTS * const eventMask); + +/*@}*/ + +/***************************************************************************/ + +/*! + * @name USB and USB On-The-Go APIs + * USB Connectivity mode-specific configuration and setup functions. + */ +/*@{*/ + +/*! + * @brief Set the USB transceiver's operating speed. + * + * Set the USB transceiver speed. + * + * @param handle Device handle from open() call. + * @param speed The desired USB transceiver speed. + * + * @retval PMIC_SUCCESS If the transceiver speed was successfully + * set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the high speed (480 Mbps) mode is + * requested. + */ +PMIC_STATUS pmic_convity_usb_set_speed(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_SPEED speed); + +/*! + * This function enables/disables VUSB and VBUS output. + * This API configures the VUSBEN and VBUSEN bits of USB register + * + * @param handle Device handle from open() call. + * @param out_type true, for VUSB + * false, for VBUS + * @param out if true, output is enabled + * if false, output is disabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_convity_set_output(const PMIC_CONVITY_HANDLE handle, + bool out_type, bool out); + +/*! + * @brief Get the USB transceiver's operating speed. + * + * Get the USB transceiver speed. + * + * @param handle Device handle from open() call. + * @param speed The current USB transceiver speed. + * @param mode The current USB transceiver mode. + * + * @retval PMIC_SUCCESS If the transceiver speed was successfully + * set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * obtained + */ +PMIC_STATUS pmic_convity_usb_get_speed(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_SPEED * const speed, + PMIC_CONVITY_USB_MODE * const mode); + +/*! + * @brief Set the USB transceiver's power supply configuration. + * + * Set the USB transceiver's power supply configuration. + * + * @param handle Device handle from open() call. + * @param pwrin USB transceiver regulator input power source. + * @param pwrout USB transceiver regulator output power level. + * + * @retval PMIC_SUCCESS If the USB transceiver's power supply + * configuration was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the PMIC hardware does not support + * the desired configuration. + */ +PMIC_STATUS pmic_convity_usb_set_power_source(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_POWER_IN + pwrin, + const PMIC_CONVITY_USB_POWER_OUT + pwrout); + +/*! + * @brief Get the USB transceiver's power supply configuration. + * + * Get the USB transceiver's current power supply configuration. + * + * @param handle Device handle from open() call. + * @param pwrin USB transceiver regulator input power source + * @param pwrout USB transceiver regulator output power level + * + * @retval PMIC_SUCCESS If the USB transceiver's power supply + * configuration was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_usb_get_power_source(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_POWER_IN * + const pwrin, + PMIC_CONVITY_USB_POWER_OUT * + const pwrout); + +/*! + * @brief Set the current USB transceiver operating mode. + * + * Set the USB transceiver's operating mode. + * + * @param handle Device handle from open() call. + * @param mode Desired operating mode. + * + * @retval PMIC_SUCCESS If the USB transceiver's operating mode + * was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB transceiver mode is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_set_xcvr(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_TRANSCEIVER_MODE + mode); + +/*! + * @brief Get the current USB transceiver operating mode. + * + * Get the USB transceiver's current operating mode. + * + * @param handle Device handle from open() call. + * @param mode Current operating mode. + * + * @retval PMIC_SUCCESS If the USB transceiver's operating mode + * was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_usb_get_xcvr(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_TRANSCEIVER_MODE * + const mode); + +/*! + * @brief Set the current USB On-The-Go data line pulse duration (ms). + * + * Set the Data Line Pulse duration (in milliseconds) for the USB OTG + * Session Request Protocol. + * + * Note that for mc13783 the duration is fixed at 7.5 ms and calling this + * function will simply return PMIC_NOT_SUPPORTED. + * + * @param handle Device handle from open() call. + * @param duration The data line pulse duration (ms). + * + * @retval PMIC_SUCCESS If the pulse duration was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or the data line pulse + * duration is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired data line pulse duration + * is not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_set_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + const unsigned int duration); + +/*! + * @brief Get the current USB On-The-Go data line pulse duration (ms). + * + * Get the current Data Line Pulse duration (in milliseconds) for the USB + * OTG Session Request Protocol. + * + * Note that the Data Line Pulse duration is fixed at 7.5 ms for the mc13783 + * PMIC. Therefore, calling this function while using the mc13783 PMIC will + * simply return PMIC_NOT_SUPPORTED. + * + * @param handle Device handle from open() call. + * @param duration The data line pulse duration (ms). + * + * @retval PMIC_SUCCESS If the pulse duration was successfully + * obtained. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If called using the mc13783 PMIC. + */ +PMIC_STATUS pmic_convity_usb_otg_get_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + unsigned int *const duration); + +/*! + * @brief Start the USB OTG Host Negotiation Protocol (HNP) process. + * + * This function must be called during the start of the HNP process to + * properly reconfigure the pull-up resistor on the D+ line for both + * the USB A and B devices. + * + * @param handle device handle from open() call + * @param deviceType the USB device type (either A or B) + * + * @return PMIC_SUCCESS if the HNP was successfully started + */ +PMIC_STATUS pmic_convity_usb_otg_begin_hnp(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_DEVICE_TYPE + deviceType); + +/*! + * @brief Complete the USB OTG Host Negotiation Protocol (HNP) process. + * + * This function must be called during the end of the HNP process to + * properly reconfigure the pull-up resistor on the D+ line for both + * the USB A and B devices. + * + * @param handle device handle from open() call + * @param deviceType the USB device type (either A or B) + * + * @return PMIC_SUCCESS if the HNP was successfully ended + */ +PMIC_STATUS pmic_convity_usb_otg_end_hnp(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_DEVICE_TYPE + deviceType); + +/*! + * @brief Set the current USB On-The-Go configuration. + * + * Set the USB On-The-Go (OTG) configuration. Multiple configuration settings + * may be OR'd together in a single call. However, selecting conflicting + * settings (e.g., multiple VBUS current limits) will result in undefined + * behavior. + * + * @param handle Device handle from open() call. + * @param cfg Desired USB OTG configuration. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB OTG configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg); + +/*! + * @brief Clear the current USB On-The-Go configuration. + * + * Clears the USB On-The-Go (OTG) configuration. Multiple configuration settings + * may be OR'd together in a single call. However, selecting conflicting + * settings (e.g., multiple VBUS current limits) will result in undefined + * behavior. + * + * @param handle Device handle from open() call. + * @param cfg USB OTG configuration settings to be cleared. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * cleared. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB OTG configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_clear_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg); + +/*! + * @brief Get the current USB On-The-Go configuration. + * + * Get the current USB On-The-Go (OTG) configuration. + * + * @param handle Device handle from open() call. + * @param cfg The current USB OTG configuration. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_usb_otg_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_OTG_CONFIG * + const cfg); + +/*@}*/ + +/***************************************************************************/ + +/*! + * @name RS-232 APIs + * RS-232 Connectivity mode-specific configuration and setup functions. + */ +/*@{*/ + +/*! + * @brief Set the current RS-232 operating configuration. + * + * Set the connectivity interface to the selected RS-232 operating mode. + * Note that the RS-232 operating mode will be automatically overridden + * if the USB_EN is asserted at any time (e.g., when a USB device is + * attached). + * + * @param handle Device handle from open() call. + * @param cfgInternal RS-232 transceiver internal connections. + * @param cfgExternal RS-232 transceiver external connections. + * + * @retval PMIC_SUCCESS If the requested RS-232 mode was set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired RS-232 configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_rs232_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_RS232_INTERNAL + cfgInternal, + const PMIC_CONVITY_RS232_EXTERNAL + cfgExternal); + +/*! + * @brief Get the current RS-232 operating configuration. + * + * Get the connectivity interface's current RS-232 operating mode. + * + * @param handle Device handle from open() call. + * @param cfgInternal RS-232 transceiver internal connections. + * @param cfgExternal RS-232 transceiver external connections. + * + * @retval PMIC_SUCCESS If the requested RS-232 mode was retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_rs232_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_RS232_INTERNAL * + const cfgInternal, + PMIC_CONVITY_RS232_EXTERNAL * + const cfgExternal); + +/***************************************************************************/ + +/*@}*/ + +/*! + * @name CE-936 APIs + * CE-936 Connectivity mode-specific configuration and setup functions. + */ +/*@{*/ + +/*! + * @brief Send a signal to exit CEA-936 mode. + * + * Signal the attached device to exit the current CEA-936 operating mode. + * Returns an error if the current operating mode is not CEA-936. + * + * @param handle Device handle from open() call. + * @param signal Type of exit signal to be sent. + * + * @retval PMIC_SUCCESS If the CEA-936 exit mode signal was sent. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired CEA-936 exit mode signal + * is not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_cea936_exit_signal(const PMIC_CONVITY_HANDLE handle, + const + PMIC_CONVITY_CEA936_EXIT_SIGNAL + signal); + +/*@}*/ + +#endif /* __ASM_ARCH_MXC_PMIC_CONVITY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pmic_power.h b/arch/arm/plat-mxc/include/mach/pmic_power.h new file mode 100644 index 000000000000..68b8e74e3565 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pmic_power.h @@ -0,0 +1,1358 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_POWER_H__ +#define __ASM_ARCH_MXC_PMIC_POWER_H__ + +/*! + * @defgroup PMIC_POWER PMIC Power Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_power.h + * @brief This is the header of PMIC power driver. + * + * @ingroup PMIC_POWER + */ + +#include <linux/ioctl.h> +#include <linux/pmic_status.h> +#include <linux/pmic_external.h> + +/*! + * @name IOCTL user space interface + */ +/*! @{ */ + +/*! + * Turn on a regulator. + */ +#define PMIC_REGULATOR_ON _IOWR('p', 0xf0, int) + +/*! + * Turn off a regulator. + */ +#define PMIC_REGULATOR_OFF _IOWR('p', 0xf1, int) + +/*! + * Set regulator configuration. + */ +#define PMIC_REGULATOR_SET_CONFIG _IOWR('p', 0xf2, int) + +/*! + * Get regulator configuration. + */ +#define PMIC_REGULATOR_GET_CONFIG _IOWR('p', 0xf3, int) + +/*! + * Miscellaneous Power Test. + */ +#define PMIC_POWER_CHECK_MISC _IOWR('p', 0xf4, int) + +/*! @} */ + +/*! + * This enumeration define all power interrupts + */ +typedef enum { + /*! + * BP turn on threshold detection + */ + PWR_IT_BPONI = 0, + /*! + * End of life / low battery detect + */ + PWR_IT_LOBATLI, + /*! + * Low battery warning + */ + PWR_IT_LOBATHI, + /*! + * ON1B event + */ + PWR_IT_ONOFD1I, + /*! + * ON2B event + */ + PWR_IT_ONOFD2I, + /*! + * ON3B event + */ + PWR_IT_ONOFD3I, + /*! + * System reset + */ + PWR_IT_SYSRSTI, + /*! + * Power ready + */ + PWR_IT_PWRRDYI, + /*! + * Power cut event + */ + PWR_IT_PCI, + /*! + * Warm start event + */ + PWR_IT_WARMI, + /*! + * Memory hold event + */ +} t_pwr_int; + +/*! + * VHOLD regulator output voltage setting. + */ +typedef enum { + VH_1_875V, /*!< 1.875V */ + VH_2_5V, /*!< 2.5V */ + VH_1_55V, /*!< 1.55V */ + VH_PASSTHROUGH, /*!< Pass-through mode */ +} t_vhold_voltage; + +/*! + * PMIC power control configuration. + */ + +typedef struct { + bool pc_enable; /*!< Power cut enable */ + unsigned char pc_timer; /*!< Power cut timer value */ + bool pc_count_enable; /*!< Power cut counter enable, + If TURE, Power cuts are disabled + when pc_count > pc_max_count; + If FALSE, Power cuts are not + disabled when + pc_count > pc_max_count */ + unsigned char pc_count; /*!< Power cut count */ + unsigned char pc_max_count; /*!< Power cut maximum count */ + bool warm_enable; /*!< User Off state enable */ + bool user_off_pc; /*!< Automatic transition to user off + during power cut */ + bool clk_32k_enable; /*!< 32 kHz output buffer enable + during memory hold */ + bool clk_32k_user_off; /*!< Keeps the CLK32KMCU active during + user off power cut modes */ + bool en_vbkup1; /*!< enable VBKUP1 regulator */ + bool auto_en_vbkup1; /*!< automatically enable VBKUP1 + regulator in the memory hold + and user of modes */ + t_vhold_voltage vhold_voltage; /*!< output voltage for VBKUP1 */ + bool en_vbkup2; /*!< enable VBKUP2 regulator */ + bool auto_en_vbkup2; /*!< automatically enable VBKUP2 + regulator in the memory hold + and user of modes */ + t_vhold_voltage vhold_voltage2; /*!< output voltage for VBKUP2 */ + unsigned char mem_timer; /*!< duration of the memory hold + timer */ + bool mem_allon; /*!< memory hold timer infinity mode, + If TRUE, the memory hold timer + will be set to infinity and + the mem_timer filed will be + ignored */ +} t_pc_config; + +/*! + * brief PMIC regulators. + */ + +typedef enum { + SW_SW1A = 0, /*!< SW1A or SW1 */ + SW_SW1B, /*!< SW1B */ + SW_SW2A, /*!< SW2A or SW2 */ + SW_SW2B, /*!< SW2B */ + SW_SW3, /*!< SW3 */ + SW_PLL, /*!< PLL */ + REGU_VAUDIO, /*!< VAUDIO */ + REGU_VIOHI, /*!< VIOHI */ + REGU_VIOLO, /*!< VIOLO */ + REGU_VDIG, /*!< VDIG */ + REGU_VGEN, /*!< VGEN */ + REGU_VRFDIG, /*!< VRFDIG */ + REGU_VRFREF, /*!< VRFREF */ + REGU_VRFCP, /*!< VRFCP */ + REGU_VSIM, /*!< VSIM */ + REGU_VESIM, /*!< VESIM */ + REGU_VCAM, /*!< VCAM */ + REGU_VRFBG, /*!< VRFBG */ + REGU_VVIB, /*!< VVIB */ + REGU_VRF1, /*!< VRF1 */ + REGU_VRF2, /*!< VRF2 */ + REGU_VMMC1, /*!< VMMC1 or VMMC */ + REGU_VMMC2, /*!< VMMC2 */ + REGU_GPO1, /*!< GPIO1 */ + REGU_GPO2, /*!< GPO2 */ + REGU_GPO3, /*!< GPO3 */ + REGU_GPO4, /*!< GPO4 */ + REGU_V1, /*!< V1 */ + REGU_V2, /*!< V2 */ + REGU_V3, /*!< V3 */ + REGU_V4, /*!< V4 */ +} t_pmic_regulator; + +/*! + * @enum t_pmic_regulator_voltage_sw1 + * @brief PMIC Switch mode regulator SW1 output voltages. + */ + +typedef enum { + SW1_1V = 0, /*!< 1.0 V */ + SW1_1_1V, /*!< 1.1 V */ + SW1_1_2V, /*!< 1.2 V */ + SW1_1_3V, /*!< 1.3 V */ + SW1_1_4V, /*!< 1.4 V */ + SW1_1_55V, /*!< 1.55 V */ + SW1_1_625V, /*!< 1.625 V */ + SW1_1_875V, /*!< 1.875 V */ +} t_pmic_regulator_voltage_sw1; + +/*! + * @enum t_pmic_regulator_voltage_sw1a + * @brief PMIC regulator SW1A output voltage. + */ +typedef enum { + SW1A_0_9V = 0, /*!< 0.900 V */ + SW1A_0_925V, /*!< 0.925 V */ + SW1A_0_95V, /*!< 0.950 V */ + SW1A_0_975V, /*!< 0.975 V */ + SW1A_1V, /*!< 1.000 V */ + SW1A_1_025V, /*!< 1.025 V */ + SW1A_1_05V, /*!< 1.050 V */ + SW1A_1_075V, /*!< 1.075 V */ + SW1A_1_1V, /*!< 1.100 V */ + SW1A_1_125V, /*!< 1.125 V */ + SW1A_1_15V, /*!< 1.150 V */ + SW1A_1_175V, /*!< 1.175 V */ + SW1A_1_2V, /*!< 1.200 V */ + SW1A_1_225V, /*!< 1.225 V */ + SW1A_1_25V, /*!< 1.250 V */ + SW1A_1_275V, /*!< 1.275 V */ + SW1A_1_3V, /*!< 1.300 V */ + SW1A_1_325V, /*!< 1.325 V */ + SW1A_1_35V, /*!< 1.350 V */ + SW1A_1_375V, /*!< 1.375 V */ + SW1A_1_4V, /*!< 1.400 V */ + SW1A_1_425V, /*!< 1.425 V */ + SW1A_1_45V, /*!< 1.450 V */ + SW1A_1_475V, /*!< 1.475 V */ + SW1A_1_5V, /*!< 1.500 V */ + SW1A_1_525V, /*!< 1.525 V */ + SW1A_1_55V, /*!< 1.550 V */ + SW1A_1_575V, /*!< 1.575 V */ + SW1A_1_6V, /*!< 1.600 V */ + SW1A_1_625V, /*!< 1.625 V */ + SW1A_1_65V, /*!< 1.650 V */ + SW1A_1_675V, /*!< 1.675 V */ + SW1A_1_7V, /*!< 1.700 V */ + SW1A_1_8V = 36, /*!< 1.800 V */ + SW1A_1_85V = 40, /*!< 1.850 V */ + SW1A_2V = 44, /*!< 2_000 V */ + SW1A_2_1V = 48, /*!< 2_100 V */ + SW1A_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw1a; + +/*! + * @enum t_pmic_regulator_voltage_sw1b + * @brief PMIC regulator SW1B output voltage. + */ +typedef enum { + SW1B_0_9V = 0, /*!< 0.900 V */ + SW1B_0_925V, /*!< 0.925 V */ + SW1B_0_95V, /*!< 0.950 V */ + SW1B_0_975V, /*!< 0.975 V */ + SW1B_1V, /*!< 1.000 V */ + SW1B_1_025V, /*!< 1.025 V */ + SW1B_1_05V, /*!< 1.050 V */ + SW1B_1_075V, /*!< 1.075 V */ + SW1B_1_1V, /*!< 1.100 V */ + SW1B_1_125V, /*!< 1.125 V */ + SW1B_1_15V, /*!< 1.150 V */ + SW1B_1_175V, /*!< 1.175 V */ + SW1B_1_2V, /*!< 1.200 V */ + SW1B_1_225V, /*!< 1.225 V */ + SW1B_1_25V, /*!< 1.250 V */ + SW1B_1_275V, /*!< 1.275 V */ + SW1B_1_3V, /*!< 1.300 V */ + SW1B_1_325V, /*!< 1.325 V */ + SW1B_1_35V, /*!< 1.350 V */ + SW1B_1_375V, /*!< 1.375 V */ + SW1B_1_4V, /*!< 1.400 V */ + SW1B_1_425V, /*!< 1.425 V */ + SW1B_1_45V, /*!< 1.450 V */ + SW1B_1_475V, /*!< 1.475 V */ + SW1B_1_5V, /*!< 1.500 V */ + SW1B_1_525V, /*!< 1.525 V */ + SW1B_1_55V, /*!< 1.550 V */ + SW1B_1_575V, /*!< 1.575 V */ + SW1B_1_6V, /*!< 1.600 V */ + SW1B_1_625V, /*!< 1.625 V */ + SW1B_1_65V, /*!< 1.650 V */ + SW1B_1_675V, /*!< 1.675 V */ + SW1B_1_7V, /*!< 1.700 V */ + SW1B_1_8V = 36, /*!< 1.800 V */ + SW1B_1_85V = 40, /*!< 1.850 V */ + SW1B_2V = 44, /*!< 2_000 V */ + SW1B_2_1V = 48, /*!< 2_100 V */ + SW1B_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw1b; + +/*! + * @enum t_pmic_regulator_voltage_sw2 + * @brief PMIC Switch mode regulator SW2 output voltages. + */ +typedef enum { + SW2_1V = 0, /*!< 1.0 V */ + SW2_1_1V, /*!< 1.1 V */ + SW2_1_2V, /*!< 1.2 V */ + SW2_1_3V, /*!< 1.3 V */ + SW2_1_4V, /*!< 1.4 V */ + SW2_1_55V, /*!< 1.55 V */ + SW2_1_625V, /*!< 1.625 V */ + SW2_1_875V, /*!< 1.875 V */ +} t_pmic_regulator_voltage_sw2; + +/*! + * @enum t_pmic_regulator_voltage_sw2a + * @brief PMIC regulator SW2A output voltage. + */ +typedef enum { + SW2A_0_9V = 0, /*!< 0.900 V */ + SW2A_0_925V, /*!< 0.925 V */ + SW2A_0_95V, /*!< 0.950 V */ + SW2A_0_975V, /*!< 0.975 V */ + SW2A_1V, /*!< 1.000 V */ + SW2A_1_025V, /*!< 1.025 V */ + SW2A_1_05V, /*!< 1.050 V */ + SW2A_1_075V, /*!< 1.075 V */ + SW2A_1_1V, /*!< 1.100 V */ + SW2A_1_125V, /*!< 1.125 V */ + SW2A_1_15V, /*!< 1.150 V */ + SW2A_1_175V, /*!< 1.175 V */ + SW2A_1_2V, /*!< 1.200 V */ + SW2A_1_225V, /*!< 1.225 V */ + SW2A_1_25V, /*!< 1.250 V */ + SW2A_1_275V, /*!< 1.275 V */ + SW2A_1_3V, /*!< 1.300 V */ + SW2A_1_325V, /*!< 1.325 V */ + SW2A_1_35V, /*!< 1.350 V */ + SW2A_1_375V, /*!< 1.375 V */ + SW2A_1_4V, /*!< 1.400 V */ + SW2A_1_425V, /*!< 1.425 V */ + SW2A_1_45V, /*!< 1.450 V */ + SW2A_1_475V, /*!< 1.475 V */ + SW2A_1_5V, /*!< 1.500 V */ + SW2A_1_525V, /*!< 1.525 V */ + SW2A_1_55V, /*!< 1.550 V */ + SW2A_1_575V, /*!< 1.575 V */ + SW2A_1_6V, /*!< 1.600 V */ + SW2A_1_625V, /*!< 1.625 V */ + SW2A_1_65V, /*!< 1.650 V */ + SW2A_1_675V, /*!< 1.675 V */ + SW2A_1_7V, /*!< 1.700 V */ + SW2A_1_8V = 36, /*!< 1.800 V */ + SW2A_1_9V = 40, /*!< 1.900 V */ + SW2A_2V = 44, /*!< 2_000 V */ + SW2A_2_1V = 48, /*!< 2_100 V */ + SW2A_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw2a; + +/*! + * @enum t_pmic_regulator_voltage_sw2b + * @brief PMIC regulator SW2B output voltage. + */ +typedef enum { + SW2B_0_9V = 0, /*!< 0.900 V */ + SW2B_0_925V, /*!< 0.925 V */ + SW2B_0_95V, /*!< 0.950 V */ + SW2B_0_975V, /*!< 0.975 V */ + SW2B_1V, /*!< 1.000 V */ + SW2B_1_025V, /*!< 1.025 V */ + SW2B_1_05V, /*!< 1.050 V */ + SW2B_1_075V, /*!< 1.075 V */ + SW2B_1_1V, /*!< 1.100 V */ + SW2B_1_125V, /*!< 1.125 V */ + SW2B_1_15V, /*!< 1.150 V */ + SW2B_1_175V, /*!< 1.175 V */ + SW2B_1_2V, /*!< 1.200 V */ + SW2B_1_225V, /*!< 1.225 V */ + SW2B_1_25V, /*!< 1.250 V */ + SW2B_1_275V, /*!< 1.275 V */ + SW2B_1_3V, /*!< 1.300 V */ + SW2B_1_325V, /*!< 1.325 V */ + SW2B_1_35V, /*!< 1.350 V */ + SW2B_1_375V, /*!< 1.375 V */ + SW2B_1_4V, /*!< 1.400 V */ + SW2B_1_425V, /*!< 1.425 V */ + SW2B_1_45V, /*!< 1.450 V */ + SW2B_1_475V, /*!< 1.475 V */ + SW2B_1_5V, /*!< 1.500 V */ + SW2B_1_525V, /*!< 1.525 V */ + SW2B_1_55V, /*!< 1.550 V */ + SW2B_1_575V, /*!< 1.575 V */ + SW2B_1_6V, /*!< 1.600 V */ + SW2B_1_625V, /*!< 1.625 V */ + SW2B_1_65V, /*!< 1.650 V */ + SW2B_1_675V, /*!< 1.675 V */ + SW2B_1_7V, /*!< 1.700 V */ + SW2B_1_8V = 36, /*!< 1.800 V */ + SW2B_1_9V = 40, /*!< 1.900 V */ + SW2B_2V = 44, /*!< 2_000 V */ + SW2B_2_1V = 48, /*!< 2_100 V */ + SW2B_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw2b; + +/*! + * @enum t_pmic_regulator_voltage_sw3 + * @brief PMIC Switch mode regulator SW3 output voltages. + */ +typedef enum { + SW3_5V = 0, /*!< 5.0 V */ + SW3_5_1V = 0, /*!< 5.1 V */ + SW3_5_6V, /*!< 5.6 V */ +} t_pmic_regulator_voltage_sw3; + +/*! + * @enum t_switcher_factor + * @brief PLL multiplication factor + */ +typedef enum { + FACTOR_28 = 0, /*!< 917 504 kHz */ + FACTOR_29, /*!< 950 272 kHz */ + FACTOR_30, /*!< 983 040 kHz */ + FACTOR_31, /*!< 1 015 808 kHz */ + FACTOR_32, /*!< 1 048 576 kHz */ + FACTOR_33, /*!< 1 081 344 kHz */ + FACTOR_34, /*!< 1 114 112 kHz */ + FACTOR_35, /*!< 1 146 880 kHz */ +} t_switcher_factor; + +/*! + * @enum t_pmic_regulator_voltage_violo + * @brief PMIC regulator VIOLO output voltage. + */ +typedef enum { + VIOLO_1_2V = 0, /*!< 1.2 V */ + VIOLO_1_3V, /*!< 1.3 V */ + VIOLO_1_5V, /*!< 1.5 V */ + VIOLO_1_8V, /*!< 1.8 V */ +} t_pmic_regulator_voltage_violo; + +/*! + * @enum t_pmic_regulator_voltage_vdig + * @brief PMIC regulator VDIG output voltage. + */ +typedef enum { + VDIG_1_2V = 0, /*!< 1.2 V */ + VDIG_1_3V, /*!< 1.3 V */ + VDIG_1_5V, /*!< 1.5 V */ + VDIG_1_8V, /*!< 1.8 V */ +} t_pmic_regulator_voltage_vdig; + +/*! + * @enum t_pmic_regulator_voltage_vgen + * @brief PMIC regulator VGEN output voltage. + */ +typedef enum { + VGEN_1_2V = 0, /*!< 1.2 V */ + VENG_1_3V, /*!< 1.3 V */ + VGEN_1_5V, /*!< 1.5 V */ + VGEN_1_8V, /*!< 1.8 V */ + VGEN_1_1V, /*!< 1.1 V */ + VGEN_2V, /*!< 2 V */ + VGEN_2_775V, /*!< 2.775 V */ + VGEN_2_4V, /*!< 2.4 V */ +} t_pmic_regulator_voltage_vgen; + +/*! + * @enum t_pmic_regulator_voltage_vrfdig + * @brief PMIC regulator VRFDIG output voltage. + */ +typedef enum { + VRFDIG_1_2V = 0, /*!< 1.2 V */ + VRFDIG_1_5V, /*!< 1.5 V */ + VRFDIG_1_8V, /*!< 1.8 V */ + VRFDIG_1_875V, /*!< 1.875 V */ +} t_pmic_regulator_voltage_vrfdig; + +/*! + * @enum t_pmic_regulator_voltage_vrfref + * @brief PMIC regulator VRFREF output voltage. + */ +typedef enum { + VRFREF_2_475V = 0, /*!< 2.475 V */ + VRFREF_2_6V, /*!< 2.600 V */ + VRFREF_2_7V, /*!< 2.700 V */ + VRFREF_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrfref; + +/*! + * @enum t_pmic_regulator_voltage_vrfcp + * @brief PMIC regulator VRFCP output voltage. + */ +typedef enum { + VRFCP_2_7V = 0, /*!< 2.700 V */ + VRFCP_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrfcp; + +/*! + * @enum t_pmic_regulator_voltage_vsim + * @brief PMIC linear regulator VSIM output voltage. + */ +typedef enum { + VSIM_1_8V = 0, /*!< 1.8 V */ + VSIM_2_9V, /*!< 2.90 V */ + VSIM_3V = 1, /*!< 3 V */ +} t_pmic_regulator_voltage_vsim; + +/*! + * @enum t_pmic_regulator_voltage_vesim + * @brief PMIC regulator VESIM output voltage. + */ +typedef enum { + VESIM_1_8V = 0, /*!< 1.80 V */ + VESIM_2_9V, /*!< 2.90 V */ +} t_pmic_regulator_voltage_vesim; + +/*! + * @enum t_pmic_regulator_voltage_vcam + * @brief PMIC regulator VCAM output voltage. + */ +typedef enum { + VCAM_1_5V = 0, /*!< 1.50 V */ + VCAM_1_8V, /*!< 1.80 V */ + VCAM_2_5V, /*!< 2.50 V */ + VCAM_2_55V, /*!< 2.55 V */ + VCAM_2_6V, /*!< 2.60 V */ + VCAM_2_75V, /*!< 2.75 V */ + VCAM_2_8V, /*!< 2.80 V */ + VCAM_3V, /*!< 3.00 V */ +} t_pmic_regulator_voltage_vcam; + +/*! + * @enum t_pmic_regulator_voltage_vvib + * @brief PMIC linear regulator V_VIB output voltage. + */ +typedef enum { + VVIB_1_3V = 0, /*!< 1.30 V */ + VVIB_1_8V, /*!< 1.80 V */ + VVIB_2V, /*!< 2 V */ + VVIB_3V, /*!< 3 V */ +} t_pmic_regulator_voltage_vvib; + +/*! + * @enum t_pmic_regulator_voltage_vrf1 + * @brief PMIC regulator VRF1 output voltage. + */ +typedef enum { + VRF1_1_5V = 0, /*!< 1.500 V */ + VRF1_1_875V, /*!< 1.875 V */ + VRF1_2_7V, /*!< 2.700 V */ + VRF1_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrf1; + +/*! + * @enum t_pmic_regulator_voltage_vrf2 + * @brief PMIC regulator VRF2 output voltage. + */ +typedef enum { + VRF2_1_5V = 0, /*!< 1.500 V */ + VRF2_1_875V, /*!< 1.875 V */ + VRF2_2_7V, /*!< 2.700 V */ + VRF2_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrf2; + +/*! + * @enum t_pmic_regulator_voltage_vmmc + * @brief PMIC linear regulator VMMC output voltage. + */ +typedef enum { + VMMC_OFF = 0, /*!< Output off */ + VMMC_1_6V, /*!< 1.6 V */ + VMMC_1_8V, /*!< 1.8 V */ + VMMC_2V, /*!< 2 V */ + VMMC_2_2V, /*!< 2.2 V */ + VMMC_2_4V, /*!< 2.4 V */ + VMMC_2_6V, /*!< 2.6 V */ + VMMC_2_8V, /*!< 2.8 V */ + VMMC_3V, /*!< 3 V */ + VMMC_3_2V, /*!< 3.2 V */ + VMMC_3_3V, /*!< 3.3 V */ + VMMC_3_4V, /*!< 3.4 V */ +} t_pmic_regulator_voltage_vmmc; + +/*! + * @enum t_pmic_regulator_voltage_vmmc1 + * @brief PMIC regulator VMMC1 output voltage. + */ +typedef enum { + VMMC1_1_6V = 0, /*!< 1.60 V */ + VMMC1_1_8V, /*!< 1.80 V */ + VMMC1_2V, /*!< 2.00 V */ + VMMC1_2_6V, /*!< 2.60 V */ + VMMC1_2_7V, /*!< 2.70 V */ + VMMC1_2_8V, /*!< 2.80 V */ + VMMC1_2_9V, /*!< 2.90 V */ + VMMC1_3V, /*!< 3.00 V */ +} t_pmic_regulator_voltage_vmmc1; + +/*! + * @enum t_pmic_regulator_voltage_vmmc2 + * @brief PMIC regulator VMMC2 output voltage. + */ +typedef enum { + VMMC2_1_6V = 0, /*!< 1.60 V */ + VMMC2_1_8V, /*!< 1.80 V */ + VMMC2_2V, /*!< 2.00 V */ + VMMC2_2_6V, /*!< 2.60 V */ + VMMC2_2_7V, /*!< 2.70 V */ + VMMC2_2_8V, /*!< 2.80 V */ + VMMC2_2_9V, /*!< 2.90 V */ + VMMC2_3V, /*!< 3.00 V */ +} t_pmic_regulator_voltage_vmmc2; + +/*! + * @enum t_pmic_regulator_voltage_v1 + * @brief PMIC linear regulator V1 output voltages. + */ +typedef enum { + V1_2_775V = 0, /*!< 2.775 V */ + V1_1_2V, /*!< 1.2 V */ + V1_1_3V, /*!< 1.3 V */ + V1_1_4V, /*!< 1.4 V */ + V1_1_55V, /*!< 1.55 V */ + V1_1_75V, /*!< 1.75 V */ + V1_1_875V, /*!< 1.875 V */ + V1_2_475V, /*!< 2.475 V */ +} t_pmic_regulator_voltage_v1; + +/*! + * @enum t_pmic_regulator_voltage_v2 + * @brief PMIC linear regulator V2 output voltage, V2 has fixed + * output voltage 2.775 volts. + */ +typedef enum { + V2_2_775V = 0, /*!< 2.775 V */ +} t_pmic_regulator_voltage_v2; + +/*! + * @enum t_pmic_regulator_voltage_v3 + * @brief PMIC linear regulator V3 output voltage. + */ +typedef enum { + V3_1_875V = 0, /*!< 1.875 V */ + V3_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_v3; + +/*! + * @enum t_pmic_regulator_voltage_v4 + * @brief PMIC linear regulator V4 output voltage, V4 has fixed + * output voltage 2.775 volts. + */ +typedef enum { + V4_2_775V = 0, /*!< 2.775 V */ +} t_pmic_regulator_voltage_v4; + +/*! + * @union t_regulator_voltage + * @brief PMIC regulator output voltages. + */ +typedef union { + t_pmic_regulator_voltage_sw1 sw1; /*!< SW1 voltage */ + t_pmic_regulator_voltage_sw1a sw1a; /*!< SW1A voltage */ + t_pmic_regulator_voltage_sw1b sw1b; /*!< SW1B voltage */ + t_pmic_regulator_voltage_sw2 sw2; /*!< SW2 voltage */ + t_pmic_regulator_voltage_sw2a sw2a; /*!< SW2A voltage */ + t_pmic_regulator_voltage_sw2b sw2b; /*!< SW2B voltage */ + t_pmic_regulator_voltage_sw3 sw3; /*!< SW3 voltage */ + t_pmic_regulator_voltage_violo violo; /*!< VIOLO voltage */ + t_pmic_regulator_voltage_vdig vdig; /*!< VDIG voltage */ + t_pmic_regulator_voltage_vgen vgen; /*!< VGEN voltage */ + t_pmic_regulator_voltage_vrfdig vrfdig; /*!< VRFDIG voltage */ + t_pmic_regulator_voltage_vrfref vrfref; /*!< VRFREF voltage */ + t_pmic_regulator_voltage_vrfcp vrfcp; /*!< VRFCP voltage */ + t_pmic_regulator_voltage_vsim vsim; /*!< VSIM voltage */ + t_pmic_regulator_voltage_vesim vesim; /*!< VESIM voltage */ + t_pmic_regulator_voltage_vcam vcam; /*!< VCAM voltage */ + t_pmic_regulator_voltage_vvib vvib; /*!< VVIB voltage */ + t_pmic_regulator_voltage_vrf1 vrf1; /*!< VRF1 voltage */ + t_pmic_regulator_voltage_vrf2 vrf2; /*!< VRF2 voltage */ + t_pmic_regulator_voltage_vmmc vmmc; /*!< VMMC voltage */ + t_pmic_regulator_voltage_vmmc1 vmmc1; /*!< VMMC1 voltage */ + t_pmic_regulator_voltage_vmmc2 vmmc2; /*!< VMMC2 voltage */ + t_pmic_regulator_voltage_v1 v1; /*!< V1 voltage */ + t_pmic_regulator_voltage_v2 v2; /*!< V2 voltage */ + t_pmic_regulator_voltage_v3 v3; /*!< V3 voltage */ + t_pmic_regulator_voltage_v4 v4; /*!< V4 voltage */ +} t_regulator_voltage; + +/*! + * @enum t_pmic_regulator_sw_mode + * @brief define switch mode regulator mode. + * + * The synchronous rectifier can be disabled (and pulse-skipping enabled) + * to improve low current efficiency. Software should disable synchronous + * rectifier / enable the pulse skipping for average loads less than + * approximately 30 mA, depending on the quiescent current penalty due to + * synchronous mode. + */ +typedef enum { + SYNC_RECT = 0, + NO_PULSE_SKIP, + PULSE_SKIP, + LOW_POWER, +} t_pmic_regulator_sw_mode; + +/*! + * Generic PMIC switch mode regulator mode. + */ +typedef t_pmic_regulator_sw_mode t_regulator_sw_mode; +typedef t_pmic_regulator_sw_mode t_regulator_stby_mode; + +/*! + * @enum t_regulator_lp_mode + * @brief Low power mode control modes. + */ + +typedef enum { + /*! + * Low Power Mode is disabled + */ + LOW_POWER_DISABLED = 0, + /*! + * Low Power Mode is controlled by STANDBY pin and/or LVS pin + */ + LOW_POWER_CTRL_BY_PIN, + /*! + * Set Low Power mode no matter of hardware pins + */ + LOW_POWER_EN, + /*! + * Set Low Power mode and control by STANDBY + */ + LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN, +} t_regulator_lp_mode; + +/*! + * @enum t_switcher_dvs_speed + * @brief DVS speed setting + */ +typedef enum { + /*! + * Transition speed is dictated by the current + * limit and input -output conditions + */ + DICTATED = 0, + /*! + * 25mV step each 4us + */ + DVS_4US, + /*! + * 25mV step each 8us + */ + DVS_8US, + /*! + * 25mV step each 16us + */ + DVS_16US, +} t_switcher_dvs_speed; + +/*! + * @struct t_regulator_config + * @brief regulator configuration. + * + */ + +typedef struct { + /*! + * Switch mode regulator operation mode. This field only applies to + * switch mode regulators. + */ + t_regulator_sw_mode mode; + /*! + * Switch mode stby regulator operation mode. This field only applies + * to switch mode regulators. + */ + t_regulator_stby_mode stby_mode; + /*! + * Regulator output voltage. + */ + t_regulator_voltage voltage; + /*! + * Regulator output voltage in LVS mode. + */ + t_regulator_voltage voltage_lvs; + /*! + * Regulator output voltage in standby mode. + */ + t_regulator_voltage voltage_stby; + /*! + * Regulator low power mode. + */ + t_regulator_lp_mode lp_mode; + /*! + * Switcher dvs speed + */ + t_switcher_dvs_speed dvs_speed; + /*! + * Switcher panic mode + */ + bool panic_mode; + /*! + * Switcher softstart + */ + bool softstart; + /*! + * PLL Multiplication factor + */ + t_switcher_factor factor; +} t_regulator_config; + +/*! + * @struct t_regulator_cfg_param + * @brief regulator configuration structure for IOCTL. + * + */ +typedef struct { + /*! + * Regulator. + */ + t_pmic_regulator regulator; + /*! + * Regulator configuration. + */ + t_regulator_config cfg; +} t_regulator_cfg_param; + +/*! + * This struct list all state reads in Power Up Sense + */ +struct t_p_up_sense { + /*! + * power up sense ictest + */ + bool state_ictest; + /*! + * power up sense clksel + */ + bool state_clksel; + /*! + * power up mode supply 1 + */ + bool state_pums1; + /*! + * power up mode supply 2 + */ + bool state_pums2; + /*! + * power up mode supply 3 + */ + bool state_pums3; + /*! + * power up sense charge mode 0 + */ + bool state_chrgmode0; + /*! + * power up sense charge mode 1 + */ + bool state_chrgmode1; + /*! + * power up sense USB mode + */ + bool state_umod; + /*! + * power up sense boot mode enable for USB/RS232 + */ + bool state_usben; + /*! + * power up sense switcher 1a1b joined + */ + bool state_sw_1a1b_joined; + /*! + * power up sense switcher 1a1b joined + */ + bool state_sw_2a2b_joined; +}; + +/*! + * This enumeration define all On_OFF button + */ +typedef enum { + /*! + * ON1B + */ + BT_ON1B = 0, + /*! + * ON2B + */ + BT_ON2B, + /*! + * ON3B + */ + BT_ON3B, +} t_button; + +#ifdef __KERNEL__ +/* EXPORTED FUNCTIONS */ + +/*! + * This function sets user power off in power control register and thus powers + * off the phone. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +void pmic_power_off(void); + +/*! + * This function sets the power control configuration. + * + * @param pc_config power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_set_pc_config(t_pc_config *pc_config); + +/*! + * This function retrives the power control configuration. + * + * @param pc_config pointer to power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_pc_config(t_pc_config *pc_config); + +/*! + * This function turns on a regulator. + * + * @param regulator The regulator to be turned on. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_on(t_pmic_regulator regulator); + +/*! + * This function turns off a regulator. + * + * @param regulator The regulator to be turned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_off(t_pmic_regulator regulator); + +/*! + * This function sets the regulator output voltage. + * + * @param regulator The regulator to be turned off. + * @param voltage The regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_voltage(t_pmic_regulator regulator, + t_regulator_voltage voltage); + +/*! + * This function retrieves the regulator output voltage. + * + * @param regulator The regulator to be turned off. + * @param voltage Pointer to regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_voltage(t_pmic_regulator regulator, + t_regulator_voltage *voltage); + +/*! + * This function sets the DVS voltage + * + * @param regulator The regulator to be configured. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs(t_pmic_regulator regulator, + t_regulator_voltage dvs); + +/*! + * This function gets the DVS voltage + * + * @param regulator The regulator to be handled. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs(t_pmic_regulator regulator, + t_regulator_voltage *dvs); + +/*! + * This function sets the standby voltage + * + * @param regulator The regulator to be configured. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_stby(t_pmic_regulator regulator, + t_regulator_voltage stby); + +/*! + * This function gets the standby voltage + * + * @param regulator The regulator to be handled. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_stby(t_pmic_regulator regulator, + t_regulator_voltage *stby); + +/*! + * This function sets the switchers mode. + * + * @param regulator The regulator to be configured. + * @param mode The switcher mode + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_mode(t_pmic_regulator regulator, + t_regulator_sw_mode mode, bool stby); + +/*! + * This function gets the switchers mode. + * + * @param regulator The regulator to be handled. + * @param mode The switcher mode. + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_mode(t_pmic_regulator regulator, + t_regulator_sw_mode *mode, bool stby); + +/*! + * This function sets the switch dvs speed + * + * @param regulator The regulator to be configured. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed speed); + +/*! + * This function gets the switch dvs speed + * + * @param regulator The regulator to be handled. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed *speed); + +/*! + * This function sets the switch panic mode + * + * @param regulator The regulator to be configured. + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_panic_mode(t_pmic_regulator regulator, + bool panic_mode); + +/*! + * This function gets the switch panic mode + * + * @param regulator The regulator to be handled + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_panic_mode(t_pmic_regulator regulator, + bool *panic_mode); + +/*! + * This function sets the switch softstart mode + * + * @param regulator The regulator to be configured. + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_softstart(t_pmic_regulator regulator, + bool softstart); + +/*! + * This function gets the switch softstart mode + * + * @param regulator The regulator to be handled + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_softstart(t_pmic_regulator regulator, + bool *softstart); + +/*! + * This function sets the PLL multiplication factor + * + * @param regulator The regulator to be configured. + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_factor(t_pmic_regulator regulator, + t_switcher_factor factor); + +/*! + * This function gets the PLL multiplication factor + * + * @param regulator The regulator to be handled + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_factor(t_pmic_regulator regulator, + t_switcher_factor *factor); + +/*! + * This function enables or disables low power mode. + * + * @param regulator The regulator to be configured. + * @param mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode lp_mode); + +/*! + * This function gets low power mode. + * + * @param regulator The regulator to be handled + * @param mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode *lp_mode); + +/*! + * This function sets the regulator configuration. + * + * @param regulator The regulator to be turned off. + * @param config The regulator output configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_config(t_pmic_regulator regulator, + t_regulator_config *config); + +/*! + * This function retrieves the regulator output configuration. + * + * @param regulator The regulator to be turned off. + * @param config Pointer to regulator configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_config(t_pmic_regulator regulator, + t_regulator_config *config); + +/*! + * This function enables automatically VBKUP2 in the memory hold modes. + * + * @param en if true, enable VBKUP2AUTOMH + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vbkup2_auto_en(bool en); + +/*! + * This function gets state of automatically VBKUP2. + * + * @param en if true, VBKUP2AUTOMH is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_vbkup2_auto_state(bool *en); + +/*! + * This function enables battery detect function. + * + * @param en if true, enable BATTDETEN + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_bat_det_en(bool en); + +/*! + * This function gets state of battery detect function. + * + * @param en if true, BATTDETEN is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_bat_det_state(bool *en); + +/*! + * This function enables control of VVIB by VIBEN pin. + * + * @param en if true, enable VIBPINCTRL + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vib_pin_en(bool en); + +/*! + * This function gets state of control of VVIB by VIBEN pin. + * @param en if true, VIBPINCTRL is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_gets_vib_pin_state(bool *en); + +/*! + * This function returns power up sense value + * + * @param p_up_sense value of power up sense + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_power_mode_sense(struct t_p_up_sense *p_up_sense); + +/*! + * This function configures the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis if true, the regulator is enabled by regen. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_assig(t_pmic_regulator regulator, bool en_dis); + +/*! + * This function gets the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis return value, if true : + * the regulator is enabled by regen. + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_regen_assig(t_pmic_regulator regu, bool *en_dis); + +/*! + * This function sets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_inv(bool en_dis); + +/*! + * This function gets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ + +PMIC_STATUS pmic_power_get_regen_inv(bool *en_dis); + +/*! + * This function enables esim control voltage. + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_esim_v_en(bool vesim, bool vmmc1, bool vmmc2); + +/*! + * This function gets esim control voltage values. + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_gets_esim_v_state(bool *vesim, + bool *vmmc1, bool *vmmc2); + +/*! + * This function enables auto reset after a system reset. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_auto_reset_en(bool en); + +/*! + * This function gets auto reset configuration. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_auto_reset_en(bool *en); + +/*! + * This function configures a system reset on a button. + * + * @param bt type of button. + * @param sys_rst if true, enable the system reset on this button + * @param deb_time sets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_conf_button(t_button bt, bool sys_rst, int deb_time); + +/*! + * This function gets configuration of a button. + * + * @param bt type of button. + * @param sys_rst if true, the system reset is enabled on this button + * @param deb_time gets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_conf_button(t_button bt, + bool *sys_rst, int *deb_time); + +/*! + * This function is used to subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_sub(t_pwr_int event, void *callback); + +/*! + * This function is used to un subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_unsub(t_pwr_int event, void *callback); + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_POWER_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h new file mode 100644 index 000000000000..d134d9de6682 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -0,0 +1,572 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_SDMA_H__ +#define __ASM_ARCH_MXC_SDMA_H__ + +/*! + * @defgroup SDMA Smart Direct Memory Access (SDMA) Driver + */ + +/*! + * @file arch-mxc/sdma.h + * + * @brief This file contains the SDMA API declarations. + * + * SDMA is responsible on moving data between peripherals and memories (MCU, EMI and DSP). + * + * @ingroup SDMA + */ + +#include <linux/interrupt.h> +#include <asm/dma.h> +#include <stdarg.h> + +#include <mach/hardware.h> +#include <mach/dma.h> + +/*! + * This defines maximum DMA address + */ +#define MAX_DMA_ADDRESS 0xffffffff + +/*! + * This defines maximum number of DMA channels + */ +#ifdef CONFIG_MXC_SDMA_API +#define MAX_DMA_CHANNELS 32 +#define MAX_BD_NUMBER 16 +#define MXC_SDMA_DEFAULT_PRIORITY 1 +#define MXC_SDMA_MIN_PRIORITY 1 +#define MXC_SDMA_MAX_PRIORITY 7 +#else +#define MAX_DMA_CHANNELS 0 +#endif + +#define MXC_FIFO_MEM_DEST_FIXED 0x1 +#define MXC_FIFO_MEM_SRC_FIXED 0x2 + +#define SDMA_ASRC_INFO_WML_OFF 0 +#define SDMA_ASRC_INFO_WML_MASK ((1 << 10) - 1) +#define SDMA_ASRC_INFO_PS (1 << 10) +#define SDMA_ASRC_INFO_PA (1 << 11) +#define SDMA_ASRC_INFO_TXFR_DIR (1 << 14) +#define SDMA_ASRC_INFO_N_OFF (24) +#define SDMA_ASRC_INFO_N_MASK ((1 << 4) - 1) + +#define SDMA_ASRC_P2P_INFO_LWML_OFF 0 +#define SDMA_ASRC_P2P_INFO_LWML_MASK ((1 << 8) - 1) +#define SDMA_ASRC_P2P_INFO_PS (1 << 8) +#define SDMA_ASRC_P2P_INFO_PA (1 << 9) +#define SDMA_ASRC_P2P_INFO_SPDIF (1 << 10) +#define SDMA_ASRC_P2P_INFO_SP (1 << 11) +#define SDMA_ASRC_P2P_INFO_DP (1 << 12) +#define SDMA_ASRC_P2P_INFO_HWML_OFF 14 +#define SDMA_ASRC_P2P_INFO_HWML_MASK ((1 << 10) - 1) +#define SDMA_ASRC_P2P_INFO_LWE (1 << 28) +#define SDMA_ASRC_P2P_INFO_HWE (1 << 29) +#define SDMA_ASRC_P2P_INFO_CONT (1 << 31) + +/*! + * This enumerates transfer types + */ +typedef enum { + emi_2_per = 0, /*!< EMI memory to peripheral */ + emi_2_int, /*!< EMI memory to internal RAM */ + emi_2_emi, /*!< EMI memory to EMI memory */ + emi_2_dsp, /*!< EMI memory to DSP memory */ + per_2_int, /*!< Peripheral to internal RAM */ + per_2_emi, /*!< Peripheral to internal EMI memory */ + per_2_dsp, /*!< Peripheral to DSP memory */ + per_2_per, /*!< Peripheral to Peripheral */ + int_2_per, /*!< Internal RAM to peripheral */ + int_2_int, /*!< Internal RAM to Internal RAM */ + int_2_emi, /*!< Internal RAM to EMI memory */ + int_2_dsp, /*!< Internal RAM to DSP memory */ + dsp_2_per, /*!< DSP memory to peripheral */ + dsp_2_int, /*!< DSP memory to internal RAM */ + dsp_2_emi, /*!< DSP memory to EMI memory */ + dsp_2_dsp, /*!< DSP memory to DSP memory */ + emi_2_dsp_loop, /*!< EMI memory to DSP memory loopback */ + dsp_2_emi_loop, /*!< DSP memory to EMI memory loopback */ + dvfs_pll, /*!< DVFS script with PLL change */ + dvfs_pdr /*!< DVFS script without PLL change */ +} sdma_transferT; + +/*! + * This enumerates peripheral types + */ +typedef enum { + SSI, /*!< MCU domain SSI */ + SSI_SP, /*!< Shared SSI */ + MMC, /*!< MMC */ + SDHC, /*!< SDHC */ + UART, /*!< MCU domain UART */ + UART_SP, /*!< Shared UART */ + FIRI, /*!< FIRI */ + CSPI, /*!< MCU domain CSPI */ + CSPI_SP, /*!< Shared CSPI */ + SIM, /*!< SIM */ + ATA, /*!< ATA */ + CCM, /*!< CCM */ + EXT, /*!< External peripheral */ + MSHC, /*!< Memory Stick Host Controller */ + MSHC_SP, /*!< Shared Memory Stick Host Controller */ + DSP, /*!< DSP */ + MEMORY, /*!< Memory */ + FIFO_MEMORY, /*!< FIFO type Memory */ + SPDIF, /*!< SPDIF */ + IPU_MEMORY, /*!< IPU Memory */ + ASRC, /*!< ASRC */ + ESAI, /*!< ESAI */ +} sdma_periphT; + +#ifndef TRANSFER_32BIT +/*! + * This defines SDMA access data size + */ +#define TRANSFER_32BIT 0x00 +#define TRANSFER_8BIT 0x01 +#define TRANSFER_16BIT 0x02 +#define TRANSFER_24BIT 0x03 + +#endif + +/*! + * This defines maximum device name length passed during mxc_request_dma(). + */ +#define MAX_DEVNAME_LENGTH 32 + +/*! + * This defines SDMA interrupt callback function prototype. + */ +typedef void (*dma_callback_t) (void *arg); + +/*! + * Structure containing sdma channel parameters. + */ +typedef struct { + __u32 watermark_level; /*!< Lower/upper threshold that + * triggers SDMA event + * for p2p, this is event1 watermark level + */ + __u32 per_address; /*!< Peripheral source/destination + * physical address + * for p2p, this is destination address + */ + sdma_periphT peripheral_type; /*!< Peripheral type */ + sdma_transferT transfer_type; /*!< Transfer type */ + int event_id; /*!< Event number, + * needed by all channels + * that started by peripherals dma + * request (per_2_*,*_2_per) + * Not used for memory and DSP + * transfers. + */ + int event_id2; /*!< Second event number, + * used in ATA scripts only. + */ + int bd_number; /*!< Buffer descriptors number. + * If not set, single buffer + * descriptor will be used. + */ + dma_callback_t callback; /*! callback function */ + void *arg; /*! callback argument */ + unsigned long word_size:8; /*!< SDMA data access word size */ + unsigned long ext:1; /*!< 1: extend parameter structure */ +} dma_channel_params; + +typedef struct { + dma_channel_params common; + unsigned long p2p_dir:1; /*!< 0: per2 to per. + * the device of peripheral_type is per. + * 1: per to per2 + * the device of peripheral_type is per2 + */ + unsigned long info_bits; /*!< info field in context */ + unsigned long info_mask; /*!< info field mask in context */ + __u32 watermark_level2; /*!< event2 threshold that + * triggers SDMA event + * just valid for p2p. + */ + __u32 per_address2; /*!< Peripheral source + * physical address. + * just valid for p2p. + */ + struct dma_channel_info info; /*!< the channel special parameter */ +} dma_channel_ext_params; + +/*! + * Structure containing sdma request parameters. + */ +typedef struct { + /*! physical source memory address */ + __u8 *sourceAddr; + /*! physical destination memory address */ + __u8 *destAddr; + /*! amount of data to transfer, + * updated during mxc_dma_get_config + */ + __u16 count; + /*!< DONE bit of the buffer descriptor, + * updated during mxc_dma_get_config + * 0 - means the BD is done and closed by SDMA + * 1 - means the BD is still being processed by SDMA + */ + int bd_done; + /*!< CONT bit of the buffer descriptor, + * set it if full multi-buffer descriptor mechanism + * required. + */ + int bd_cont; + /*!< ERROR bit of the buffer descriptor, + * updated during mxc_dma_get_config. + * If it is set - there was an error during BD processing. + */ + int bd_error; +} dma_request_t; + +/*! + * Structure containing sdma request parameters. + */ +typedef struct { + /*! address of ap_2_ap script */ + int mxc_sdma_ap_2_ap_addr; + /*! address of ap_2_bp script */ + int mxc_sdma_ap_2_bp_addr; + /*! address of ap_2_ap_fixed script */ + int mxc_sdma_ap_2_ap_fixed_addr; + /*! address of bp_2_ap script */ + int mxc_sdma_bp_2_ap_addr; + /*! address of loopback_on_dsp_side script */ + int mxc_sdma_loopback_on_dsp_side_addr; + /*! address of mcu_interrupt_only script */ + int mxc_sdma_mcu_interrupt_only_addr; + + /*! address of firi_2_per script */ + int mxc_sdma_firi_2_per_addr; + /*! address of firi_2_mcu script */ + int mxc_sdma_firi_2_mcu_addr; + /*! address of per_2_firi script */ + int mxc_sdma_per_2_firi_addr; + /*! address of mcu_2_firi script */ + int mxc_sdma_mcu_2_firi_addr; + + /*! address of uart_2_per script */ + int mxc_sdma_uart_2_per_addr; + /*! address of uart_2_mcu script */ + int mxc_sdma_uart_2_mcu_addr; + /*! address of per_2_app script */ + int mxc_sdma_per_2_app_addr; + /*! address of mcu_2_app script */ + int mxc_sdma_mcu_2_app_addr; + /*! address of per_2_per script */ + int mxc_sdma_per_2_per_addr; + + /*! address of uartsh_2_per script */ + int mxc_sdma_uartsh_2_per_addr; + /*! address of uartsh_2_mcu script */ + int mxc_sdma_uartsh_2_mcu_addr; + /*! address of per_2_shp script */ + int mxc_sdma_per_2_shp_addr; + /*! address of mcu_2_shp script */ + int mxc_sdma_mcu_2_shp_addr; + + /*! address of ata_2_mcu script */ + int mxc_sdma_ata_2_mcu_addr; + /*! address of mcu_2_ata script */ + int mxc_sdma_mcu_2_ata_addr; + + /*! address of app_2_per script */ + int mxc_sdma_app_2_per_addr; + /*! address of app_2_mcu script */ + int mxc_sdma_app_2_mcu_addr; + /*! address of shp_2_per script */ + int mxc_sdma_shp_2_per_addr; + /*! address of shp_2_mcu script */ + int mxc_sdma_shp_2_mcu_addr; + + /*! address of mshc_2_mcu script */ + int mxc_sdma_mshc_2_mcu_addr; + /*! address of mcu_2_mshc script */ + int mxc_sdma_mcu_2_mshc_addr; + + /*! address of spdif_2_mcu script */ + int mxc_sdma_spdif_2_mcu_addr; + /*! address of mcu_2_spdif script */ + int mxc_sdma_mcu_2_spdif_addr; + + /*! address of asrc_2_mcu script */ + int mxc_sdma_asrc_2_mcu_addr; + + /*! address of ext_mem_2_ipu script */ + int mxc_sdma_ext_mem_2_ipu_addr; + + /*! address of descrambler script */ + int mxc_sdma_descrambler_addr; + + /*! address of dptc_dvfs script */ + int mxc_sdma_dptc_dvfs_addr; + + int mxc_sdma_utra_addr; + + /*! address of peripheral ssi to mcu script */ + int mxc_sdma_ssiapp_2_mcu_addr; + /*! address of mcu to peripheral ssi script */ + int mxc_sdma_mcu_2_ssiapp_addr; + + /*! address of shared peripheral ssi to mcu script */ + int mxc_sdma_ssish_2_mcu_addr; + /*! address of mcu to shared peripheral ssi script */ + int mxc_sdma_mcu_2_ssish_addr; + + /*! address where ram code starts */ + int mxc_sdma_ram_code_start_addr; + /*! size of the ram code */ + int mxc_sdma_ram_code_size; + + /*! RAM image address */ + unsigned short *mxc_sdma_start_addr; +} sdma_script_start_addrs; + +/*! Structure to store the initialized dma_channel parameters */ +typedef struct mxc_sdma_channel_params { + /*! Channel type (static channel number or dynamic channel) */ + unsigned int channel_num; + /*! Channel priority [0x1(lowest) - 0x7(highest)] */ + unsigned int chnl_priority; + /*! Channel params */ + dma_channel_params chnl_params; +} mxc_sdma_channel_params_t; + +/*! Structure to store the initialized dma_channel extend parameters */ +typedef struct mxc_sdma_channel_ext_params { + /*! Channel type (static channel number or dynamic channel) */ + unsigned int channel_num; + /*! Channel priority [0x1(lowest) - 0x7(highest)] */ + unsigned int chnl_priority; + /*! Channel extend params */ + dma_channel_ext_params chnl_ext_params; +} mxc_sdma_channel_ext_params_t; + +/*! Private SDMA data structure */ +typedef struct mxc_dma_channel_private { + /*! ID of the buffer that was processed */ + unsigned int buf_tail; + /*! Tasklet for the channel */ + struct tasklet_struct chnl_tasklet; + /*! Flag indicates if interrupt is required after every BD transfer */ + int intr_after_every_bd; +} mxc_dma_channel_private_t; + +/*! + * Setup channel according to parameters. + * Must be called once after mxc_request_dma() + * + * @param channel channel number + * @param p channel parameters pointer + * @return 0 on success, error code on fail + */ +int mxc_dma_setup_channel(int channel, dma_channel_params *p); + +/*! + * Setup the channel priority. This can be used to change the default priority + * for the channel. + * + * @param channel channel number + * @param priority priority to be set for the channel + * + * @return 0 on success, error code on failure + */ +int mxc_dma_set_channel_priority(unsigned int channel, unsigned int priority); + +/*! + * Allocates dma channel. + * If channel's value is 0, then the function allocates a free channel + * dynamically and sets its value to channel. + * Else allocates requested channel if it is free. + * If the channel is busy or no free channels (in dynamic allocation) -EBUSY returned. + * + * @param channel pointer to channel number + * @param devicename device name + * @return 0 on success, error code on fail + */ +int mxc_request_dma(int *channel, const char *devicename); + +/*! + * Configures request parameters. Can be called multiple times after + * mxc_request_dma() and mxc_dma_setup_channel(). + * + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to set + * @return 0 on success, error code on fail + */ +/* int mxc_dma_set_config(int channel, dma_request_t *p, int bd_index); */ +int mxc_dma_set_config(int channel, dma_request_t *p, int bd_index); + +/*! + * Returns request parameters. + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to get + * @return 0 on success, error code on fail + */ +/* int mxc_dma_get_config(int channel, dma_request_t *p, int bd_index); */ +int mxc_dma_get_config(int channel, dma_request_t *p, int bd_index); + +/*! + * This function is used by MXC IPC's write_ex2. It passes the a pointer to the + * data control structure to iapi_write_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_write_ipcv2(int channel, void *ctrl_ptr); + +/*! + * This function is used by MXC IPC's read_ex2. It passes the a pointer to the + * data control structure to iapi_read_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_read_ipcv2(int channel, void *ctrl_ptr); + +/*! + * Starts dma channel. + * + * @param channel channel number + */ +int mxc_dma_start(int channel); + +/*! + * Stops dma channel. + * + * @param channel channel number + */ +int mxc_dma_stop(int channel); + +/*! + * Frees dma channel. + * + * @param channel channel number + */ +void mxc_free_dma(int channel); + +/*! + * Sets callback function. Used with standard dma api + * for supporting interrupts + * + * @param channel channel number + * @param callback callback function pointer + * @param arg argument for callback function + */ +void mxc_dma_set_callback(int channel, dma_callback_t callback, void *arg); + +/*! + * Allocates uncachable buffer. Uses hash table. + * + * @param size size of allocated buffer + * @return pointer to buffer + */ +void *sdma_malloc(size_t size); + +#ifdef CONFIG_SDMA_IRAM +/*! + * Allocates uncachable buffer from IRAM.. + * + * @param size size of allocated buffer + * @return pointer to buffer + */ +void *sdma_iram_malloc(size_t size); +#endif /*CONFIG_SDMA_IRAM */ + +/*! + * Frees uncachable buffer. Uses hash table. + */ +void sdma_free(void *buf); + +/*! + * Converts virtual to physical address. Uses hash table. + * + * @param buf virtual address pointer + * @return physical address value + */ +unsigned long sdma_virt_to_phys(void *buf); + +/*! + * Converts physical to virtual address. Uses hash table. + * + * @param buf physical address value + * @return virtual address pointer + */ +void *sdma_phys_to_virt(unsigned long buf); + +/*! + * Configures the BD_INTR bit on a buffer descriptor parameters. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * @param bd_intr flag to set or clear the BD_INTR bit + */ +void mxc_dma_set_bd_intr(int channel, int bd_index, int bd_intr); + +/*! + * Gets the BD_INTR bit on a buffer descriptor. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * + * @return returns the BD_INTR bit status + */ +int mxc_dma_get_bd_intr(int channel, int bd_index); + +/*! + * Stop the current transfer + * + * @param channel channel number + * @param buffer_number number of buffers (beginning with 0), + * whose done bits should be reset to 0 + */ +int mxc_dma_reset(int channel, int buffer_number); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id); + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl); + +/*! + * Initializes SDMA driver + */ +int __init sdma_init(void); + +#define DEFAULT_ERR 1 + +#endif diff --git a/arch/arm/plat-mxc/include/mach/sdram_autogating.h b/arch/arm/plat-mxc/include/mach/sdram_autogating.h new file mode 100644 index 000000000000..5dcc38178279 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdram_autogating.h @@ -0,0 +1,56 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver + */ + +/*! + * @file arch-mxc/sdram_autogating.h + * + * @brief This file contains the SDRAM autogating function prototypes + * + * + * @ingroup PM + */ + +#ifndef __ASM_ARCH_SDRAM_AUTOGATING_H__ +#define __ASM_ARCH_SDRAM_AUTOGATING_H__ + +#ifdef __KERNEL__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/workqueue.h> +#include <linux/device.h> + + +#ifdef CONFIG_ARCH_MX5 +extern void start_sdram_autogating(void); +extern void stop_sdram_autogating(void); +extern int sdram_autogating_active(void); +#else +static inline void start_sdram_autogating(void) +{} + +static inline void stop_sdram_autogating(void) +{} + +static inline int sdram_autogating_active(void) +{ + return 0; +} +#endif + +#endif /*__KERNEL__ */ +#endif /* __ASM_ARCH_MXC_DVFS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index ef00199568de..33fe6f8e5e7f 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,18 +24,9 @@ #include <mach/hardware.h> #include <mach/common.h> -static inline void arch_idle(void) -{ -#ifdef CONFIG_ARCH_MXC91231 - if (cpu_is_mxc91231()) { - /* Need this to set DSM low-power mode */ - mxc91231_prepare_idle(); - } -#endif - - cpu_do_idle(); -} +void arch_idle(void); void arch_reset(char mode, const char *cmd); +int mxs_reset_block(void __iomem *hwreg, int just_enable); #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 024416ed11cd..145e50495d65 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -1,6 +1,6 @@ /* * Copyright (C) 1999 ARM Limited - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,8 +26,10 @@ #define CLOCK_TICK_RATE 13300000 #elif defined CONFIG_ARCH_MX3 #define CLOCK_TICK_RATE 16625000 +#elif defined CONFIG_ARCH_MX37 +#define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MX25 -#define CLOCK_TICK_RATE 16000000 +#define CLOCK_TICK_RATE 13300000 #elif defined CONFIG_ARCH_MX5 #define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MXC91231 diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b6d3d0fddc48..d3c46b167ece 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -25,6 +25,7 @@ #include <asm/mach-types.h> +unsigned int system_rev; static unsigned long uart_base; #define UART(x) (*(volatile unsigned long *)(uart_base + (x))) @@ -67,6 +68,8 @@ static inline void flush(void) #define MX3X_UART1_BASE_ADDR 0x43F90000 #define MX3X_UART2_BASE_ADDR 0x43F94000 #define MX51_UART1_BASE_ADDR 0x73fbc000 +#define MX53_UART1_BASE_ADDR 0x53fbc000 +#define MX50_UART1_BASE_ADDR 0x53fbc000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -105,6 +108,14 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX51_BABBAGE: uart_base = MX51_UART1_BASE_ADDR; break; + case MACH_TYPE_MX53_EVK: + case MACH_TYPE_MX53_ARD: + uart_base = MX53_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX50_ARM2: + case MACH_TYPE_MX50_RDP: + uart_base = MX50_UART1_BASE_ADDR; + break; default: break; } |