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2017-03-31arm: tegra: soc: Use sys_soc to expose SoC UIDBhuvanchandra DV
Use the standard sys_soc interface to expose the SoC UID information. e.g. ~# cat /sys/bus/soc/devices/soc0/machine NVIDIA Tegra ~# cat /sys/bus/soc/devices/soc0/family NVIDIA Tegra30 ~# cat /sys/bus/soc/devices/soc0/revision A03 ~# cat /sys/bus/soc/devices/soc0/soc_id 98317451306464792 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2013-03-03Conflicts:Marcel Ziswiler
arch/arm/mach-tegra/common.c drivers/ata/ahci-tegra.c
2012-12-17arm: tegra: display: handle fbmem2 cmdline parameterJong Kim
Parse and handle fbmem2 cmdline parameter. bug 1175957 Change-Id: I0933825371bf13782e9f4364a4dba078929ae836 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/170662 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2012-12-17arm: tegra: display: provide framebuffer clear functionJong Kim
Add tegra_clear_framebuffer function. bug 1175957 Change-Id: I12c249e011ecd839bbe9c5371b8be6e8a4b27bba Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/170661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2012-11-12Merge branch 'l4t/l4t-r16-r2' into colibriMarcel Ziswiler
Conflicts: arch/arm/mach-tegra/tegra3_usb_phy.c arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/tegra_udc.c drivers/usb/otg/Makefile drivers/video/tegra/fb.c sound/soc/tegra/tegra_pcm.c
2012-10-03tegra: colibri_t20: clock clean-upMarcel Ziswiler
Clean-up some of the early clock initialisation hacks.
2012-09-10Merge branch 'l4t/l4t-r16' into colibriMarcel Ziswiler
Merge with latest NVIDIA L4T R16. Only real conflict concerning inverted VBUS gpio support.
2012-09-06arm: tegra: secureos: disable L2 as part of sleep CPU SMCChris Johnson
This is an alternate way to have the L2 disabled available with later TL secureos versions. In this version, the sleep CPU SMC which is the last one issued before entering LP2 on CPU0, will also disable the L2 without a flush of the secureos workspace. Change-Id: I61c3caade6cb6f922b9d9f9ca0739bc6ae4e78cd Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/128951 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: James Zhao <jamesz@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-08-23ARM: Tegra: Omit L2 flush at disableAntti P Miettinen
In Tegra kernel L2 is disabled only upon CPU cluster power down, e.g. LP2 entry. Flushing L2 upon every LP2 entry is costly. Since we are always in single core mode upon cluster power down we can safely omit L2 flush upon L2 disable. Change-Id: I27542b11e6133f3192a02440e5b14ea408b860fd Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/105625 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2012-08-06arm: tegra: optimize L2 enable/disable paths for secureosHyung Taek Ryoo
For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Bug 939415 Signed-off-by: Chris Johnson<cwj@nvidia.com> Change-Id: I756d2ceda83d5d8d6bc5670218e9d874d5e5f62a Reviewed-on: http://git-master/r/119786 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-08-03arm: tegra: read board info from device treeNitin Kumbhar
Read board_info data from device tree instead of ATAGs, if we're booting with device tree. Bug 1001225 Change-Id: I2d659252a6a91f723bf4bb6c74918774650b87e2 Original-Author: Dan Willemsen <dwillemsen@nvidia.com> Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/116604 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-23ARM: tegra: clock: Set SCLK floor for CPU mode switchAlex Frid
Set SCLK floor to 80MHz for Tegra3 CPU mode switch. Bug 933984 Change-Id: Ibbb0a24cd763c11b3cead60efe26096bae3e6ddd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/106035 Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Tested-by: Jay Cheng <jacheng@nvidia.com> (cherry picked from commit 842f7ddb7a188e36a2ff153dc0d8ed38b5e28319) Reviewed-on: http://git-master/r/113981 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-20tegra: carveout and framebuffer memory sizingMarcel Ziswiler
Support fbmem in addition to tegra_fbmem kernel argument for backwards compatibility reason. Support nvmem kernel argument for carveout definition to be backward compatible. Add special handling in case of already reserved fbmem/nvmem.
2012-06-19arm: tegra: Fix cpu governor change issuePuneet Saxena
It fixes the issue where cpu governor change was inconsistent across platforms. In T2x, AUTO HOTPLUG is disabled therefore we need to store/restore gov for all online cpus across LP0 cycle. In T3x, AUTO HOTPLUG is enabled therefore storing/restoring gov for Cpu0 across LP0 cycle. Cpu0 remains online in suspend and resume. bug 991081 Change-Id: I167654aa21e4832b3fdc40e3d388a4d3f984632b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/105404 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-08Initial Toradex Colibri T20 L4T R15 support.Marcel Ziswiler
2012-05-30arm: tegra: resolve compilation time warningsSanjay Singh Rawat
Warnings removed are related to unused variables/labels, structure/argument type mismatch, copyright update, function return type mismatch and wrong C coding style. Bug 949219 Change-Id: Ib748d12d5ab3cfc35118be28c29983081cca6cbb Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/103770 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-05-21arm: tegra: governor: change governor using cpufreq interfacePuneet Saxena
Older code sets "conservative" governor in early-suspend using sysfs entries.This implementation changes governor in early-suspend using cpufreq interfaces. bug 871958 Change-Id: I721afb6184982a063dc5f330da31f8fb88481cfd Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/100849 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-07arm: tegra: pl310: Enable dynamic clock gating and standy.Krishna Reddy
Bug 947861 Change-Id: Ib4ce7bfa3624562a766678a2ef20ebdcd3055d89 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/100462 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-04-30arch: arm: tegra: Add support for marvell 8797Nitin Bindal
If bootloader specify that marvell wifi chip is present on the board, then create marvell wifi device, else create broadcom wifi device. Bug 954218 Change-Id: Ia0515e70b6d4b239a165b8d8629e3b90c19666b6 Signed-off-by: Nitin Bindal <nbindal@nvidia.com> Reviewed-on: http://git-master/r/98490 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-26ARM: tegra: clock: Move SCLK shared users initializationAlex Frid
Moved SCLK shared users initialization from silicon only section of init table to common silicon/emulation section - there is no reason to limit this settings to silicon only. Change-Id: Ib1aa1bd3f98008b6584222e6c49f0825d635b8bd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/98104 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-19arm: tegra: resolve compilation time warningsSanjay Singh Rawat
Bug 949219 Change-Id: I875f8688a272c415ebf345b8f30e4afdf7551b29 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/91523 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-12ARM: tegra: common: Remove T30 A01 SMMU workaroundJuha Tukkinen
Remove CONFIG_TEGRA_SMMU_BASE_AT_E0000000 workaround as T30 A01 is no longer supported. Change-Id: I0ba6c838984e3c3ec401057925727c9596a8075f Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/95644 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-12ARM: tegra: clock: Update common clock tableAlex Frid
- Moved table entries for always running core clocks on the top of the table (this way we guarantee that changing parent of such clock down the road would automatically enable new parent). - Removed unnecessary pll_a and pll_a_out0 entries (effectively they are "NOP") - actual audio configuration is done in per-board tables. - Removed unnecessary pll_c and pll_c_out1 entries for emulation platforms Change-Id: I8327d6313804419405dd93af08f369db02fcbf25 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/95465 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-03arm: tegra3: change min_rate for sclkAmit Kamath
Change the minimal rate of sclk to 12 MHz and set the lowest frequency of sbus to be 40 MHz when display is on. bug 939415 Original change http://git-master/r/#change,76959 Change-Id: I81cda6a95494764721c1be5b4001c476f3aed6ab Signed-off-by: Amit Kamath <akamath@nvidia.com> Reviewed-on: http://git-master/r/93850 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-03ARM: tegra: clock: Fix emulation clock tableAlex Frid
Configure PLLC on emulation platforms after SCLK is switched to PLLP. This would avoid failure in case when emulation initialization script set PLLC as SCLK source. Change-Id: Ie0f48c066f6df7f6f3c67858de7e9d7608dcb7ff Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/93730 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-26ARM: tegra: dvfs: Add chip sku overrideRay Poudrier
Based on command line parameter, override the sku Bug 925878 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/83241 (cherry picked from commit 24df2878418fc0c5f2b2dd20130df91a23dd042e) Change-Id: Ic8d2408c6e408fcf28f9b64f12866971b753b41e Reviewed-on: http://git-master/r/88864 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-20ARM: tegra: Add support to identify if image RCKAshwini Ghuge
With this change, we can identify if system enters RCK mode in kernel. Bug 948270 Change-Id: I4240fd4171b6b71fbc5f1271f21a588d62db88b1 Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/90914 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-19arm: tegra: enable pll_p clocks by defaultPeter Zu
Setting pll_p init state to false may cause lp0 resume issue when cpu_restore_complex tries to restore pll_p state on CPU cluster switching. Bug 932820 Signed-off-by: Peter Zu <pzu@nvidia.com> Reviewed-on: http://git-master/r/86904 (cherry picked from commit 939e6c177927a4731b043ac77543f075ac17fca2) Change-Id: I4513470515a20edcf54a9aa11a54e65838012fe5 Reviewed-on: http://git-master/r/90568 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-03-15ARM: tegra: common: Set SCLK to 40MHz for spiLaxman Dewangan
Setting sclk frequency for spi to 40MHz. bug 949393 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/89525 cherry-picked from 171f5693e4137e9fe5a8b4e496c0c5db3b7838f1 Change-Id: I34808a64b834111dfff1592dd9244a45e9d3312c Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/90295 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-15ARM: tegra: use common console flush on rebootTom Cherry
Bug 952455 Change-Id: I5272bdf2fc726994f3a22fd42671bb807bc30a21 Signed-off-by: Tom Cherry <tcherry@nvidia.com> Reviewed-on: http://git-master/r/89875 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-06ARM: tegra: Add forced-recovery support for bootloader.Gaurav Sarode
Set SCRATCH0 bit 1 when forced-recovery is set. Bootrom will check this and put device into nvflash mode. Bug 948326 Signed-off-by: Gaurav Sarode <gsarode@nvidia.com> Change-Id: I78108021dffda681d63ddc6760e07cb563ba2eac Reviewed-on: http://git-master/r/87238 Reviewed-by: Vivek Kumar <vivekk@nvidia.com> Reviewed-by: Hon Fei Chong <hchong@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-03-01ARM: tegra: Add support for passing arguments to bootloader.Gaurav Sarode
PMC SCRATCH register 0 holds value across warmboot. Storing values in bit31:30 for recovery and fastboot. This requires change in bootloader as well to parse these arguments. Bug 863014 Change-Id: I1d4b752dbc6dd7b065e9d0cc87df189e7caeb201 Signed-off-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-on: http://git-master/r/86140 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-23ARM: tegra: clock src initialisation for debug port in common placeLaxman Dewangan
Moving clock source rate initialisation of debug ports in common place from board files. In this way, it does not need to call the same function from all board files and so avoid duplicating. Change-Id: I4e0292c7760488125c0dd8ee5fa23f50faca3436 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/85174 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-17Revert "arm: tegra3: change min_rate for sclk"Chandrakanth Gorantla
This reverts commit a61ef84d7746134aae316fa76867d69fc0753880. Bug 939415 Change-Id: I7d7c2a69ac7261a221cf69b8f8981d42f575f789 Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Reviewed-on: http://git-master/r/84025 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-13ARM: tegra: Clean up CACHE_L2X0 conditionals and includesScott Williams
Change-Id: I9862e73f264c757f97aaad03f3373fb1d3e95462 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/79138 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-09arm: tegra: Reduce coresite clock frequencyScottPeterson
Source coresite clock from clk_m and reduce its frequency to 1Mhz to reduce the power consumption on csite module. BUG 922351 Signed-off-by: ScottPeterson <speterson@nvidia.com> Reviewed-on: http://git-master/r/76287 (cherry picked from commit 80c11f4c789efea49b30b8731711aa4c20d7630c) Change-Id: If8a75924229c8d6aae4fd449eff6ae2e194a6e45 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/79995 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-02-03arm: tegra: fix warning in governor parameter set functionDiwakar Tundlam
Bug 922351 Reviewed-on: http://git-master/r/78310 Change-Id: I4d1a341386b10c584715d2bbb76ac69877b47fb7 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78904 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-03ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entriesAlex Frid
Bug 841336 Reviewed-on: http://git-master/r/76912 Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78706 Reviewed-by: Automatic_Commit_Validation_User
2012-01-31arm: tegra3: change min_rate for sclkWen Yi
Change the minimal rate of sclk to 12 MHz and set the lowest frequency of sbus to be 40 MHz when display is on. BUG 922351 Reviewed-on: http://git-master/r/76959 Change-Id: I6a2871d1cc02a19829cf397e9583122e02255f81 Signed-off-by: Wen Yi <wyi@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78010 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-30ARM: tegra: clock: Add support for Tegra3 MSelect clockAlex Frid
Added clock for memory path selection module (MSelect) to Tegra3 peripheral clocks. Initialized MSelect clock rate to 102MHz. Reviewed-on: http://git-master/r/76484 Change-Id: I73676882d8e6805445985b23257bcf6410e8c3e0 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77766 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30arm: tegra: Clock audio from clk_mScottPeterson
Clock audio from clkm as a pre-condition of disabling pllp_out1 and plla when I2S is in slave mode. Change-Id: I1706c2989cf7ad9045526ceba3326777b702868a Reviewed-on: http://git-master/r/76391 Signed-off-by: ScottPeterson <speterson@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I243508cc553ebf22bb5594a9461019abfec24b65 Reviewed-on: http://git-master/r/77753 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30arm: tegra: modify governor parameter set functionWen Yi
Use the parameter name and value to set to the conservative governor. Also defined the value of freq_step to be 3 and set it during early suspension. Bug 922351 Reviewed-on: http://git-master/r/73841 Change-Id: Ieefa487f8b255d4bf242a7d98b07dc3758a70e86 Signed-off-by: Wen Yi <wyi@nvidia.com> Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77743 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30arm: tegra: Disable pll_p_out clocks by defaultPrashant Gaikwad
Disable unused pll_p_out clocks until they are needed to reduce power. Reviewed-on: http://git-master/r/76778 Change-Id: I16dba325fff48cc895ec115f3a4124a1d7228cee Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77736 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30ARM: tegra: clock: Auto-detect PLLP rate in clock initAlex Frid
Tegra3 platform may boot with one of the predefined fixed PLLP (peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This commit implements auto-detection of PLLP rate, as well as CPU, and system bus PLLP dependencies configuration during clock tree initialization. Bug 928260 Change-Id: I65ea4db2e5cfe96f13566c93e882a3be9deaa129 Reviewed-on: http://git-master/r/75850 Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77295 Reviewed-by: Automatic_Commit_Validation_User
2012-01-12arm: tegra: move ram console to common codesHaley Teng
cleanup ram console related source codes and move most of the implementation in board files to common.c since ram console is a common debug mechanism. bug 873307 Signed-off-by: Haley Teng <hteng@nvidia.com> Reviewed-on: http://git-master/r/54598 Reviewed-on: http://git-master/r/66588 (cherry picked from commit 119ce36b7bed370a528dfebc80bd79698118248d) Change-Id: I8b769b422305101a97f1fbc99db4af48dc7d4f25 Reviewed-on: http://git-master/r/71961 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-on: http://git-master/r/74552 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-12arm: tegra: smmu: Move tegra_smmu.h under "include/mach"Hiroshi DOYU
This is the preparation the following patches so that this header can be referred from another directly than "arch/arm/mach-tegra". Change-Id: I846970f306ff3daa8229e10e6f33b8e9fcf57cf9 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/73947 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-06arm: tegra: Disable pll_p_out clocks by defaultScottPeterson
Disable unused pll_p_out clocks until they are needed to reduce power. Change-Id: I60c2a7ca50a957f23ca20ec559dbbb1aa26ca797 Reviewed-on: http://git-master/r/72464 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-12-30arm: tegra: Switch governor for both CPUsPrashant Gaikwad
HOTPLUG_CPU option is enabled for both Tegra20 and Tegra30. For Tegra20, need to switch governor for both CPUs. Use TERA_AUTO_HOTPLUG config which is enabled only for Tegra30. Bug 909096 Change-Id: I683079d834f137bb84ff2d3bdb853dac826038d6 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/72127 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-12-23arm: tegra: set cpu0 governor for early suspendSang-Hun Lee
The cpufreq sysfs entry for cpus other than cpu0 in T30 is populated when the cpu becomes online and removed when the cpu becomes offline. This caused race condition between setting cpu governor and bringing cpu offline. The solution is to change the governor for cpu0 only. BUG 914009 Signed-Off by: Karthik Ramakrishnan <karthikr@nvidia.com> Cherry-picked from: http://git-master/r/#change,50155 Change-Id: Ia604169f2a211083803f161d1e28bc0e3ca80ab2 Reviewed-on: http://git-master/r/70213 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-12-22ARM: tegra: correctly access file in kernelVictor(Weiguo) Pan
1. Tell the kernel the pointers from within the kernel address space are safe before accessing the file. Save/restore current process address before/after the file accessing. 2. Use macro IS_ERR to check file opening is successful or not because filp_open() returns negtive value once error happens. bug 865113 bug 917684 Reviewed-on: http://git-master/r/48788 (cherry picked from commit 76d0a832b0fb8c5c6446f9c86ccc743701ff704e) Change-Id: Ie96152396f93a49babe848041feca354c6dfce50 Signed-off-by: Roger Hsieh <rhsieh@nvidia.com> Reviewed-on: http://git-master/r/71152 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-26 21:11:16 +0000