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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS2081A RDB Board.
*
* Copyright 2017 NXP
*
* Priyanka Jain <priyanka.jain@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls2088a.dtsi"
/ {
model = "NXP Layerscape 2081A RDB Board";
compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&esdhc {
status = "okay";
};
&ifc {
status = "disabled";
};
&i2c0 {
status = "okay";
pca9547@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&dspi {
status = "okay";
dflash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
};
&qspi {
status = "okay";
fsl,qspi-has-second-chip;
flash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-max-frequency = <20000000>;
reg = <0>;
};
flash1: s25fs512s@1 {
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
compatible = "spansion,m25p80";
spi-max-frequency = <20000000>;
reg = <1>;
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
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