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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
cm40_subsys: bus@34000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
cm40_ipg_clk: clock-cm40-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <132000000>;
clock-output-names = "cm40_ipg_clk";
};
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&cm40_intmux>;
clocks = <&cm40_i2c_lpcg 0>,
<&cm40_i2c_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
status = "disabled";
};
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
bit-offset = <0 16>;
clock-output-names = "cm40_lpcg_i2c_clk",
"cm40_lpcg_i2c_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
};
cm40_intmux: intmux@37400000 {
compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux";
reg = <0x37400000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&cm40_ipg_clk>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
status = "disabled";
};
cm40_lpuart: serial@37220000 {
compatible = "fsl,imx8qxp-lpuart";
reg = <0x37220000 0x1000>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&cm40_intmux>;
clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_UART>;
status = "disabled";
};
cm40_uart_lpcg: clock-controller@37620000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37620000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
bit-offset = <0 4>;
clock-output-names = "cm40_lpcg_uart_clk",
"cm40_lpcg_uart_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_UART>;
};
};
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