1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
cm41_subsys: bus@38000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x38000000 0x0 0x38000000 0x4000000>;
cm41_ipg_clk: clock-cm41-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <132000000>;
clock-output-names = "cm41_ipg_clk";
};
cm41_i2c: i2c@3b230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x3b230000 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&cm41_intmux>;
clocks = <&cm41_i2c_lpcg 0>,
<&cm41_i2c_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_1_I2C>;
status = "disabled";
};
cm41_i2c_lpcg: clock-controller@3b630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x3b630000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>,
<&cm41_ipg_clk>;
bit-offset = <0 16>;
clock-output-names = "cm41_lpcg_i2c_clk",
"cm41_lpcg_i2c_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_1_I2C>;
};
cm41_intmux: intmux@3b400000 {
compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux";
reg = <0x3b400000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&cm41_ipg_clk>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_M4_1_INTMUX>;
status = "disabled";
};
};
|
