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|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2020 NXP
* Zhou Guoniu <guoniu.zhou@nxp.com>
*/
img_subsys: bus@58000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x58000000 0x0 0x58000000 0x1000000>;
img_ipg_clk: clock-img-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "img_ipg_clk";
};
img_axi_clk: clock-img-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
clock-output-names = "img_axi_clk";
};
img_pxl_clk: clock-img-pxl {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
clock-output-names = "img_pxl_clk";
};
csi0_core_lpcg: clock-controller@58223018 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58223018 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>;
bit-offset = <16>;
clock-output-names = "csi0_lpcg_core_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
csi0_esc_lpcg: clock-controller@5822301c {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5822301c 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>;
bit-offset = <16>;
clock-output-names = "csi0_lpcg_esc_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
csi1_core_lpcg: clock-controller@58243018 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58243018 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>;
bit-offset = <16>;
clock-output-names = "csi1_lpcg_core_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
csi1_esc_lpcg: clock-controller@5824301c {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5824301c 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>;
bit-offset = <16>;
clock-output-names = "csi1_lpcg_esc_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
pi0_pxl_lpcg: clock-controller@58263018 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58263018 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
bit-offset = <0>;
clock-output-names = "pi0_lpcg_pxl_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
pi0_ipg_lpcg: clock-controller@58263004 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58263004 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
bit-offset = <16>;
clock-output-names = "pi0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
pi0_misc_lpcg: clock-controller@5826301c {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5826301c 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>;
bit-offset = <0>;
clock-output-names = "pi0_lpcg_misc_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
pdma0_lpcg: clock-controller@58500000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58500000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma0_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
};
pdma1_lpcg: clock-controller@58510000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58510000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma1_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH1>;
};
pdma2_lpcg: clock-controller@58520000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58520000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma2_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH2>;
};
pdma3_lpcg: clock-controller@58530000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58530000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma3_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH3>;
};
pdma4_lpcg: clock-controller@58540000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58540000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma4_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH4>;
};
pdma5_lpcg: clock-controller@58550000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58550000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma5_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH5>;
};
pdma6_lpcg: clock-controller@58560000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58560000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma6_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH6>;
};
pdma7_lpcg: clock-controller@58570000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58570000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "pdma7_lpcg_clk";
power-domains = <&pd IMX_SC_R_ISI_CH7>;
};
csi0_pxl_lpcg: clock-controller@58580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58580000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "csi0_lpcg_pxl_clk";
power-domains = <&pd IMX_SC_R_CSI_0>;
};
csi1_pxl_lpcg: clock-controller@58590000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58590000 0x10000>;
#clock-cells = <1>;
clocks = <&img_pxl_clk>;
bit-offset = <0>;
clock-output-names = "csi1_lpcg_pxl_clk";
power-domains = <&pd IMX_SC_R_CSI_1>;
};
img_jpeg_dec_clk: clock-controller@585d0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x585d0000 0x10000>;
#clock-cells = <1>;
clocks = <&img_ipg_clk>, <&img_ipg_clk>;
bit-offset = <0 16>;
clock-output-names = "img_jpeg_dec_clk",
"img_jpeg_dec_ipg_clk";
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
};
img_jpeg_enc_clk: clock-controller@585f0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x585f0000 0x10000>;
#clock-cells = <1>;
clocks = <&img_ipg_clk>, <&img_ipg_clk>;
bit-offset = <0 16>;
clock-output-names = "img_jpeg_enc_clk",
"img_jpeg_enc_ipg_clk";
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
};
irqsteer_csi0: irqsteer@58220000 {
compatible = "fsl,imx-irqsteer";
reg = <0x58220000 0x1000>;
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <1>;
clocks = <&img_ipg_clk>;
clock-names = "ipg";
fsl,channel = <0>;
fsl,num-irqs = <32>;
power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_csi", "pd_isi_ch0";
status = "disabled";
};
irqsteer_csi1: irqsteer@58240000 {
compatible = "fsl,imx-irqsteer";
reg = <0x58240000 0x1000>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <1>;
clocks = <&img_ipg_clk>;
clock-names = "ipg";
fsl,channel = <0>;
fsl,num-irqs = <32>;
power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_csi", "pd_isi_ch0";
status = "disabled";
};
irqsteer_parallel: irqsteer@58260000 {
compatible = "fsl,imx-irqsteer";
reg = <0x58260000 0x1000>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <1>;
clocks = <&clk_dummy>;
clock-names = "ipg";
fsl,channel = <0>;
fsl,num-irqs = <32>;
power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_pi", "pd_isi_ch0";
status = "disabled";
};
gpio0_mipi_csi0: gpio@58222000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x58222000 0x1000>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_csi0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_csi", "pd_isi_ch0";
};
i2c_mipi_csi0: i2c@58226000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x58226000 0x1000>;
interrupts = <8>;
interrupt-parent = <&irqsteer_csi0>;
clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>,
<&img_ipg_clk>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
status = "disabled";
};
i2c0_parallel: i2c@58266000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x58266000 0x1000>;
interrupts = <8>;
interrupt-parent = <&irqsteer_parallel>;
clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>,
<&img_ipg_clk>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_PI_0_I2C_0>;
status = "disabled";
};
gpio0_mipi_csi1: gpio@58242000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x58242000 0x1000>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_csi1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_csi", "pd_isi_ch0";
};
i2c_mipi_csi1: i2c@58246000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x58246000 0x1000>;
interrupts = <8>;
interrupt-parent = <&irqsteer_csi1>;
clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>,
<&img_ipg_clk>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
status = "disabled";
};
cameradev: camera {
compatible = "fsl,mxc-md", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
isi_0: isi@58100000 {
compatible = "fsl,imx8-isi";
reg = <0x58100000 0x10000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma0_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH0>;
interface = <2 0 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
m2m_device{
compatible = "imx-isi-m2m";
status = "disabled";
};
};
isi_1: isi@58110000 {
compatible = "fsl,imx8-isi";
reg = <0x58110000 0x10000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma1_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH1>;
interface = <2 1 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isi_2: isi@58120000 {
compatible = "fsl,imx8-isi";
reg = <0x58120000 0x10000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma2_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH2>;
interface = <2 2 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isi_3: isi@58130000 {
compatible = "fsl,imx8-isi";
reg = <0x58130000 0x10000>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma3_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH3>;
interface = <2 3 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isi_4: isi@58140000 {
compatible = "fsl,imx8-isi";
reg = <0x58140000 0x10000>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma4_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH4>;
interface = <3 0 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isi_5: isi@58150000 {
compatible = "fsl,imx8-isi";
reg = <0x58150000 0x10000>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma5_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH5>;
interface = <3 1 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isi_6: isi@58160000 {
compatible = "fsl,imx8-isi";
reg = <0x58160000 0x10000>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma6_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH6>;
interface = <3 2 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isi_7: isi@58170000 {
compatible = "fsl,imx8-isi";
reg = <0x58170000 0x10000>;
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&pdma7_lpcg 0>;
clock-names = "per";
power-domains = <&pd IMX_SC_R_ISI_CH7>;
interface = <3 3 2>;
no-reset-control;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
mipi_csi_0: csi@58227000 {
compatible = "fsl,mxc-mipi-csi2";
reg = <0x58227000 0x1000>,
<0x58221000 0x1000>;
clocks = <&csi0_core_lpcg 0>,
<&csi0_esc_lpcg 0>,
<&csi0_pxl_lpcg 0>;
clock-names = "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&csi0_core_lpcg 0>,
<&csi0_esc_lpcg 0>;
assigned-clock-rates = <360000000>, <72000000>;
power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_csi", "pd_isi_ch0";
status = "disabled";
};
mipi_csi_1: csi@58247000{
compatible = "fsl,mxc-mipi-csi2";
reg = <0x58247000 0x1000>,
<0x58241000 0x1000>;
clocks = <&csi1_core_lpcg 0>,
<&csi1_esc_lpcg 0>,
<&csi1_pxl_lpcg 0>;
clock-names = "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&csi1_core_lpcg 0>,
<&csi1_esc_lpcg 0>;
assigned-clock-rates = <360000000>, <72000000>;
power-domains = <&pd IMX_SC_R_CSI_1>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_csi", "pd_isi_ch0";
status = "disabled";
};
parallel_csi: pcsi@58261000 {
compatible = "fsl,mxc-parallel-csi";
reg = <0x58261000 0x1000>;
clocks = <&pi0_pxl_lpcg 0>,
<&pi0_ipg_lpcg 0>,
<&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
clock-names = "pixel", "ipg", "div", "dpll";
assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
assigned-clock-rates = <160000000>; /* 160MHz */
power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>;
power-domain-names = "pd_pi", "pd_isi_ch0";
status = "disabled";
};
jpegdec: jpegdec@58400000 {
compatible = "fsl,imx8-jpgdec";
reg = <0x58400000 0x00050000 >;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_clk 0>,
<&img_jpeg_dec_clk 1>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_dec_clk 0>,
<&img_jpeg_dec_clk 1>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_ISI_CH0>,
<&pd IMX_SC_R_MJPEG_DEC_MP>,
<&pd IMX_SC_R_MJPEG_DEC_S0>,
<&pd IMX_SC_R_MJPEG_DEC_S1>,
<&pd IMX_SC_R_MJPEG_DEC_S2>,
<&pd IMX_SC_R_MJPEG_DEC_S3>;
power-domain-names = "pd_isi_ch0", "pd_dec_mp",
"pd_dec_s0", "pd_dec_s1",
"pd_dec_s2", "pd_dec_s3";
status = "disabled";
};
jpegenc: jpegenc@58450000 {
compatible = "fsl,imx8-jpgenc";
reg = <0x58450000 0x00050000 >;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_clk 0>,
<&img_jpeg_enc_clk 1>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_enc_clk 0>,
<&img_jpeg_enc_clk 1>;
assigned-clock-rates = <200000000>;
power-domains = <&pd IMX_SC_R_ISI_CH0>,
<&pd IMX_SC_R_MJPEG_ENC_MP>,
<&pd IMX_SC_R_MJPEG_ENC_S0>,
<&pd IMX_SC_R_MJPEG_ENC_S1>,
<&pd IMX_SC_R_MJPEG_ENC_S2>,
<&pd IMX_SC_R_MJPEG_ENC_S3>;
power-domain-names = "pd_isi_ch0", "pd_enc_mp",
"pd_enc_s0", "pd_enc_s1",
"pd_enc_s2", "pd_enc_s3";
status = "disabled";
};
};
};
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