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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
lcdif_subsys: bus@5a180000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5a180000 0x0 0x5a180000 0x500000>;
ipg_dma_clk: clock-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "ipg_dma_clk";
};
lcd_clk_lpcg: clock-controller@5a580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a580000 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
<&ipg_dma_clk>;
bit-offset = <0 16>;
clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk";
power-domains = <&pd IMX_SC_R_LCD_0>;
};
adma_lcdif: lcdif@5a180000 {
compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
reg = <0x5a180000 0x10000>;
clocks = <&lcd_clk_lpcg 0>,
<&lcd_clk_lpcg 1>,
<&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
assigned-clock-rates = <0>, <24000000>, <804000000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_LCD_0>;
status = "disabled";
};
};
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