path: root/arch/arm64/boot/dts/freescale/imx8dxl-phantom-mek.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019 NXP
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8qxp.dtsi"

/ {
	model = "Freescale i.MX8DXL Phantom MEK";
	compatible = "fsl,imx8dxl-phantom-mek", "fsl,imx8dxl-phantom", "fsl,imx8qxp";

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
		stdout-path = &lpuart0;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		m4_reserved: m4@0x88000000 {
			no-map;
			reg = <0 0x88000000 0 0x8000000>;
		};

		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90000000 0 0x400000>;
		};

		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x90400000 0 0x100000>;
		};
	};

	modem_reset: modem-reset {
		compatible = "gpio-reset";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pinctrl_modem_reset>;
		pinctrl-1 = <&pinctrl_modem_reset_sleep>;
		reset-gpios = <&lsio_gpio3 1 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		m4_reserved: m4@0x88000000 {
			no-map;
			reg = <0 0x88000000 0 0x8000000>;
		};

		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90000000 0 0x400000>;
		};

		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x90400000 0 0x100000>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_can0_en: regulator-can0-gen {
			compatible = "regulator-fixed";
			regulator-name = "can0-en";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&pca6416 2 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_can1_en: regulator-can1-gen {
			compatible = "regulator-fixed";
			regulator-name = "can1-en";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_can0_stby: regulator-can0-stby {
			compatible = "regulator-fixed";
			regulator-name = "can0-stby";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			vin-supply = <&reg_can0_en>;
		};

		reg_can1_stby: regulator-can1-stby {
			compatible = "regulator-fixed";
			regulator-name = "can1-stby";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			vin-supply = <&reg_can1_en>;
		};

		reg_fec2_supply: fec2_nvcc {
			compatible = "regulator-fixed";
			regulator-name = "fec2_nvcc";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			/*gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; removing as i2c bus is changing in new board */
			enable-active-high;
		};

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "SD1_SPWR";
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
			off-on-delay-us = <3480>;
			enable-active-high;
		};

		epdev_on: fixedregulator@100 {
			compatible = "regulator-fixed";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&pinctrl_wlreg_on>;
			pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "epdev_on";
			gpio = <&lsio_gpio3 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_reg_usb_vbus>;
			reg = <0>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_audio: fixedregulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "cs42888_supply";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};

	sound: sound {
		compatible = "fsl,imx7d-evk-wm8960",
			   "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		cpu-dai = <&sai1>;
		audio-codec = <&wm8960>;
		asrc-controller = <&asrc0>;
		codec-master;
		/*
		 * hp-det = <hp-det-pin hp-det-polarity>;
		 * hp-det-pin: JD1 JD2  or JD3
		 * hp-det-polarity = 0: hp detect high for headphone
		 * hp-det-polarity = 1: hp detect high for speaker
		 */
		hp-det = <2 0>;
		hp-det-gpios = <&lsio_gpio0 13 0>;
		mic-det-gpios = <&lsio_gpio0 13 0>;
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT2", "Mic Jack",
			"LINPUT3", "Mic Jack",
			"RINPUT1", "Main MIC",
			"RINPUT2", "Main MIC",
			"Mic Jack", "MICB",
			"Main MIC", "MICB",
			"CPU-Playback", "ASRC-Playback",
			"Playback", "CPU-Playback",
			"ASRC-Capture", "CPU-Capture",
			"CPU-Capture", "Capture";
	};
};

&lvds_subsys {
	status = "disabled";
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 */
	vdev-nums = <2>;
	reg = <0x0 0x90000000 0x0 0x20000>;
	memory-region = <&rpmsg_dma_reserved>;
	status = "okay";
};

&acm {
	status = "okay";
};

&asrc0 {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx8dxl-phantom-mek {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0		0x0600004c
				IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
				IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
			>;
		};

		pinctrl_esai0: esai0grp {
			fsl,pins = <
				IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR		0xc6000040
				IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST		0xc6000040
				IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR		0xc6000040
				IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT		0xc6000040
				IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0		0xc6000040
				IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1		0xc6000040
				IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3	0xc6000040
				IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2	0xc6000040
				IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1	0xc6000040
				IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0	0xc6000040
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				IMX8QXP_UART0_RX_ADMA_UART0_RX	0x06000020
				IMX8QXP_UART0_TX_ADMA_UART0_TX	0x06000020
			>;
		};

		pinctrl_lpuart1: lpuart1grp {
			fsl,pins = <
				IMX8QXP_UART1_TX_ADMA_UART1_TX		0x06000020
				IMX8QXP_UART1_RX_ADMA_UART1_RX		0x06000020
				IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B	0x06000020
				IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B	0x06000020
			>;
		};

		pinctrl_lpuart2: lpuart2grp {
			fsl,pins = <
				IMX8QXP_UART2_TX_ADMA_UART2_TX	0x06000020
				IMX8QXP_UART2_RX_ADMA_UART2_RX	0x06000020
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
				IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
				IMX8QXP_ENET0_MDC_CONN_ENET1_MDC			0x06000020
				IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO			0x06000020
				IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
				IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
				IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
				IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
				IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
				IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060
				IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
				IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
				IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
				IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
				IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
				IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
			>;
		};

		pinctrl_flexcan1: flexcan0grp {
			fsl,pins = <
				IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21
				IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21
			>;
		};

		pinctrl_flexcan2: flexcan1grp {
			fsl,pins = <
				IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX		0x21
				IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX		0x21
			>;
		};

		pinctrl_flexspi0: flexspi0grp {
			fsl,pins = <
				IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
				IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
				IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
				IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
				IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
				IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
				IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
				IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
				IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
				IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
				IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
				IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
			>;
		};

		pinctrl_cm40_i2c: cm40i2cgrp {
			fsl,pins = <
				IMX8QXP_ADC_IN1_M40_I2C0_SDA	0x0600004c
				IMX8QXP_ADC_IN0_M40_I2C0_SCL	0x0600004c
			>;
		};

		pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp {
			fsl,pins = <
				IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01	0x07800021
			>;
		};

		pinctrl_modem_reset: modemresetgrp {
			fsl,pins = <
				IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01	0x06000021
			>;
		};

		pinctrl_modem_reset_sleep: modemreset_sleepgrp {
			fsl,pins = <
				IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01	0x07800021
			>;
		};

		pinctrl_sai1: sai1grp {
			fsl,pins = <
				IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD	0x06000040
				IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC	0x06000040
				IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS	0x06000040
				IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD	0x06000060
				IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13	0x06000040
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
			>;
		};
		pinctrl_reg_usb_vbus: regusbvbusgrp {
			fsl,pins = <
				IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
			fsl,pins = <
				IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021
				IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021
				IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
				IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
				IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
				IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
				IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
				IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
				IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_pcieb: pcieagrp{
			fsl,pins = <
				IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
				IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
				IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
				IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00				0x06000021
				IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18			0x06000021
			>;
		};

		pinctrl_gpio3: gpio3grp{
			fsl,pins = <
				IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07		0xC0000041
				IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08		0xC0000041
			>;
		};

		pinctrl_wlreg_on: wlregongrp{
			fsl,pins = <
				IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x06000000
			>;
		};

		pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
			fsl,pins = <
				IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x07800000
			>;
		};
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	resets = <&modem_reset>;
	status = "okay";
};


&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy0>;
	phy-reset-gpio=<&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can0_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can1_stby>;
	status = "okay";
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt35xu512aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt35xu512aba";
		spi-max-frequency = <133000000>;
		spi-nor,ddr-quad-read-dummy = <4>;
	};
};

&cm40_intmux {
	status = "okay";
};

&cm40_i2c {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_cm40_i2c>;
	status = "okay";

	wm8960: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&mclkout0_lpcg 0>;
		clock-names = "mclk";
		wlf,shared-lrclk;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				<&mclkout0_lpcg 0>;
		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
	};

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

};

&sai1 {
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			<&sai1_lpcg 0>; /* FIXME: should be sai1, original code is 0 */
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	fsl,sai-synchronous-rx;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-polarity-active-high;
	disable-over-current;
	status = "okay";
};

&usbphy1 {
	fsl,tx-d-cal = <114>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&lsio_gpio3 {
	pinctrl-name = "default";
	pinctrl-0 = <&pinctrl_gpio3>;
};

&tsens {
	tsens-num = <3>;
};

&thermal_zones {
	cpu-thermal0 {
		cooling-maps {
			map0 {
				cooling-device =
				<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens 497>;
		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};
			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};
		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&a35_opp_table {
	/delete-node/ opp-900000000;
};

&cpus {
	/delete-node/ cpu@2;
	/delete-node/ cpu@3;
};

&pcieb{
	compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcieb>;
	reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
	epdev_on-supply = <&epdev_on>;
	ext_osc = <1>;
	status = "okay";
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 */
	vdev-nums = <2>;
	reg = <0x0 0x90000000 0x0 0x20000>;
	memory-region = <&rpmsg_dma_reserved>;
	status = "okay";
};