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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
&ddr_pmu0 {
compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
&ddr_subsys {
db_ipg_clk: clock-db-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <456000000>;
clock-output-names = "db_ipg_clk";
};
db_pmu0: db-pmu@5ca40000 {
compatible = "fsl,imx8dxl-db-pmu";
reg = <0x5ca40000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;
clock-names = "ipg", "cnt";
power-domains = <&pd IMX_SC_R_PERF>;
};
db_pmu0_lpcg: clock-controller@5cae0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5cae0000 0x10000>;
#clock-cells = <1>;
clocks = <&db_ipg_clk>, <&db_ipg_clk>;
bit-offset = <0 16>;
clock-output-names = "perf_lpcg_cnt_clk",
"perf_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_PERF>;
};
};
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