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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 NXP
*/
/dts-v1/;
#include "imx8mp-evk.dts"
/ {
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c_rpbus_3;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
m4_reserved: m4@0x80000000 {
no-map;
reg = <0 0x80000000 0 0x1000000>;
};
vdev0vring0: vdev0vring0@55000000 {
reg = <0 0x55000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@55008000 {
reg = <0 0x55008000 0 0x8000>;
no-map;
};
vdevbuffer: vdevbuffer@55400000 {
compatible = "shared-dma-pool";
reg = <0 0x55400000 0 0x100000>;
no-map;
};
rsc_table: rsc_table@550ff000 {
reg = <0 0x550ff000 0 0x1000>;
no-map;
};
audio_reserved: audio@0x81000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x81000000 0 0x10000000>;
};
micfil_reserved: mic_rpmsg@91000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x91000000 0 0x100000>;
};
};
sound-wm8960 {
status = "disabled";
};
sound-micfil {
status = "disabled";
};
rpmsg_audio: rpmsg_audio {
compatible = "fsl,imx8mp-rpmsg-audio";
model = "wm8960-audio";
fsl,platform = "rpmsg-audio-channel";
fsl,enable-lpa;
fsl,rpmsg-out;
fsl,rpmsg-in;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>;
clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
audio-codec = <&codec>;
memory-region = <&audio_reserved>;
power-domains = <&audiomix_pd>;
audio-routing =
"LINPUT1", "MICB",
"LINPUT3", "MICB";
status = "okay";
};
rpmsg_micfil: rpmsg_micfil {
compatible = "fsl,imx8mp-rpmsg-audio";
model = "micfil-audio";
fsl,platform = "rpmsg-micfil-channel";
fsl,enable-lpa;
fsl,rpmsg-in;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>;
clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
memory-region = <&micfil_reserved>;
power-domains = <&audiomix_pd>;
status = "okay";
};
imx8mp-cm7 {
compatible = "fsl,imx8mn-cm7";
rsc-da = <0x55000000>;
clocks = <&clk IMX8MP_CLK_M7_DIV>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
status = "okay";
fsl,startup-delay-ms = <500>;
};
};
/*
* ATTENTION: M7 may use IPs like below
* ECSPI0/ECSPI2, FLEXCAN, GPIO1/GPIO5, GPT1, I2C3, I2S3, UART4,
* PWM4, SDMA1/SDMA2
*/
&ecspi2 {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexspi {
status = "disabled";
};
/delete-node/ &i2c3;
&i2c_rpbus_3 {
compatible = "fsl,i2c-rpbus";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
ov5640_1: ov5640_mipi@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <0>;
powerdown-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "disabled";
port {
ov5640_mipi_1_ep: endpoint {
remote-endpoint = <&mipi_csi1_ep>;
data-lanes = <1 2>;
clock-lanes = <0>;
};
};
};
codec: wm8960@1a {
compatible = "wlf,wm8960,lpa";
reg = <0x1a>;
wlf,shared-lrclk;
SPKVDD1-supply = <®_audio_pwr>;
};
};
&pwm4{
status = "disabled";
};
&sai3 {
status = "disabled";
};
&micfil {
status = "disabled";
};
&sdma3{
status = "disabled";
};
&uart3 {
status = "disabled";
};
&uart4 {
status = "disabled";
};
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