blob: 33d7dc1a047f2e888473f8261b5fa9f8df53c748 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 NXP
*/
#include "imx8mq-evk.dts"
/ {
modem_reset: modem-reset {
reset-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
};
usdhc2_pwrseq: usdhc2_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
};
};
&pinctrl_usdhc2 {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x46
>;
};
&pinctrl_usdhc2_100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
>;
};
&pinctrl_usdhc2_200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
>;
};
&pcie0{
status = "disabled";
};
&pcie1{
status = "disabled";
};
&usdhc2 {
pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/delete-property/ cd-gpios;
pm-ignore-notify;
keep-power-in-suspend;
non-removable;
cap-power-off-card;
mmc-pwrseq = <&usdhc2_pwrseq>;
};
|
