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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&lsio_subsys {
lsio_mu6: mailbox@5d210000 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d210000 0x10000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_6A>;
};
lsio_mu8: mailbox@5d230000 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d230000 0x10000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_8A>;
status = "disabled";
};
lsio_mu8b: mailbox@5d2c0000 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d2c0000 0x10000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
fsl,mu-side-b;
power-domains = <&pd IMX_SC_R_MU_8B>;
status = "disabled";
};
};
&lsio_gpio0 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio1 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio2 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio3 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio4 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio5 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio6 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio7 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_mu0 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu1 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu2 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu3 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
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