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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 NXP
*/
#include "imx8ulp-evk.dts"
/ {
model = "NXP i.MX8ULP 9X9 EVK";
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power-on {
label = "PowerOn";
gpios = <&gpiof 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
};
};
&iomuxc1 {
pinctrl_sai6: sai6grp {
fsl,pins = <
MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43
MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43
MX8ULP_PAD_PTE14__I2S6_TXD2 0x43
MX8ULP_PAD_PTE6__I2S6_RXD0 0x43
>;
};
};
&pinctrl_dsi {
fsl,pins = <
MX8ULP_PAD_PTF21__PTF21 0x3
>;
};
&pinctrl_enet {
fsl,pins = <
MX8ULP_PAD_PTF9__ENET0_MDC 0x43
MX8ULP_PAD_PTF8__ENET0_MDIO 0x43
MX8ULP_PAD_PTF5__ENET0_RXER 0x43
MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTF0__ENET0_RXD1 0x43
MX8ULP_PAD_PTF4__ENET0_TXEN 0x43
MX8ULP_PAD_PTF3__ENET0_TXD0 0x43
MX8ULP_PAD_PTF2__ENET0_TXD1 0x43
MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
&pinctrl_gpio_keys {
fsl,pins = <
MX8ULP_PAD_PTF11__PTF11 0x3
>;
};
&pinctrl_otgid1 {
fsl,pins = <
MX8ULP_PAD_PTE16__USB0_ID 0x10003
MX8ULP_PAD_PTE18__USB0_OC 0x10003
>;
};
&pinctrl_otgid2 {
fsl,pins = <
MX8ULP_PAD_PTD23__USB1_ID 0x10003
MX8ULP_PAD_PTE20__USB1_OC 0x10003
>;
};
&i2c_rpbus_0 {
fxls8974@18 {
compatible = "nxp,fxls8974cf";
reg = <0x18>;
drive-open-drain;
};
};
&pinctrl_lpuart6 {
fsl,pins = <
MX8ULP_PAD_PTF18__LPUART6_TX 0x3
MX8ULP_PAD_PTF19__LPUART6_RX 0x3
MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x3
MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x3
>;
};
&lpspi5 { /* conflict with lpuart6 PAD_PTF16-19 */
status = "disabled";
};
&lpuart6 {
pinctrl-assert-gpios = <&pca6416_1 10 GPIO_ACTIVE_LOW>;
};
&sai5 {
status = "disabled";
};
&sai6 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai6>;
pinctrl-1 = <&pinctrl_sai6>;
assigned-clocks = <&cgc2 IMX8ULP_CLK_SAI6_SEL>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
fsl,dataline = <0 0x01 0x04>;
status = "okay";
};
&btcpu {
sound-dai = <&sai6>;
};
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