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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
#include "imx8ulp-evk.dts"
/ {
imx8ulp-lpm {
sys-dvfs-enabled;
};
};
&gpu3d {
assigned-clock-rates = <200000000>, <200000000>, <200000000>;
};
&gpu2d {
assigned-clock-rates = <200000000>, <200000000>, <200000000>;
};
&dcnano {
/* Place Holder */
};
&mipi_csi0 {
assigned-clock-rates = <396000000>,
<176000000>,
<132000000>,
<396000000>,
<176000000>,
<132000000>,
<79200000>;
};
&epdc {
/* Place Holder */
};
&dsp {
assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>;
assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>;
assigned-clock-rates = <0>, <260000000>;
};
&i3c2 {
assigned-clock-rates = <24000000>;
};
&usdhc0 {
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC0>;
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
assigned-clock-rates = <198000000>, <198000000>;
};
&usdhc1 {
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC1>;
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
assigned-clock-rates = <198000000>, <198000000>;
};
&usdhc2 {
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>, <&pcc4 IMX8ULP_CLK_USDHC2>;
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
assigned-clock-rates = <198000000>, <198000000>;
};
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