summaryrefslogtreecommitdiff
path: root/include/asm-avr32/ocd.h
blob: 996405e0393f8e999289d503d2902d9e50a47e6e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
/*
 * AVR32 OCD Interface and register definitions
 *
 * Copyright (C) 2004-2007 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ASM_AVR32_OCD_H
#define __ASM_AVR32_OCD_H

/* OCD Register offsets. Abbreviations used below:
 *
 *      BP      Breakpoint
 *      Comm    Communication
 *      DT      Data Trace
 *      PC      Program Counter
 *      PID     Process ID
 *      R/W     Read/Write
 *      WP      Watchpoint
 */
#define OCD_DID				0x0000  /* Device ID */
#define OCD_DC				0x0008  /* Development Control */
#define OCD_DS				0x0010  /* Development Status */
#define OCD_RWCS			0x001c  /* R/W Access Control */
#define OCD_RWA				0x0024  /* R/W Access Address */
#define OCD_RWD				0x0028  /* R/W Access Data */
#define OCD_WT				0x002c  /* Watchpoint Trigger */
#define OCD_DTC				0x0034  /* Data Trace Control */
#define OCD_DTSA0			0x0038  /* DT Start Addr Channel 0 */
#define OCD_DTSA1			0x003c  /* DT Start Addr Channel 1 */
#define OCD_DTEA0			0x0048  /* DT End Addr Channel 0 */
#define OCD_DTEA1			0x004c  /* DT End Addr Channel 1 */
#define OCD_BWC0A			0x0058  /* PC BP/WP Control 0A */
#define OCD_BWC0B			0x005c  /* PC BP/WP Control 0B */
#define OCD_BWC1A			0x0060  /* PC BP/WP Control 1A */
#define OCD_BWC1B			0x0064  /* PC BP/WP Control 1B */
#define OCD_BWC2A			0x0068  /* PC BP/WP Control 2A */
#define OCD_BWC2B			0x006c  /* PC BP/WP Control 2B */
#define OCD_BWC3A			0x0070  /* Data BP/WP Control 3A */
#define OCD_BWC3B			0x0074  /* Data BP/WP Control 3B */
#define OCD_BWA0A			0x0078  /* PC BP/WP Address 0A */
#define OCD_BWA0B			0x007c  /* PC BP/WP Address 0B */
#define OCD_BWA1A			0x0080  /* PC BP/WP Address 1A */
#define OCD_BWA1B			0x0084  /* PC BP/WP Address 1B */
#define OCD_BWA2A			0x0088  /* PC BP/WP Address 2A */
#define OCD_BWA2B			0x008c  /* PC BP/WP Address 2B */
#define OCD_BWA3A			0x0090  /* Data BP/WP Address 3A */
#define OCD_BWA3B			0x0094  /* Data BP/WP Address 3B */
#define OCD_NXCFG			0x0100  /* Nexus Configuration */
#define OCD_DINST			0x0104  /* Debug Instruction */
#define OCD_DPC				0x0108  /* Debug Program Counter */
#define OCD_CPUCM			0x010c  /* CPU Control Mask */
#define OCD_DCCPU			0x0110  /* Debug Comm CPU */
#define OCD_DCEMU			0x0114  /* Debug Comm Emulator */
#define OCD_DCSR			0x0118  /* Debug Comm Status */
#define OCD_PID				0x011c  /* Ownership Trace PID */
#define OCD_EPC0			0x0120  /* Event Pair Control 0 */
#define OCD_EPC1			0x0124  /* Event Pair Control 1 */
#define OCD_EPC2			0x0128  /* Event Pair Control 2 */
#define OCD_EPC3			0x012c  /* Event Pair Control 3 */
#define OCD_AXC				0x0130  /* AUX port Control */

/* Bits in DID */
#define OCD_DID_MID_START		1
#define OCD_DID_MID_SIZE		11
#define OCD_DID_PN_START		12
#define OCD_DID_PN_SIZE			16
#define OCD_DID_RN_START		28
#define OCD_DID_RN_SIZE			4

/* Bits in DC */
#define OCD_DC_TM_START			0
#define OCD_DC_TM_SIZE			2
#define OCD_DC_EIC_START		3
#define OCD_DC_EIC_SIZE			2
#define OCD_DC_OVC_START		5
#define OCD_DC_OVC_SIZE			3
#define OCD_DC_SS_BIT			8
#define OCD_DC_DBR_BIT			12
#define OCD_DC_DBE_BIT			13
#define OCD_DC_EOS_START		20
#define OCD_DC_EOS_SIZE			2
#define OCD_DC_SQA_BIT			22
#define OCD_DC_IRP_BIT			23
#define OCD_DC_IFM_BIT			24
#define OCD_DC_TOZ_BIT			25
#define OCD_DC_TSR_BIT			26
#define OCD_DC_RID_BIT			27
#define OCD_DC_ORP_BIT			28
#define OCD_DC_MM_BIT			29
#define OCD_DC_RES_BIT			30
#define OCD_DC_ABORT_BIT		31

/* Bits in DS */
#define OCD_DS_SSS_BIT			0
#define OCD_DS_SWB_BIT			1
#define OCD_DS_HWB_BIT			2
#define OCD_DS_HWE_BIT			3
#define OCD_DS_STP_BIT			4
#define OCD_DS_DBS_BIT			5
#define OCD_DS_BP_START			8
#define OCD_DS_BP_SIZE			8
#define OCD_DS_INC_BIT			24
#define OCD_DS_BOZ_BIT			25
#define OCD_DS_DBA_BIT			26
#define OCD_DS_EXB_BIT			27
#define OCD_DS_NTBF_BIT			28

/* Bits in RWCS */
#define OCD_RWCS_DV_BIT			0
#define OCD_RWCS_ERR_BIT		1
#define OCD_RWCS_CNT_START		2
#define OCD_RWCS_CNT_SIZE		14
#define OCD_RWCS_CRC_BIT		19
#define OCD_RWCS_NTBC_START		20
#define OCD_RWCS_NTBC_SIZE		2
#define OCD_RWCS_NTE_BIT		22
#define OCD_RWCS_NTAP_BIT		23
#define OCD_RWCS_WRAPPED_BIT		24
#define OCD_RWCS_CCTRL_START		25
#define OCD_RWCS_CCTRL_SIZE		2
#define OCD_RWCS_SZ_START		27
#define OCD_RWCS_SZ_SIZE		3
#define OCD_RWCS_RW_BIT			30
#define OCD_RWCS_AC_BIT			31

/* Bits in RWA */
#define OCD_RWA_RWA_START		0
#define OCD_RWA_RWA_SIZE		32

/* Bits in RWD */
#define OCD_RWD_RWD_START		0
#define OCD_RWD_RWD_SIZE		32

/* Bits in WT */
#define OCD_WT_DTE_START		20
#define OCD_WT_DTE_SIZE			3
#define OCD_WT_DTS_START		23
#define OCD_WT_DTS_SIZE			3
#define OCD_WT_PTE_START		26
#define OCD_WT_PTE_SIZE			3
#define OCD_WT_PTS_START		29
#define OCD_WT_PTS_SIZE			3

/* Bits in DTC */
#define OCD_DTC_T0WP_BIT		0
#define OCD_DTC_T1WP_BIT		1
#define OCD_DTC_ASID0EN_BIT		2
#define OCD_DTC_ASID0_START		3
#define OCD_DTC_ASID0_SIZE		8
#define OCD_DTC_ASID1EN_BIT		11
#define OCD_DTC_ASID1_START		12
#define OCD_DTC_ASID1_SIZE		8
#define OCD_DTC_RWT1_START		28
#define OCD_DTC_RWT1_SIZE		2
#define OCD_DTC_RWT0_START		30
#define OCD_DTC_RWT0_SIZE		2

/* Bits in DTSA0 */
#define OCD_DTSA0_DTSA_START		0
#define OCD_DTSA0_DTSA_SIZE		32

/* Bits in DTSA1 */
#define OCD_DTSA1_DTSA_START		0
#define OCD_DTSA1_DTSA_SIZE		32

/* Bits in DTEA0 */
#define OCD_DTEA0_DTEA_START		0
#define OCD_DTEA0_DTEA_SIZE		32

/* Bits in DTEA1 */
#define OCD_DTEA1_DTEA_START		0
#define OCD_DTEA1_DTEA_SIZE		32

/* Bits in BWC0A */
#define OCD_BWC0A_ASIDEN_BIT		0
#define OCD_BWC0A_ASID_START		1
#define OCD_BWC0A_ASID_SIZE		8
#define OCD_BWC0A_EOC_BIT		14
#define OCD_BWC0A_AME_BIT		25
#define OCD_BWC0A_BWE_START		30
#define OCD_BWC0A_BWE_SIZE		2

/* Bits in BWC0B */
#define OCD_BWC0B_ASIDEN_BIT		0
#define OCD_BWC0B_ASID_START		1
#define OCD_BWC0B_ASID_SIZE		8
#define OCD_BWC0B_EOC_BIT		14
#define OCD_BWC0B_AME_BIT		25
#define OCD_BWC0B_BWE_START		30
#define OCD_BWC0B_BWE_SIZE		2

/* Bits in BWC1A */
#define OCD_BWC1A_ASIDEN_BIT		0
#define OCD_BWC1A_ASID_START		1
#define OCD_BWC1A_ASID_SIZE		8
#define OCD_BWC1A_EOC_BIT		14
#define OCD_BWC1A_AME_BIT		25
#define OCD_BWC1A_BWE_START		30
#define OCD_BWC1A_BWE_SIZE		2

/* Bits in BWC1B */
#define OCD_BWC1B_ASIDEN_BIT		0
#define OCD_BWC1B_ASID_START		1
#define OCD_BWC1B_ASID_SIZE		8
#define OCD_BWC1B_EOC_BIT		14
#define OCD_BWC1B_AME_BIT		25
#define OCD_BWC1B_BWE_START		30
#define OCD_BWC1B_BWE_SIZE		2

/* Bits in BWC2A */
#define OCD_BWC2A_ASIDEN_BIT		0
#define OCD_BWC2A_ASID_START		1
#define OCD_BWC2A_ASID_SIZE		8
#define OCD_BWC2A_EOC_BIT		14
#define OCD_BWC2A_AMB_START		20
#define OCD_BWC2A_AMB_SIZE		5
#define OCD_BWC2A_AME_BIT		25
#define OCD_BWC2A_BWE_START		30
#define OCD_BWC2A_BWE_SIZE		2

/* Bits in BWC2B */
#define OCD_BWC2B_ASIDEN_BIT		0
#define OCD_BWC2B_ASID_START		1
#define OCD_BWC2B_ASID_SIZE		8
#define OCD_BWC2B_EOC_BIT		14
#define OCD_BWC2B_AME_BIT		25
#define OCD_BWC2B_BWE_START		30
#define OCD_BWC2B_BWE_SIZE		2

/* Bits in BWC3A */
#define OCD_BWC3A_ASIDEN_BIT		0
#define OCD_BWC3A_ASID_START		1
#define OCD_BWC3A_ASID_SIZE		8
#define OCD_BWC3A_SIZE_START		9
#define OCD_BWC3A_SIZE_SIZE		3
#define OCD_BWC3A_EOC_BIT		14
#define OCD_BWC3A_BWO_START		16
#define OCD_BWC3A_BWO_SIZE		2
#define OCD_BWC3A_BME_START		20
#define OCD_BWC3A_BME_SIZE		4
#define OCD_BWC3A_BRW_START		28
#define OCD_BWC3A_BRW_SIZE		2
#define OCD_BWC3A_BWE_START		30
#define OCD_BWC3A_BWE_SIZE		2

/* Bits in BWC3B */
#define OCD_BWC3B_ASIDEN_BIT		0
#define OCD_BWC3B_ASID_START		1
#define OCD_BWC3B_ASID_SIZE		8
#define OCD_BWC3B_SIZE_START		9
#define OCD_BWC3B_SIZE_SIZE		3
#define OCD_BWC3B_EOC_BIT		14
#define OCD_BWC3B_BWO_START		16
#define OCD_BWC3B_BWO_SIZE		2
#define OCD_BWC3B_BME_START		20
#define OCD_BWC3B_BME_SIZE		4
#define OCD_BWC3B_BRW_START		28
#define OCD_BWC3B_BRW_SIZE		2
#define OCD_BWC3B_BWE_START		30
#define OCD_BWC3B_BWE_SIZE		2

/* Bits in BWA0A */
#define OCD_BWA0A_BWA_START		0
#define OCD_BWA0A_BWA_SIZE		32

/* Bits in BWA0B */
#define OCD_BWA0B_BWA_START		0
#define OCD_BWA0B_BWA_SIZE		32

/* Bits in BWA1A */
#define OCD_BWA1A_BWA_START		0
#define OCD_BWA1A_BWA_SIZE		32

/* Bits in BWA1B */
#define OCD_BWA1B_BWA_START		0
#define OCD_BWA1B_BWA_SIZE		32

/* Bits in BWA2A */
#define OCD_BWA2A_BWA_START		0
#define OCD_BWA2A_BWA_SIZE		32

/* Bits in BWA2B */
#define OCD_BWA2B_BWA_START		0
#define OCD_BWA2B_BWA_SIZE		32

/* Bits in BWA3A */
#define OCD_BWA3A_BWA_START		0
#define OCD_BWA3A_BWA_SIZE		32

/* Bits in BWA3B */
#define OCD_BWA3B_BWA_START		0
#define OCD_BWA3B_BWA_SIZE		32

/* Bits in NXCFG */
#define OCD_NXCFG_NXARCH_START		0
#define OCD_NXCFG_NXARCH_SIZE		4
#define OCD_NXCFG_NXOCD_START		4
#define OCD_NXCFG_NXOCD_SIZE		4
#define OCD_NXCFG_NXPCB_START		8
#define OCD_NXCFG_NXPCB_SIZE		4
#define OCD_NXCFG_NXDB_START		12
#define OCD_NXCFG_NXDB_SIZE		4
#define OCD_NXCFG_MXMSEO_BIT		16
#define OCD_NXCFG_NXMDO_START		17
#define OCD_NXCFG_NXMDO_SIZE		4
#define OCD_NXCFG_NXPT_BIT		21
#define OCD_NXCFG_NXOT_BIT		22
#define OCD_NXCFG_NXDWT_BIT		23
#define OCD_NXCFG_NXDRT_BIT		24
#define OCD_NXCFG_NXDTC_START		25
#define OCD_NXCFG_NXDTC_SIZE		3
#define OCD_NXCFG_NXDMA_BIT		28

/* Bits in DINST */
#define OCD_DINST_DINST_START		0
#define OCD_DINST_DINST_SIZE		32

/* Bits in CPUCM */
#define OCD_CPUCM_BEM_BIT		1
#define OCD_CPUCM_FEM_BIT		2
#define OCD_CPUCM_REM_BIT		3
#define OCD_CPUCM_IBEM_BIT		4
#define OCD_CPUCM_IEEM_BIT		5

/* Bits in DCCPU */
#define OCD_DCCPU_DATA_START		0
#define OCD_DCCPU_DATA_SIZE		32

/* Bits in DCEMU */
#define OCD_DCEMU_DATA_START		0
#define OCD_DCEMU_DATA_SIZE		32

/* Bits in DCSR */
#define OCD_DCSR_CPUD_BIT		0
#define OCD_DCSR_EMUD_BIT		1

/* Bits in PID */
#define OCD_PID_PROCESS_START		0
#define OCD_PID_PROCESS_SIZE		32

/* Bits in EPC0 */
#define OCD_EPC0_RNG_START		0
#define OCD_EPC0_RNG_SIZE		2
#define OCD_EPC0_CE_BIT			4
#define OCD_EPC0_ECNT_START		16
#define OCD_EPC0_ECNT_SIZE		16

/* Bits in EPC1 */
#define OCD_EPC1_RNG_START		0
#define OCD_EPC1_RNG_SIZE		2
#define OCD_EPC1_ATB_BIT		5
#define OCD_EPC1_AM_BIT			6

/* Bits in EPC2 */
#define OCD_EPC2_RNG_START		0
#define OCD_EPC2_RNG_SIZE		2
#define OCD_EPC2_DB_START		2
#define OCD_EPC2_DB_SIZE		2

/* Bits in EPC3 */
#define OCD_EPC3_RNG_START		0
#define OCD_EPC3_RNG_SIZE		2
#define OCD_EPC3_DWE_BIT		2

/* Bits in AXC */
#define OCD_AXC_DIV_START		0
#define OCD_AXC_DIV_SIZE		4
#define OCD_AXC_AXE_BIT			8
#define OCD_AXC_AXS_BIT			9
#define OCD_AXC_DDR_BIT			10
#define OCD_AXC_LS_BIT			11
#define OCD_AXC_REX_BIT			12
#define OCD_AXC_REXTEN_BIT		13

/* Constants for DC:EIC */
#define OCD_EIC_PROGRAM_AND_DATA_TRACE	0
#define OCD_EIC_BREAKPOINT		1
#define OCD_EIC_NOP			2

/* Constants for DC:OVC */
#define OCD_OVC_OVERRUN			0
#define OCD_OVC_DELAY_CPU_BTM		1
#define OCD_OVC_DELAY_CPU_DTM		2
#define OCD_OVC_DELAY_CPU_BTM_DTM	3

/* Constants for DC:EOS */
#define OCD_EOS_NOP			0
#define OCD_EOS_DEBUG_MODE		1
#define OCD_EOS_BREAKPOINT_WATCHPOINT	2
#define OCD_EOS_THQ			3

/* Constants for RWCS:NTBC */
#define OCD_NTBC_OVERWRITE		0
#define OCD_NTBC_DISABLE		1
#define OCD_NTBC_BREAKPOINT		2

/* Constants for RWCS:CCTRL */
#define OCD_CCTRL_AUTO			0
#define OCD_CCTRL_CACHED		1
#define OCD_CCTRL_UNCACHED		2

/* Constants for RWCS:SZ */
#define OCD_SZ_BYTE			0
#define OCD_SZ_HALFWORD			1
#define OCD_SZ_WORD			2

/* Constants for WT:PTS */
#define OCD_PTS_DISABLED		0
#define OCD_PTS_PROGRAM_0B		1
#define OCD_PTS_PROGRAM_1A		2
#define OCD_PTS_PROGRAM_1B		3
#define OCD_PTS_PROGRAM_2A		4
#define OCD_PTS_PROGRAM_2B		5
#define OCD_PTS_DATA_3A			6
#define OCD_PTS_DATA_3B			7

/* Constants for DTC:RWT1 */
#define OCD_RWT1_NO_TRACE		0
#define OCD_RWT1_DATA_READ		1
#define OCD_RWT1_DATA_WRITE		2
#define OCD_RWT1_DATA_READ_WRITE	3

/* Constants for DTC:RWT0 */
#define OCD_RWT0_NO_TRACE		0
#define OCD_RWT0_DATA_READ		1
#define OCD_RWT0_DATA_WRITE		2
#define OCD_RWT0_DATA_READ_WRITE	3

/* Constants for BWC0A:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC0B:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC1A:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC1B:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC2A:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC2B:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC3A:SIZE */
#define OCD_SIZE_BYTE_ACCESS		4
#define OCD_SIZE_HALFWORD_ACCESS	5
#define OCD_SIZE_WORD_ACCESS		6
#define OCD_SIZE_DOUBLE_WORD_ACCESS	7

/* Constants for BWC3A:BRW */
#define OCD_BRW_READ_BREAK		0
#define OCD_BRW_WRITE_BREAK		1
#define OCD_BRW_ANY_ACCES_BREAK		2

/* Constants for BWC3A:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for BWC3B:SIZE */
#define OCD_SIZE_BYTE_ACCESS		4
#define OCD_SIZE_HALFWORD_ACCESS	5
#define OCD_SIZE_WORD_ACCESS		6
#define OCD_SIZE_DOUBLE_WORD_ACCESS	7

/* Constants for BWC3B:BRW */
#define OCD_BRW_READ_BREAK		0
#define OCD_BRW_WRITE_BREAK		1
#define OCD_BRW_ANY_ACCES_BREAK		2

/* Constants for BWC3B:BWE */
#define OCD_BWE_DISABLED		0
#define OCD_BWE_BREAKPOINT_ENABLED	1
#define OCD_BWE_WATCHPOINT_ENABLED	3

/* Constants for EPC0:RNG */
#define OCD_RNG_DISABLED		0
#define OCD_RNG_EXCLUSIVE		1
#define OCD_RNG_INCLUSIVE		2

/* Constants for EPC1:RNG */
#define OCD_RNG_DISABLED		0
#define OCD_RNG_EXCLUSIVE		1
#define OCD_RNG_INCLUSIVE		2

/* Constants for EPC2:RNG */
#define OCD_RNG_DISABLED		0
#define OCD_RNG_EXCLUSIVE		1
#define OCD_RNG_INCLUSIVE		2

/* Constants for EPC2:DB */
#define OCD_DB_DISABLED			0
#define OCD_DB_CHAINED_B		1
#define OCD_DB_CHAINED_A		2
#define OCD_DB_AHAINED_A_AND_B		3

/* Constants for EPC3:RNG */
#define OCD_RNG_DISABLED		0
#define OCD_RNG_EXCLUSIVE		1
#define OCD_RNG_INCLUSIVE		2

#ifndef __ASSEMBLER__

/* Register access macros */
static inline unsigned long __ocd_read(unsigned int reg)
{
	return __builtin_mfdr(reg);
}

static inline void __ocd_write(unsigned int reg, unsigned long value)
{
	__builtin_mtdr(reg, value);
}

#define ocd_read(reg)			__ocd_read(OCD_##reg)
#define ocd_write(reg, value)		__ocd_write(OCD_##reg, value)

#endif /* !__ASSEMBLER__ */

#endif /* __ASM_AVR32_OCD_H */