diff options
| author | Igor Opaniuk <igor.opaniuk@toradex.com> | 2019-11-28 15:56:21 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-12-23 10:30:21 +0100 |
| commit | 694e2136eefc2d110f44b26218c03e44a1e88235 (patch) | |
| tree | 29dac6daec4e02040793bdb85ee52ae830fd659f /arch/arm/mach-imx/mx7/soc.c | |
| parent | bc138ed0a86f0ca8f870c419955f07f3f21b7dfa (diff) | |
mach-imx: bootaux: elf firmware supportVerdin-iMX8MM_Console-Image_3.0b3.118-20200101Colibri-iMX8X_Console-Image_3.0b3.118-20200101Colibri-iMX7_Console-Image_3.0b3.118-20200101Colibri-iMX7-eMMC_Console-Image_3.0b3.118-20200101Colibri-iMX6_Console-Image_3.0b3.118-20200101Colibri-iMX6ULL_Console-Image_3.0b3.118-20200101Apalis-iMX8_Console-Image_3.0b3.118-20200101Apalis-iMX8X_Console-Image_3.0b3.118-20191231Apalis-iMX6_Console-Image_3.0b3.118-20191231Apalis-TK1_Console-Image_3.0b3.118-20191231Apalis-TK1-Mainline_Console-Image_3.0b3.118-20200101
Currently imx-specific bootaux command doesn't support ELF format
firmware for Cortex-M4 core.
This patches introduces a PoC implementation of handling elf firmware
(load_elf_image_phdr() was copy-pasted from elf.c just for PoC).
This has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to handle
and load the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (Cortex A7/A9 cores).
This allows to boot firmwares from any location with just using
bootaux, e.g.:
> tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr}
Similar translation table can be found in the Linux remoteproc
driver [1].
[1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
(submitted upstream https://patchwork.ozlabs.org/patch/1202074/)
Diffstat (limited to 'arch/arm/mach-imx/mx7/soc.c')
| -rw-r--r-- | arch/arm/mach-imx/mx7/soc.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 1b4bbc5037..c140b02c3c 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -192,6 +192,34 @@ static void init_cpu_basic(void) #endif } +#ifdef CONFIG_IMX_BOOTAUX +/* + * Table of mappings of physical mem regions in both + * Cortex-A7 and Cortex-M4 address spaces. + * + * For additional details check sections 2.1.2 and 2.1.3 in + * i.MX7Dual Applications Processor Reference Manual + * + */ +const struct rproc_att hostmap[] = { + /* aux core , host core, size */ + { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */ + { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */ + { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */ + { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */ + { /* sentinel */ } +}; +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* enable all periherial can be accessed in nosec mode */ static void init_csu(void) |