diff options
| author | Tom Rini <trini@konsulko.com> | 2025-06-14 09:10:48 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-06-14 09:10:48 -0600 |
| commit | 03817a2a8046ea89dac2be72ce0c16a9faa5570b (patch) | |
| tree | b4d6f39f9b0ded094c7f54aeb135a9eae6e19492 /arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | |
| parent | 2556caa89caba6c3d4df7910828119bc65beb1f0 (diff) | |
| parent | 0230ad1c30a405c807dad5f78c95c57704234ffd (diff) | |
Merge patch series "Hex value prefix case cleanup"
E Shattow <e@freeshell.de> says:
Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.
There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
or placeholder in documentation and error messages.
External devicetree-rebasing dts/upstream and the generated code of
xilinx/zynq are ignored for the series.
Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/clock_manager_s10.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index 18921169a6d..5dcbda9473e 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -120,12 +120,12 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_PLLGLOB_PD_MASK 0x00000001 #define CLKMGR_PLLGLOB_RST_MASK 0x00000002 -#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0x3 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 #define CLKMGR_VCO_PSRC_EOSC1 0 #define CLKMGR_VCO_PSRC_INTOSC 1 #define CLKMGR_VCO_PSRC_F2S 2 -#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0x3f #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 #define CLKMGR_CLKSRC_MASK 0x7 @@ -152,7 +152,7 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 -#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3 +#define CLKMGR_NOCDIV_L4SPCLK_MASK 0x3 #define CLKMGR_NOCDIV_DIV1 0 #define CLKMGR_NOCDIV_DIV2 1 #define CLKMGR_NOCDIV_DIV4 2 |