diff options
| author | Tom Rini <trini@konsulko.com> | 2024-05-13 09:15:51 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-05-13 09:15:51 -0600 |
| commit | c8ffd1356d42223cbb8c86280a083cc3c93e6426 (patch) | |
| tree | 35be4e1f46e5b386c124483872c58611cd97fe6c /arch/arm/mach-versatile/timer.c | |
| parent | 2ee6f3a5f7550de3599faef9704e166e5dcace35 (diff) | |
| parent | 577373239a35afa865098741cf805f6176de8b16 (diff) | |
Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"
Roger Quadros <rogerq@kernel.org> says:
Sync AM62 device tree files with Linux v6.9 and
add in the missing bits in -u-boot.dtsi to get CPSW
Ethernet working.
CI testing: https://github.com/u-boot/u-boot/pull/534
Diffstat (limited to 'arch/arm/mach-versatile/timer.c')
| -rw-r--r-- | arch/arm/mach-versatile/timer.c | 62 |
1 files changed, 0 insertions, 62 deletions
diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c deleted file mode 100644 index b471412186d..00000000000 --- a/arch/arm/mach-versatile/timer.c +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> - */ - -#include <common.h> - -#define TIMER_ENABLE (1 << 7) -#define TIMER_MODE_MSK (1 << 6) -#define TIMER_MODE_FR (0 << 6) -#define TIMER_MODE_PD (1 << 6) - -#define TIMER_INT_EN (1 << 5) -#define TIMER_PRS_MSK (3 << 2) -#define TIMER_PRS_8S (1 << 3) -#define TIMER_SIZE_MSK (1 << 2) -#define TIMER_ONE_SHT (1 << 0) - -int timer_init (void) -{ - ulong tmr_ctrl_val; - - /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); - tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - - /* - * The Timer Control Register has one Undefined/Shouldn't Use Bit - * So we should do read/modify/write Operation - */ - - /* - * Timer Mode : Free Running - * Interrupt : Disabled - * Prescale : 8 Stage, Clk/256 - * Tmr Siz : 16 Bit Counter - * Tmr in Wrapping Mode - */ - tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); - tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); - tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - - *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - - return 0; -} |