diff options
| author | Tom Rini <trini@konsulko.com> | 2025-09-03 15:21:14 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-09-03 15:21:14 -0600 |
| commit | 76b8edbc732e327d1e56f08c641f51fdefdbff06 (patch) | |
| tree | ccece7062070bb0fb4a7ba7942a8a95dd0f8c06e /board/microsoft/surface-2/surface-2-spl.c | |
| parent | 8d2bde7af1f94ffb8e37ce79e941e0a30c9c896a (diff) | |
| parent | 392b5b426cfc40f94803688fe63f72d83d0a5e70 (diff) | |
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Branch contains minor improvents for ASUS SL101 and Jetson Nano along
with support for Microsoft Surface 2 tablet.
Diffstat (limited to 'board/microsoft/surface-2/surface-2-spl.c')
| -rw-r--r-- | board/microsoft/surface-2/surface-2-spl.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/board/microsoft/surface-2/surface-2-spl.c b/board/microsoft/surface-2/surface-2-spl.c new file mode 100644 index 00000000000..16f4373c7f0 --- /dev/null +++ b/board/microsoft/surface-2/surface-2-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Surface 2 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} |